Copied from ip_arria10_e2sg_ddio_<ddio_name>_1.vhd and changed technology name to ip_agi027_xxxx. Updated information header.

New IP version for iwave using Agilex 7 (agi027_xxxx) selected variant 10AX115U3F45E2SG. Based on ip_arria10_e2sg/ddio/compile_ip.tcl. Replaced information except description.

Copied from ip_arria10_e2sg/ddio/README.txt. This is file is not updated since ip_arria10. Updated information.

Updated information header. Added library ip_agi027_xxxx_ddio_lib; Added generate-block inclusive the instantiation of a module for the agi027_xxxx.

Updated information. Added component descriptions for ip_agi027_xxxx: ip_agi027_xxxx_ddio_in and ip_agi027_xxxx_ddio_out.

Added the library to hdl_lib_uses_synth for the ip_agi027_xxxx_ddio. Added ip_agi027_xxxx_ddio ip_agi027_xxxx_ddio_lib to hdl_lib_disclose_library_clause_names.

Copied from ip_arria10_e2sg_ddio_<ddio_name>.vhd and changed technology name to ip_agi027_xxxx. Verified it against generated/altera_gpio_2100/sim/ip_agi027_xxxx_ddio_<ddio_name>_altera_gpio_2100_<hash>.

Create new IPs with the same configuration as the ip_arria10_e2sg_ddio_<ddio_name>.ip. The version for the arria10_e2sg is 19.3.0 and for the agi027_xxxx is 21.0.0.

Porting fifo for Intel Agilex 7

Closes RTSD-180

See merge request !362

The README is fully adapted for the Agilex 7 and the most important results of the synthesis are reported.

Copied the ip_arria10_e2sg/fifo/ip_arria10_e2sg_<fifo_name>.vhd files. Updated information header. Changed the technology_name from ip_arria10_e2sg to ip_agi027_xxxx. Checked the differences between the underlying files where the original vhd file is based on. There are no significant differences. The parameters that are different are added and commented out. For <fifo_name>=dc_mixed_widths: In the range specification of std_logic_vectors within component ports, used_port'range is employed. However, for quicker referencing, it is preferable to specify the range in the same manner as with entity ports.

Create new IP's with the same configuration as the ip_arria10_e2sg_fifo_<fifo_name>.ip. The only difference is that it is a newer version. The version for the arria10_e2sg is 19.1.0 and for the agi027_xxxx is 19.2.1.

Copied from ip_arria10_e2sg/fifo/hdllib.cfg. Changed the technology_name from ip_arria10 to ip_agi027_xxxx for hdl_lib_name, hdl_library_clause_name, hdl_lib_technology, synth_files. Removed the IPs under qsys-generate_ip_libs.

Updated information header. Added library ip_agi027_xxxx_fifo_lib; Added generate-block inclusive instantiation of module for the agi027_xxxx

Updated information header to recent standard. Added component descriptions for agi027_xxxx: ip_agi027_xxxx_fifo_sc, ip_agi027_xxxx_fifo_dc, ip_agi027_xxxx_fifo_dc_mixed_widths.

Added the library to hdl_lib_uses_synth for the ip_agi027_xxxx. Added ip_agi027_xxxx_fifo ip_agi027_xxxx_fifo_lib to hdl_lib_disclose_library_clause_names.

Porting multipliers: mult, mult_add2, mult_add4, complex_mult, complex_mult_rtl, complex_mult_rtl_canonical for Intel Agilex 7

Closes RTSD-182

See merge request !361

Changed gnu to apache and or removed '(C)' and or added space(s) in info header. Removed --LIBRARY rules.

Added to hdl_lib_uses_synth the six libraries for the ip_agi027_xxxx. Added to hdl_lib_disclose_library_clause_names the five for the ip_agi027_xxxx, except complex_mult_rtl_cononical, because this one is also not added for other technologies.

Replaced information header to recent standard. Added component descriptions for agi027_xxxx: ip_agi027_xxxx_mult, ip_agi027_xxxx_mult_rtl, ip_agi027_xxxx_mult_add4_rtl, ip_agi027_xxxx_complex_mult_rtl, ip_agi027_xxxx_complex_mult_rtl_canonical, ip_agi027_xxxx_complex_mult, ip_agi027_xxxx_complex_mult_27.

Updated headerinformation to recent standard. Added two constants c_tech_mult_agi027_xxxx_rtl and c_tech_mult_agi027_xxxx_ip for the Agilex 7 to this package.

Updated headerinformation to recent standard. There is a small error in the header information, namely “The largest pi = 2 * min**2 = 2**(c_dsp_dat_w-1) …” is not the right equation. It should be = 2**(c_dsp_prod_w-1) or = 2 * ((-2)**(c_dsp_dat_w-1))**2, and that is equal to = (-2)**(2*(c_dsp_dat_w-1)) = 2* 4*(c_dsp_dat_w-1). I updated it to 2**(c_dsp_prod_w-1). Added five (extra) libraries with two commented out: --LIBRARY ip_agi027_xxxx_mult_lib; --LIBRARY ip_agi027_xxxx_mult_rtl_lib; library ip_agi027_xxxx_complex_mult_altmult_complex_1910; library ip_agi027_xxxx_complex_mult_rtl_lib; library ip_agi027_xxxx_complex_mult_rtl_canonical_lib; Add generate-block inclusive the instantiation of a module for the agi027_xxxx: -- IP variants for <= 18 bit: ip_agi027_xxxx_complex_mult -- IP variants for > 18 bit and <= 27 bit: ip_agi027_xxxx_complex_mult_27b -- RTL variants that can infer multipliers for a technology, fits all widths: ip_agi027_xxxx_complex_mult_rtl -- RTL variants that can infer multipliers for a technology, fits all widths: ip_agi027_xxxx_complex_mult_rtl_canonical.

Replaced information header to recent standard. Added library ip_agi027_xxxx_mult_add4_lib; Added generate-block inclusive the instantiation of a module for the ip_agi027_xxxx_mult_add4_rtl.

Replaced information header to recent standard. Added library ip_agi027_xxxx_mult_add2_lib; Added generate-block inclusive the instantiation of a module for the ip_agi027_xxxx_mult_add2_rtl.

Updated information header to recent standard. Added library ip_agi027_xxxx_mult_lib. Added generate-block inclusive the instantiation of a module for the ip_agi027_xxxx_mult and for the ip_agi027_mult_rtl.

Copied from ip_arria10_e2sg/mult_add2/hdllib.cfg. Changed the technology_name from ip_arria10_e2sg to ip_agi027_xxxx for hdl_lib_name, hdl_library_clause_name, hdl_lib_technology, synth_files.

Copied from ip_arria10_e2sg/mult_add2/ip_arria10_e2sg_mult_add2_rtl.vhd. Replaced information header. Changed the technology_name from ip_arria10_e2sg to ip_agi027_xxxx.

Copied from ip_arria10/complex_mult_rtl_canonical/hdllib.cfg. Changed the technology_name from ip_arria10 to ip_agi027_xxxx for hdl_lib_name, hdl_library_clause_name, hdl_lib_technology (must kept empty), synth_files.