Copied the ip_arria10_e2sg/fifo/ip_arria10_e2sg_<fifo_name>.vhd files. Updated...

Copied the ip_arria10_e2sg/fifo/ip_arria10_e2sg_<fifo_name>.vhd files. Updated information header. Changed the technology_name from ip_arria10_e2sg to ip_agi027_xxxx. Checked the differences between the underlying files where the original vhd file is based on. There are no significant differences. The parameters that are different are added and commented out. For <fifo_name>=dc_mixed_widths: In the range specification of std_logic_vectors within component ports, used_port'range is employed. However, for quicker referencing, it is preferable to specify the range in the same manner as with entity ports.