Updated headerinformation to recent standard. There is a small error in the...

Updated headerinformation to recent standard. There is a small error in the header information, namely “The largest pi = 2 * min**2 = 2**(c_dsp_dat_w-1) …” is not the right equation. It should be = 2**(c_dsp_prod_w-1) or = 2 * ((-2)**(c_dsp_dat_w-1))**2, and that is equal to = (-2)**(2*(c_dsp_dat_w-1)) = 2* 4*(c_dsp_dat_w-1). I updated it to 2**(c_dsp_prod_w-1). Added five (extra) libraries with two commented out: --LIBRARY ip_agi027_xxxx_mult_lib; --LIBRARY ip_agi027_xxxx_mult_rtl_lib; library ip_agi027_xxxx_complex_mult_altmult_complex_1910; library ip_agi027_xxxx_complex_mult_rtl_lib; library ip_agi027_xxxx_complex_mult_rtl_canonical_lib; Add generate-block inclusive the instantiation of a module for the agi027_xxxx: -- IP variants for <= 18 bit: ip_agi027_xxxx_complex_mult -- IP variants for > 18 bit and <= 27 bit: ip_agi027_xxxx_complex_mult_27b -- RTL variants that can infer multipliers for a technology, fits all widths: ip_agi027_xxxx_complex_mult_rtl -- RTL variants that can infer multipliers for a technology, fits all widths: ip_agi027_xxxx_complex_mult_rtl_canonical.

libraries/technology/mult/tech_complex_mult.vhd

 -------------------------------------------------------------------------------
 --
--- Copyright (C) 2009
+-- Copyright (C) 2009-2023
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
@@ -20,6 +20,7 @@
 -------------------------------------------------------------------------------
 --
 -- Author : E. Kooistra
+-- Changed by : D.F. Brouwer
 -- Purpose : Wrapper for complex multiplier IP
 -- Decription :
 --
@@ -42,7 +43,7 @@
 --   The largest value for pi = min**2 + min**2.
 --   The largest value for pr = min**2 - min*max < largest pi.
 --
---   The largest pi = 2 * min**2 = 2**(c_dsp_dat_w-1), so it just does not
+--   The largest pi = 2 * min**2 = 2**(c_dsp_prod_w-1), so it just does not
 --   fit in c_dsp_prod_w, but largest pi - 1 = 2**(c_dsp_dat_w-1) - 1 does
 --   fit, so all other input values fit. In DSP systems the input value
 --   (min + j*min) typically never occurs.
@@ -64,12 +65,17 @@ use work.tech_mult_component_pkg.all;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 library ip_stratixiv_mult_lib;
 --LIBRARY ip_arria10_mult_lib;
+--LIBRARY ip_agi027_xxxx_mult_lib;
 --LIBRARY ip_arria10_mult_rtl_lib;
+--LIBRARY ip_agi027_xxxx_mult_rtl_lib;
 library ip_arria10_complex_mult_altmult_complex_150;
 library ip_arria10_e1sg_complex_mult_altmult_complex_180;
 library ip_arria10_e2sg_complex_mult_altmult_complex_1910;
+library ip_agi027_xxxx_complex_mult_altmult_complex_1910;
 library ip_arria10_complex_mult_rtl_lib;
+library ip_agi027_xxxx_complex_mult_rtl_lib;
 library ip_arria10_complex_mult_rtl_canonical_lib;
+library ip_agi027_xxxx_complex_mult_rtl_canonical_lib;
 
 entity tech_complex_mult is
   generic (
@@ -212,6 +218,31 @@ begin
     result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
   end generate;
 
+  gen_ip_agi027_xxxx_ip : if g_variant = "IP" and g_technology = c_tech_agi027_xxxx and c_dsp_dat_w <= c_dsp_mult_18_w generate
+    -- Adapt DSP input widths
+    ar <= RESIZE_SVEC(in_ar, c_dsp_mult_18_w);
+    ai <= RESIZE_SVEC(in_ai, c_dsp_mult_18_w);
+    br <= RESIZE_SVEC(in_br, c_dsp_mult_18_w);
+    bi <= RESIZE_SVEC(in_bi, c_dsp_mult_18_w) when g_conjugate_b = false else TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_18_w);
+
+    u0 : ip_agi027_xxxx_complex_mult
+    port map (
+      aclr        => rst,
+      clock       => clk,
+      dataa_imag  => ai,
+      dataa_real  => ar,
+      datab_imag  => bi,
+      datab_real  => br,
+      ena         => clken,
+      result_imag => mult_im,
+      result_real => mult_re
+    );
+
+    -- Back to true input widths and then resize for output width
+    result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
+    result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
+  end generate;
+
   -----------------------------------------------------------------------------
   -- IP variants for > 18 bit and <= 27 bit
   -----------------------------------------------------------------------------
@@ -266,6 +297,31 @@ begin
     result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
   end generate;
 
+  gen_ip_agi027_xxxx_ip_27b : if g_variant = "IP" and g_technology = c_tech_agi027_xxxx and c_dsp_dat_w > c_dsp_mult_18_w and c_dsp_dat_w <= c_dsp_mult_27_w generate
+    -- Adapt DSP input widths
+    ar <= RESIZE_SVEC(in_ar, c_dsp_mult_27_w);
+    ai <= RESIZE_SVEC(in_ai, c_dsp_mult_27_w);
+    br <= RESIZE_SVEC(in_br, c_dsp_mult_27_w);
+    bi <= RESIZE_SVEC(in_bi, c_dsp_mult_27_w) when g_conjugate_b = false else TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_27_w);
+
+    u0 : ip_agi027_xxxx_complex_mult_27b
+    port map (
+      aclr        => rst,
+      clock       => clk,
+      dataa_imag  => ai,
+      dataa_real  => ar,
+      datab_imag  => bi,
+      datab_real  => br,
+      ena         => clken,
+      result_imag => mult_im,
+      result_real => mult_re
+    );
+
+    -- Back to true input widths and then resize for output width
+    result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
+    result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
+  end generate;
+
   -----------------------------------------------------------------------------
   -- RTL variants that can infer multipliers for a technology, fits all widths
   -----------------------------------------------------------------------------
@@ -328,7 +384,6 @@ begin
   gen_ip_arria10_rtl_canonical : if g_variant = "RTL_C" and (g_technology = c_tech_arria10_proto or
                                                            g_technology = c_tech_arria10_e3sge3 or
                                                            g_technology = c_tech_arria10_e1sg or
-
                                                            g_technology = c_tech_arria10_e2sg) generate
     -- support g_conjugate_b
     bi <= in_bi when g_conjugate_b = false else TO_SVEC(-TO_SINT(in_bi), g_in_b_w);
@@ -356,4 +411,58 @@ begin
     );
   end generate;
 
+  -- RTL variant is for iwave
+  gen_ip_agi027_xxxx_rtl : if g_variant = "RTL" and (g_technology = c_tech_agi027_xxxx) generate
+    u0 : ip_agi027_xxxx_complex_mult_rtl
+    generic map (
+      g_in_a_w           => g_in_a_w,
+      g_in_b_w           => g_in_b_w,
+      g_out_p_w          => g_out_p_w,
+      g_conjugate_b      => g_conjugate_b,
+      g_pipeline_input   => g_pipeline_input,
+      g_pipeline_product => g_pipeline_product,
+      g_pipeline_adder   => g_pipeline_adder,
+      g_pipeline_output  => g_pipeline_output
+    )
+    port map (
+      rst        => rst,
+      clk        => clk,
+      clken      => clken,
+      in_ar      => in_ar,
+      in_ai      => in_ai,
+      in_br      => in_br,
+      in_bi      => in_bi,
+      result_re  => result_re,
+      result_im  => result_im
+    );
+  end generate;
+
+  -- RTL variant is for iwave
+  gen_ip_agi027_xxxx_rtl_canonical : if g_variant = "RTL_C" and (g_technology = c_tech_agi027_xxxx) generate
+    -- support g_conjugate_b
+    bi <= in_bi when g_conjugate_b = false else TO_SVEC(-TO_SINT(in_bi), g_in_b_w);
+
+    u0 : ip_agi027_xxxx_complex_mult_rtl_canonical
+    generic map (
+      g_in_a_w           => g_in_a_w,
+      g_in_b_w           => g_in_b_w,
+      g_out_p_w          => g_out_p_w,
+      g_pipeline_input   => g_pipeline_input,
+      g_pipeline_product => g_pipeline_product,
+      g_pipeline_adder   => g_pipeline_adder,
+      g_pipeline_output  => g_pipeline_output
+    )
+    port map (
+      rst        => rst,
+      clk        => clk,
+      clken      => clken,
+      in_ar      => in_ar,
+      in_ai      => in_ai,
+      in_br      => in_br,
+      in_bi      => bi,
+      result_re  => result_re,
+      result_im  => result_im
+    );
+  end generate;
+
 end str;