Copied from ip_arria10_e2sg/fifo/hdllib.cfg. Changed the technology_name from...

Copied from ip_arria10_e2sg/fifo/hdllib.cfg. Changed the technology_name from ip_arria10 to ip_agi027_xxxx for hdl_lib_name, hdl_library_clause_name, hdl_lib_technology, synth_files. Removed the IPs under qsys-generate_ip_libs.

libraries/technology/ip_agi027_xxxx/fifo/hdllib.cfg

+hdl_lib_name = ip_agi027_xxxx_fifo
+hdl_library_clause_name = ip_agi027_xxxx_fifo_lib
+hdl_lib_uses_synth = technology
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_agi027_xxxx
+
+synth_files =
+    ip_agi027_xxxx_fifo_sc.vhd
+    ip_agi027_xxxx_fifo_dc.vhd
+    ip_agi027_xxxx_fifo_dc_mixed_widths.vhd
+    
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+synth_top_level_entity = 
+
+quartus_qsf_files =
+
+
+[generate_ip_libs]
+qsys-generate_ip_files =