Updated information header to recent standard. Added component descriptions...

Updated information header to recent standard. Added component descriptions for agi027_xxxx: ip_agi027_xxxx_fifo_sc, ip_agi027_xxxx_fifo_dc, ip_agi027_xxxx_fifo_dc_mixed_widths.

libraries/technology/fifo/tech_fifo_component_pkg.vhd

 -- -----------------------------------------------------------------------------
 --
--- Copyright (C) 2014
+-- Copyright 2014-2023
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
 --
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
 --
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
 --
 -- -----------------------------------------------------------------------------
-
--- Purpose: IP components declarations for various devices that get wrapped by the tech components
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
+-- Purpose: 
+--   IP components declarations for various devices that get wrapped by the tech components
 
 library IEEE, technology_lib;
 use IEEE.std_logic_1164.all;
@@ -413,4 +415,69 @@ package tech_fifo_component_pkg is
   );
   end component;
 
+  -----------------------------------------------------------------------------
+  -- ip_agi027_xxxx
+  -----------------------------------------------------------------------------
+
+  component ip_agi027_xxxx_fifo_sc is
+  generic (
+    g_use_eab   : string := "ON";
+    g_dat_w     : natural := 20;
+    g_nof_words : natural := 1024
+  );
+  port (
+    aclr    : in std_logic;
+    clock   : in std_logic;
+    data    : in std_logic_vector(g_dat_w - 1 downto 0);
+    rdreq   : in std_logic;
+    wrreq   : in std_logic;
+    empty   : out std_logic;
+    full    : out std_logic;
+    q       : out std_logic_vector(g_dat_w - 1 downto 0);
+    usedw   : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
+  );
+  end component;
+
+  component ip_agi027_xxxx_fifo_dc is
+  generic (
+    g_use_eab   : string := "ON";
+    g_dat_w     : natural := 20;
+    g_nof_words : natural := 1024
+  );
+  port (
+    aclr    : in std_logic  := '0';
+    data    : in std_logic_vector(g_dat_w - 1 downto 0);
+    rdclk   : in std_logic;
+    rdreq   : in std_logic;
+    wrclk   : in std_logic;
+    wrreq   : in std_logic;
+    q       : out std_logic_vector(g_dat_w - 1 downto 0);
+    rdempty : out std_logic;
+    rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0);
+    wrfull  : out std_logic;
+    wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
+  );
+  end component;
+
+  component ip_agi027_xxxx_fifo_dc_mixed_widths is
+  generic (
+    g_nof_words : natural := 1024;  -- FIFO size in nof wr_dat words
+    g_wrdat_w   : natural := 20;
+    g_rddat_w   : natural := 10
+  );
+  port (
+    aclr    : in std_logic  := '0';
+    data    : in std_logic_vector(g_wrdat_w - 1 downto 0);
+    rdclk   : in std_logic;
+    rdreq   : in std_logic;
+    wrclk   : in std_logic;
+    wrreq   : in std_logic;
+    q       : out std_logic_vector(g_rddat_w - 1 downto 0);
+    rdempty : out std_logic;
+    rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words * g_wrdat_w / g_rddat_w) - 1 downto 0);
+    wrfull  : out std_logic;
+    wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
+  );
+  end component;
+
 end tech_fifo_component_pkg;