Commented modelsim_compile_ip_files because there is no simulation model for the FPGA voltage sensor IP.

from ddr4 testing version ddr4_micron_46)

Updated all IP related files to match Quartus 15.0 which uses libraries with _150 in their names instead of -141.

Upgraded Arria10 Qsys IP components to Quartus 15.0 and set device family to 10AX115U4F45I3SGES for UniBoard2 v0

(MCGB) (x6/xN)

Added ip_arria10_transceiver_reset_controller_24.qsys that generates a component with transceiver reset controller for 24 transceivers.

Renamed key hdl_lib_uses into hdl_lib_uses_synth and added new key hdl_lib_uses_sim for extra test_bench_files library dependencies.

Generated file is in sim/ not in sim/mentor this difference occurs when the GUI is use with not the same settings as the generate_ip.sh.

The IP is generated with  --allow-mixed-language-simulation option, this affects the paths in the msim_setup.tcl and therefore the compile_ip.tcl