Commits · de83af40f39642a11d9e12df2d9566bd7df81b55 · RTSD / HDL · GitLab

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Jun 14, 2023
- RTSD-93 , master with all style fixes · de83af40
  Pieter Donker authored 2 years ago
  
  de83af40
May 11, 2023
- Define ddr_gigabytes as integer to be able to represent both > 1GB (HW) and < 1GB (sim) sizes. · aac5f892
  Eric Kooistra authored 2 years ago
  
  aac5f892
Apr 08, 2015
- Removed internal DDR memory model (now needs to be instantiated in tb). Use... · 8e1a6162
  Eric Kooistra authored 10 years ago
  8e1a6162
Mar 25, 2015
- Updated description of g_sim. · fc437369
  Eric Kooistra authored 10 years ago
  
  fc437369
Feb 20, 2015
- Added g_sim because memory model should not be included in the synthesis · b02115b8
  Zanting authored 10 years ago
  
  b02115b8
Jan 20, 2015
- Added 4GByte DDR4 memory model for 1600 Mtransfers/s. · 30bdacdd
  Eric Kooistra authored 10 years ago
  
  30bdacdd
Jan 06, 2015
- set MEM_TRCD=6 to avoid timing error message in simulation. · 34014215
  Eric Kooistra authored 10 years ago
  
  34014215
Dec 22, 2014
- Corrected dqs_n connection. · 64542894
  Eric Kooistra authored 10 years ago
  
  64542894
Dec 19, 2014
- Added ddr3 memory model for simulation. The model comes from an example design in ip_stratixiv · bc5e1243
  Eric Kooistra authored 10 years ago
  
  bc5e1243