Commits · dccde9ef535b89ff6e279f7122dd45c7a98745c3 · RTSD / HDL · GitLab

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Jul 25, 2017
- edited hdllib.cfg and the vhd files of several technology libraries to · dccde9ef
  Reinier van der Walle authored 7 years ago
  dccde9ef
Feb 15, 2017
- Modify technology wrappers to include unb2b FPGA Arria 10 version e1sg · e50aab24
  Jonathan Hargreaves authored 8 years ago
  
  e50aab24
May 11, 2016
- Added missing library declaration for ip_arria10_e3sge3_ddr4_8g_2400_altera_emif_151 · 691fe3ed
  Eric Kooistra authored 8 years ago
  
  691fe3ed
Mar 11, 2016
- fix duplicate drivers in wrapper · 044030e0
  Jonathan Hargreaves authored 9 years ago
  
  044030e0
Mar 10, 2016
- add ddr4_8g_1600 to packages and wrappers · eecc4c7e
  Jonathan Hargreaves authored 9 years ago
  
  eecc4c7e
Jan 29, 2016
- update technology wrapper to include device e3sge3 for unb2a · 16efe183
  Jonathan Hargreaves authored 9 years ago
  
  16efe183
Sep 25, 2015
- can choose now ddr4 1600 or 2000 · fda9eccc
  Kenneth Hiemstra authored 9 years ago
  
  fda9eccc
Aug 18, 2015
- added ddr4_4g_2000 IP · 08d9a16e
  Kenneth Hiemstra authored 9 years ago
  
  08d9a16e
Aug 13, 2015
- using a dual rank DDR4 but the IP is single rank: disabling 2nd rank by · 0e2b1046
  Kenneth Hiemstra authored 9 years ago
  0e2b1046
Jun 12, 2015
- Connected cal_ok and cal_fail.diff · c85011f5
  Eric Kooistra authored 9 years ago
  
  c85011f5
May 20, 2015
- Updated all IP related files to match Quartus 15.0 which uses libraries with... · 6237fca5
  Eric Kooistra authored 9 years ago
  6237fca5
Apr 08, 2015
- Removed internal DDR memory model (now needs to be instantiated in tb). Use... · 8e1a6162
  Eric Kooistra authored 10 years ago
  8e1a6162
- Rename ctlr_ref_clk into ref_clk to have simpler and more clear name. · f1cda4e0
  Eric Kooistra authored 10 years ago
  
  f1cda4e0
Feb 05, 2015
- svn added missing file. · 6a945baf
  Eric Kooistra authored 10 years ago
  
  6a945baf