Added g_sim, when TRUE then use internal DDR memory model in tech_ddr component. When FALSE use DDR memory model in test bench.

Only need to reset the state reg, do not reset the other signals to easy timing closure. Use natural for burst_wr_cnt instead of slv.

Define t_mem_ctlr_mosi/miso in common_mem_pkg, to use that instead of the records defined in tech_ddr_pkg. Also remove t_tech_ddr_addr record because it is not needed.

Check UNSIGNED(wr_fifo_usedw) < c_dp_factor, because a mixed width FIFO cannot always be flushed completely empty, which is ok.diff