node2 has the tempsensors (not node3)

boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd

@@ -82,7 +82,7 @@ BEGIN
     sla_out      => reg_miso,
     
     -- MM registers
-    sens_err     => sens_err,  -- using same protocol list for both node3 and all nodes implies that sens_err is only valid for node3.
+    sens_err     => sens_err,  -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
     sens_data    => sens_data,
 
     -- Max temp threshold

boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd

@@ -31,8 +31,7 @@ PACKAGE unb2_board_pkg IS
   -- UniBoard
   CONSTANT c_unb2_board_nof_node             : NATURAL := 4;                     -- number of nodes on UniBoard
   CONSTANT c_unb2_board_nof_node_w           : NATURAL := 2;                     -- = ceil_log2(c_unb2_board_nof_node)
-  CONSTANT c_unb2_board_nof_pn               : NATURAL := c_unb2_board_nof_node; -- nof Processing Node FPGAs on UniBoard
-  CONSTANT c_unb2_board_nof_chip             : NATURAL := c_unb2_board_nof_pn;   -- = 4
+  CONSTANT c_unb2_board_nof_chip             : NATURAL := c_unb2_board_nof_node; -- = 4
   CONSTANT c_unb2_board_nof_chip_w           : NATURAL := 2;                     -- = ceil_log2(c_unb2_board_nof_chip)
   CONSTANT c_unb2_board_nof_ddr              : NATURAL := 2;                     -- each node has 2 DDR modules
   
@@ -128,7 +127,7 @@ PACKAGE unb2_board_pkg IS
     bck_id   : NATURAL;  -- = id[7:2], ID part from back plane
     chip_id  : NATURAL;  -- = id[1:0], ID part from UniBoard
     node_id  : NATURAL;  -- = id[1:0], node ID: 0, 1, 2 or 3
-    is_node3 : NATURAL;  -- 1 for Node 3, else 0.
+    is_node2 : NATURAL;  -- 1 for Node 2, else 0.
   END RECORD;
 
   FUNCTION func_unb2_board_system_info(VERSION : IN STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0);
@@ -148,7 +147,7 @@ PACKAGE BODY unb2_board_pkg IS
     v_system_info.bck_id  := TO_INTEGER(UNSIGNED(ID(7 DOWNTO 2)));
     v_system_info.chip_id := TO_INTEGER(UNSIGNED(ID(1 DOWNTO 0)));
     v_system_info.node_id := TO_INTEGER(UNSIGNED(ID(1 DOWNTO 0)));
-    IF UNSIGNED(ID(1 DOWNTO 0))=3 THEN v_system_info.is_node3 := 1; ELSE v_system_info.is_node3 := 0; END IF;
+    IF UNSIGNED(ID(1 DOWNTO 0))=2 THEN v_system_info.is_node2 := 1; ELSE v_system_info.is_node2 := 0; END IF;
     RETURN v_system_info;
   END;
   

boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_reg.vhd

@@ -52,11 +52,11 @@
 -- ==> 
 --   Via all nodes:
 --   0 = FPGA temperature                 = TInt8(fpga_temp)
---   Only via node3:
+--   Only via node2:
 --   1 = UniBoard ETH PHY temperature     = TInt8(eth_temp)
 --   2 = UniBoard hot swap supply current = hot_swap_v_sense * SENS_HOT_SWAP_I_UNIT_SENSE
 --   3 = UniBoard hot swap supply voltage = hot_swap_v_source * SENS_HOT_SWAP_V_UNIT_SOURCE
---   4 = I2C error status for node3 sensors access only, 0 = ok
+--   4 = I2C error status for node2 sensors access only, 0 = ok
 --   
 
 LIBRARY IEEE, common_lib;
@@ -150,7 +150,7 @@ BEGIN
         IF vA < g_sens_nof_result THEN
           sla_out.rddata <= RESIZE_MEM_DATA(sens_data(vA)(c_byte_w-1 DOWNTO 0));
         ELSIF vA = g_sens_nof_result THEN
-          sla_out.rddata(0) <= sens_err;   -- only valid for node3
+          sla_out.rddata(0) <= sens_err;   -- only valid for node2
         ELSE
           sla_out.rddata(6 DOWNTO 0) <= i_temp_high; 
         END IF;

boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd

@@ -43,7 +43,7 @@ ENTITY unb2_board_system_info IS
     bck_id      : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_uniboard_w-1 DOWNTO 0); -- ID[7:2]
     chip_id     : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_chip_w-1 DOWNTO 0);     -- ID[1:0]
     node_id     : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_node_w-1 DOWNTO 0);     -- ID[1:0]
-    is_node3    : OUT STD_LOGIC   -- '1' for Node 3, else '0'.
+    is_node2    : OUT STD_LOGIC   -- '1' for Node 2, else '0'.
   );
 END unb2_board_system_info;
 
@@ -59,7 +59,7 @@ ARCHITECTURE str OF unb2_board_system_info IS
   SIGNAL nxt_bck_id     : STD_LOGIC_VECTOR(bck_id'RANGE);
   SIGNAL nxt_chip_id    : STD_LOGIC_VECTOR(chip_id'RANGE);
   SIGNAL nxt_node_id    : STD_LOGIC_VECTOR(node_id'RANGE);
-  SIGNAL nxt_is_node3   : STD_LOGIC;
+  SIGNAL nxt_is_node2   : STD_LOGIC;
   
 BEGIN
 
@@ -74,7 +74,7 @@ BEGIN
       bck_id         <= nxt_bck_id;
       chip_id        <= nxt_chip_id;
       node_id        <= nxt_node_id;
-      is_node3       <= nxt_is_node3;
+      is_node2       <= nxt_is_node2;
     END IF;
   END PROCESS;
   
@@ -93,6 +93,6 @@ BEGIN
   nxt_bck_id   <= id_reg(7 DOWNTO 2);
   nxt_chip_id  <= id_reg(1 DOWNTO 0);
   nxt_node_id  <= id_reg(1 DOWNTO 0);
-  nxt_is_node3 <= '1' WHEN TO_UINT(id_reg(1 DOWNTO 0)) = 3 ELSE '0';
+  nxt_is_node2 <= '1' WHEN TO_UINT(id_reg(1 DOWNTO 0)) = 2 ELSE '0';
   
 END str;