Commits · a0a9e860ebcaab67c3493f5c060499967309e4d9 · RTSD / HDL · GitLab

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Apr 08, 2015
- Removed internal DDR memory model (now needs to be instantiated in tb). Use... · 8e1a6162
  Eric Kooistra authored Apr 8, 2015
  8e1a6162
Mar 25, 2015
- Updated description of g_sim. · fc437369
  Eric Kooistra authored Mar 25, 2015
  
  fc437369
Feb 20, 2015
- Added g_sim because memory model should not be included in the synthesis · b02115b8
  Zanting authored Feb 20, 2015
  
  b02115b8
Jan 20, 2015
- Added 4GByte DDR4 memory model for 1600 Mtransfers/s. · 30bdacdd
  Eric Kooistra authored Jan 20, 2015
  
  30bdacdd
Jan 06, 2015
- set MEM_TRCD=6 to avoid timing error message in simulation. · 34014215
  Eric Kooistra authored Jan 6, 2015
  
  34014215
Dec 22, 2014
- Corrected dqs_n connection. · 64542894
  Eric Kooistra authored Dec 22, 2014
  
  64542894
Dec 19, 2014
- Added ddr3 memory model for simulation. The model comes from an example design in ip_stratixiv · bc5e1243
  Eric Kooistra authored Dec 19, 2014
  
  bc5e1243