Added draft src/vhdl/mms_io_ddr_diag.vhd, it intstantiates the BG, DB and IO_DDR as is and it compiles.

-Defaulted BG en_sync to '1' in sim.

Section 8.10.4:
* Described 10 G Tx‐only interface between UniBoard and GPU for SC3.
* It may appear possible to have SC3 commensal with Apertif X, but it is not possible to say until more actual implementation resource usage figures are available.
* Described option of having 16 extra UniBoards (or 4 extra UniBoard2) dedicated for Arts.
* Added conclusion that all four SC of Arts will use the Uniboards to connect to the Apertif BF.

-Reduced BG output block size to 2*64.

-Also committed generated hex files.

 quartus_sdc_files =
    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc

 quartus_sdc_files =
    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc

Added sections on:
. Bsub=1 MHz change request
. TAB, IAB data processing relations
. CB12, TAB-1/12/444, IAB-37 output
. DSP resource usage (multipliers, RAM)

-Fixed BG address width;
-(also committing myhdl_mms_diag_block_gen.py, just to sync SVN)

Added quartus_sdc_files. No need to have ip_stratixiv_ddr3_uphy_4g_800_master.qip at quartus_qip_files key, because it already gets included via the *_lib.qip.

 . 375 32b words of BG data per packet;
 . IP and UDP lengths have been set accordingly;
 . Tested using BG revision targeting dop17;
 . Data rate: ~650Mbps.