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Commit 90357056 authored by Daniel van der Schuur's avatar Daniel van der Schuur
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-Increased packet size to ~1500 bytes 

 . 375 32b words of BG data per packet;
 . IP and UDP lengths have been set accordingly;
 . Tested using BG revision targeting dop17;
 . Data rate: ~650Mbps.
parent be6c10fc
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applications/compaan/designs/compaan_unb1_dp_offload/quartus/sopc_compaan_unb1_dp_offload.sopc
+ 58
− 58
View file @ 90357056
...@@ -100,48 +100,51 @@ ...@@ -100,48 +100,51 @@
type = "String"; type = "String";
} }
} }
element reg_dp_offload_tx_hdr_dat.mem element reg_dp_offload_tx.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "256"; value = "1176";
type = "long"; type = "long";
} }
} }
element ram_diag_bg.mem element reg_dp_offload_tx_hdr_dat.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "8192"; value = "256";
type = "long"; type = "long";
} }
} }
element reg_dp_offload_tx_hdr_ovr.mem element reg_diag_bg.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "128"; value = "1088";
type = "long"; type = "long";
} }
} }
element pio_system_info.mem element reg_dp_offload_rx_hdr_dat.mem
{ {
datum _lockedAddress datum baseAddress
{ {
value = "1"; value = "512";
type = "boolean"; type = "long";
} }
}
element reg_bsn_monitor.mem
{
datum baseAddress datum baseAddress
{ {
value = "0"; value = "896";
type = "long"; type = "long";
} }
} }
element ram_diag_data_buffer.mem element reg_compaan.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "65536"; value = "2097152";
type = "long"; type = "long";
} }
} }
...@@ -166,64 +169,61 @@ ...@@ -166,64 +169,61 @@
type = "long"; type = "long";
} }
} }
element reg_diag_data_buffer.mem element ram_diag_data_buffer.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "768"; value = "65536";
type = "long"; type = "long";
} }
} }
element reg_compaan.mem element reg_dp_offload_tx_hdr_ovr.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "2097152"; value = "128";
type = "long"; type = "long";
} }
} }
element reg_dp_offload_rx_hdr_dat.mem element reg_diag_data_buffer.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "512"; value = "768";
type = "long"; type = "long";
} }
} }
element reg_diag_bg.mem element reg_wdi.mem
{ {
datum baseAddress datum _lockedAddress
{ {
value = "1088"; value = "1";
type = "long"; type = "boolean";
}
} }
element reg_bsn_monitor.mem
{
datum baseAddress datum baseAddress
{ {
value = "896"; value = "12288";
type = "long"; type = "long";
} }
} }
element reg_dp_offload_tx.mem element pio_system_info.mem
{ {
datum _lockedAddress
{
value = "1";
type = "boolean";
}
datum baseAddress datum baseAddress
{ {
value = "1176"; value = "0";
type = "long"; type = "long";
} }
} }
element reg_wdi.mem element ram_diag_bg.mem
{
datum _lockedAddress
{ {
value = "1";
type = "boolean";
}
datum baseAddress datum baseAddress
{ {
value = "12288"; value = "16384";
type = "long"; type = "long";
} }
} }
...@@ -231,7 +231,7 @@ ...@@ -231,7 +231,7 @@
{ {
datum baseAddress datum baseAddress
{ {
value = "20480"; value = "32768";
type = "long"; type = "long";
} }
} }
...@@ -247,7 +247,7 @@ ...@@ -247,7 +247,7 @@
{ {
datum baseAddress datum baseAddress
{ {
value = "16384"; value = "8192";
type = "long"; type = "long";
} }
} }
...@@ -410,19 +410,11 @@ ...@@ -410,19 +410,11 @@
type = "int"; type = "int";
} }
} }
element timer_0.s1 element pio_wdi.s1
{
datum baseAddress
{
value = "1024";
type = "long";
}
}
element pio_debug_wave.s1
{ {
datum baseAddress datum baseAddress
{ {
value = "1136"; value = "1152";
type = "long"; type = "long";
} }
} }
...@@ -439,11 +431,19 @@ ...@@ -439,11 +431,19 @@
type = "long"; type = "long";
} }
} }
element pio_wdi.s1 element pio_debug_wave.s1
{ {
datum baseAddress datum baseAddress
{ {
value = "1152"; value = "1136";
type = "long";
}
}
element timer_0.s1
{
datum baseAddress
{
value = "1024";
type = "long"; type = "long";
} }
} }
...@@ -470,10 +470,10 @@ ...@@ -470,10 +470,10 @@
<parameter name="globalResetBus" value="true" /> <parameter name="globalResetBus" value="true" />
<parameter name="hdlLanguage" value="VHDL" /> <parameter name="hdlLanguage" value="VHDL" />
<parameter name="maxAdditionalLatency" value="0" /> <parameter name="maxAdditionalLatency" value="0" />
<parameter name="projectName">compaan_unb1_dp_offload.qpf</parameter> <parameter name="projectName">compaan_unb1_dp_offload_bg.qpf</parameter>
<parameter name="sopcBorderPoints" value="true" /> <parameter name="sopcBorderPoints" value="true" />
<parameter name="systemHash" value="-46914647588" /> <parameter name="systemHash" value="-44851155349" />
<parameter name="timeStamp" value="1426597100710" /> <parameter name="timeStamp" value="1433916452709" />
<parameter name="useTestBenchNamingPattern" value="false" /> <parameter name="useTestBenchNamingPattern" value="false" />
<module kind="clock_source" version="11.1" enabled="1" name="clk_0"> <module kind="clock_source" version="11.1" enabled="1" name="clk_0">
<parameter name="clockFrequency" value="25000000" /> <parameter name="clockFrequency" value="25000000" />
...@@ -574,7 +574,7 @@ ...@@ -574,7 +574,7 @@
<parameter name="dcache_numTCDM" value="_0" /> <parameter name="dcache_numTCDM" value="_0" />
<parameter name="dcache_lineSize" value="_32" /> <parameter name="dcache_lineSize" value="_32" />
<parameter name="dcache_bursts" value="false" /> <parameter name="dcache_bursts" value="false" />
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_dp_offload_tx_hdr_ovr.mem' start='0x80' end='0x100' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_rx_hdr_dat.mem' start='0x200' end='0x300' /><slave name='reg_diag_data_buffer.mem' start='0x300' end='0x380' /><slave name='reg_bsn_monitor.mem' start='0x380' end='0x3C0' /><slave name='avs_eth_0.mms_reg' start='0x3C0' end='0x400' /><slave name='timer_0.s1' start='0x400' end='0x420' /><slave name='reg_unb_sens.mem' start='0x420' end='0x440' /><slave name='reg_diag_bg.mem' start='0x440' end='0x460' /><slave name='altpll_0.pll_slave' start='0x460' end='0x470' /><slave name='pio_debug_wave.s1' start='0x470' end='0x480' /><slave name='pio_wdi.s1' start='0x480' end='0x490' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x490' end='0x498' /><slave name='reg_dp_offload_tx.mem' start='0x498' end='0x4A0' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='ram_diag_bg.mem' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_tse' start='0x4000' end='0x5000' /><slave name='avs_eth_0.mms_ram' start='0x5000' end='0x6000' /><slave name='ram_diag_data_buffer.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_compaan.mem' start='0x200000' end='0x400000' /></address-map>]]></parameter> <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_dp_offload_tx_hdr_ovr.mem' start='0x80' end='0x100' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_rx_hdr_dat.mem' start='0x200' end='0x300' /><slave name='reg_diag_data_buffer.mem' start='0x300' end='0x380' /><slave name='reg_bsn_monitor.mem' start='0x380' end='0x3C0' /><slave name='avs_eth_0.mms_reg' start='0x3C0' end='0x400' /><slave name='timer_0.s1' start='0x400' end='0x420' /><slave name='reg_unb_sens.mem' start='0x420' end='0x440' /><slave name='reg_diag_bg.mem' start='0x440' end='0x460' /><slave name='altpll_0.pll_slave' start='0x460' end='0x470' /><slave name='pio_debug_wave.s1' start='0x470' end='0x480' /><slave name='pio_wdi.s1' start='0x480' end='0x490' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x490' end='0x498' /><slave name='reg_dp_offload_tx.mem' start='0x498' end='0x4A0' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='ram_diag_bg.mem' start='0x4000' end='0x4800' /><slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' /><slave name='ram_diag_data_buffer.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_compaan.mem' start='0x200000' end='0x400000' /></address-map>]]></parameter>
<parameter name="dataAddrWidth" value="22" /> <parameter name="dataAddrWidth" value="22" />
<parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" /> <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
<parameter name="cpuReset" value="false" /> <parameter name="cpuReset" value="false" />
...@@ -922,7 +922,7 @@ q]]></parameter> ...@@ -922,7 +922,7 @@ q]]></parameter>
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" /> <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
</module> </module>
<module kind="avs_common_mm" version="1.0" enabled="1" name="ram_diag_bg"> <module kind="avs_common_mm" version="1.0" enabled="1" name="ram_diag_bg">
<parameter name="g_adr_w" value="10" /> <parameter name="g_adr_w" value="9" />
<parameter name="g_dat_w" value="32" /> <parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" /> <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
</module> </module>
...@@ -1198,7 +1198,7 @@ q]]></parameter> ...@@ -1198,7 +1198,7 @@ q]]></parameter>
start="cpu_0.data_master" start="cpu_0.data_master"
end="ram_diag_bg.mem"> end="ram_diag_bg.mem">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x2000" /> <parameter name="baseAddress" value="0x4000" />
</connection> </connection>
<connection kind="clock" version="11.1" start="altpll_0.c0" end="avs_eth_0.mm" /> <connection kind="clock" version="11.1" start="altpll_0.c0" end="avs_eth_0.mm" />
<connection <connection
...@@ -1207,7 +1207,7 @@ q]]></parameter> ...@@ -1207,7 +1207,7 @@ q]]></parameter>
start="cpu_0.data_master" start="cpu_0.data_master"
end="avs_eth_0.mms_tse"> end="avs_eth_0.mms_tse">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x4000" /> <parameter name="baseAddress" value="0x2000" />
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
...@@ -1223,7 +1223,7 @@ q]]></parameter> ...@@ -1223,7 +1223,7 @@ q]]></parameter>
start="cpu_0.data_master" start="cpu_0.data_master"
end="avs_eth_0.mms_ram"> end="avs_eth_0.mms_ram">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x5000" /> <parameter name="baseAddress" value="0x8000" />
</connection> </connection>
<connection <connection
kind="interrupt" kind="interrupt"
......
applications/compaan/designs/compaan_unb1_dp_offload/src/vhdl/compaan_unb1_dp_offload.vhd
+ 29
− 12
View file @ 90357056
...@@ -84,7 +84,7 @@ ARCHITECTURE str OF compaan_unb1_dp_offload IS ...@@ -84,7 +84,7 @@ ARCHITECTURE str OF compaan_unb1_dp_offload IS
CONSTANT c_use_compaan : BOOLEAN := g_design_name = "compaan_unb1_dp_offload_co"; CONSTANT c_use_compaan : BOOLEAN := g_design_name = "compaan_unb1_dp_offload_co";
-- Firmware version x.y -- Firmware version x.y
CONSTANT c_fw_version : t_unb1_board_fw_version := (0, 5); -- CONSTANT c_fw_version : t_unb1_board_fw_version := (1, 0); --
CONSTANT c_lpbk_data_w : NATURAL := 32; -- 128 c_tech_tse_data_w, c_xgmii_data_w CONSTANT c_lpbk_data_w : NATURAL := 32; -- 128 c_tech_tse_data_w, c_xgmii_data_w
-- CONSTANT c_eth_packet_size --FIXME -- CONSTANT c_eth_packet_size --FIXME
...@@ -96,8 +96,8 @@ ARCHITECTURE str OF compaan_unb1_dp_offload IS ...@@ -96,8 +96,8 @@ ARCHITECTURE str OF compaan_unb1_dp_offload IS
CONSTANT c_data_w : NATURAL := c_tech_tse_data_w; CONSTANT c_data_w : NATURAL := c_tech_tse_data_w;
-- Block generator -- Block generator
CONSTANT c_bg_block_size : NATURAL := 900; CONSTANT c_bg_block_size : NATURAL := 365;
CONSTANT c_bg_gapsize : NATURAL := 100; CONSTANT c_bg_gapsize : NATURAL := 9*c_bg_block_size; -- Full (no gaps in data) BG output rate = 200MHz * 32b = 6.4Gbps. Including gap size: (2200/(2200+19800))*6.4Gbps=640Mbps.
CONSTANT c_bg_blocks_per_sync : NATURAL := sel_a_b(g_sim, 10, 10); -- 200000*(900+100) = 200000000 cycles = 1 second CONSTANT c_bg_blocks_per_sync : NATURAL := sel_a_b(g_sim, 10, 10); -- 200000*(900+100) = 200000000 cycles = 1 second
CONSTANT c_bg_ctrl : t_diag_block_gen := ('0', -- enable CONSTANT c_bg_ctrl : t_diag_block_gen := ('0', -- enable
'0', -- enable_sync '0', -- enable_sync
...@@ -109,6 +109,8 @@ ARCHITECTURE str OF compaan_unb1_dp_offload IS ...@@ -109,6 +109,8 @@ ARCHITECTURE str OF compaan_unb1_dp_offload IS
TO_UVEC( 0, c_diag_bg_bsn_init_w)); TO_UVEC( 0, c_diag_bg_bsn_init_w));
-- dp_offload_tx -- dp_offload_tx
-- . IP total length : 1488 (UDP total lenth) + 20 (Ip header length) = 1508
-- . UDP total length: 8 (UDP header) + 20 (usr header) + 1460 (payload bytes) = 1488
CONSTANT c_nof_hdr_fields : NATURAL := 4+12+4+9; -- Total header bits = 512 CONSTANT c_nof_hdr_fields : NATURAL := 4+12+4+9; -- Total header bits = 512
CONSTANT c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields-1 DOWNTO 0) := ( ( field_name_pad("eth_word_align" ), " ", 16, field_default(0) ), CONSTANT c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields-1 DOWNTO 0) := ( ( field_name_pad("eth_word_align" ), " ", 16, field_default(0) ),
( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ), ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
...@@ -117,7 +119,7 @@ ARCHITECTURE str OF compaan_unb1_dp_offload IS ...@@ -117,7 +119,7 @@ ARCHITECTURE str OF compaan_unb1_dp_offload IS
( field_name_pad("ip_version" ), " ", 4, field_default(4) ), ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ), ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
( field_name_pad("ip_services" ), " ", 8, field_default(0) ), ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
( field_name_pad("ip_total_length" ), " ", 16, field_default(88) ), ( field_name_pad("ip_total_length" ), " ", 16, field_default(1508) ),
( field_name_pad("ip_identification" ), " ", 16, field_default(0) ), ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
( field_name_pad("ip_flags" ), " ", 3, field_default(2) ), ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ), ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
...@@ -128,7 +130,7 @@ ARCHITECTURE str OF compaan_unb1_dp_offload IS ...@@ -128,7 +130,7 @@ ARCHITECTURE str OF compaan_unb1_dp_offload IS
( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ), ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ), ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ), ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
( field_name_pad("udp_total_length" ), " ", 16, field_default(68) ), ( field_name_pad("udp_total_length" ), " ", 16, field_default(1488) ),
( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ), ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
( field_name_pad("usr_sync" ), " ", 1, field_default(1) ), ( field_name_pad("usr_sync" ), " ", 1, field_default(1) ),
( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ), ( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
...@@ -144,8 +146,8 @@ ARCHITECTURE str OF compaan_unb1_dp_offload IS ...@@ -144,8 +146,8 @@ ARCHITECTURE str OF compaan_unb1_dp_offload IS
CONSTANT c_fifo_size : NATURAL := 2*c_bg_block_size; CONSTANT c_fifo_size : NATURAL := 2*c_bg_block_size;
CONSTANT c_use_jumbo_frames : BOOLEAN := TRUE; CONSTANT c_use_jumbo_frames : BOOLEAN := FALSE;
CONSTANT c_def_1GbE_block_size : NATURAL := 10; -- 0 first so we have time to set RX demux reg in dest. node CONSTANT c_def_1GbE_block_size : NATURAL := c_bg_block_size;
CONSTANT c_max_frame_len : NATURAL := sel_a_b(c_use_jumbo_frames, 9018, 1518); CONSTANT c_max_frame_len : NATURAL := sel_a_b(c_use_jumbo_frames, 9018, 1518);
CONSTANT c_max_frame_nof_words : NATURAL := (c_max_frame_len * c_byte_w ) / c_data_w; CONSTANT c_max_frame_nof_words : NATURAL := (c_max_frame_len * c_byte_w ) / c_data_w;
...@@ -228,6 +230,9 @@ ARCHITECTURE str OF compaan_unb1_dp_offload IS ...@@ -228,6 +230,9 @@ ARCHITECTURE str OF compaan_unb1_dp_offload IS
SIGNAL dp_offload_tx_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0); SIGNAL dp_offload_tx_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL dp_offload_tx_src_in_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0); SIGNAL dp_offload_tx_src_in_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL dp_fifo_fill_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL dp_fifo_fill_src_in_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL dp_offload_rx_snk_in_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0); SIGNAL dp_offload_rx_snk_in_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL dp_offload_rx_snk_out_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0); SIGNAL dp_offload_rx_snk_out_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
...@@ -296,7 +301,7 @@ BEGIN ...@@ -296,7 +301,7 @@ BEGIN
u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc
GENERIC MAP ( GENERIC MAP (
g_data_w => c_data_w, g_data_w => c_data_w,
g_fifo_size => 256 g_fifo_size => 3*c_bg_block_size
) )
PORT MAP ( PORT MAP (
rst => dp_rst, rst => dp_rst,
...@@ -349,8 +354,20 @@ BEGIN ...@@ -349,8 +354,20 @@ BEGIN
hdr_fields_in_arr => hdr_fields_in_arr hdr_fields_in_arr => hdr_fields_in_arr
); );
u_dp_fifo_fill : ENTITY dp_lib.dp_fifo_fill
GENERIC MAP (
g_data_w => 32,
g_fifo_fill => 375+16,
g_fifo_size => 375+16+10
)
PORT MAP (
rst => dp_rst,
clk => dp_clk,
snk_in => dp_offload_tx_src_out_arr(0),
snk_out => dp_offload_tx_src_in_arr(0),
src_in => dp_fifo_fill_src_in_arr(0),
src_out => dp_fifo_fill_src_out_arr(0)
);
gen_hdr_in_fields : FOR i IN 0 TO c_nof_streams-1 GENERATE gen_hdr_in_fields : FOR i IN 0 TO c_nof_streams-1 GENERATE
-- dst = src -- dst = src
...@@ -655,8 +672,8 @@ BEGIN ...@@ -655,8 +672,8 @@ BEGIN
eth1g_ram_miso => eth1g_ram_miso, eth1g_ram_miso => eth1g_ram_miso,
-- eth1g UDP streaming ports -- eth1g UDP streaming ports
udp_tx_sosi_arr => dp_offload_tx_src_out_arr, udp_tx_sosi_arr => dp_fifo_fill_src_out_arr, --dp_offload_tx_src_out_arr,
udp_tx_siso_arr => dp_offload_tx_src_in_arr, udp_tx_siso_arr => dp_fifo_fill_src_in_arr, --dp_offload_tx_src_in_arr,
udp_rx_sosi_arr => dp_offload_rx_snk_in_arr, udp_rx_sosi_arr => dp_offload_rx_snk_in_arr,
udp_rx_siso_arr => dp_offload_rx_snk_out_arr, udp_rx_siso_arr => dp_offload_rx_snk_out_arr,
......
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