Added quartus_sdc_files. No need to have...

Added quartus_sdc_files. No need to have ip_stratixiv_ddr3_uphy_4g_800_master.qip at quartus_qip_files key, because it already gets included via the *_lib.qip.

boards/uniboard1/designs/unb1_ddr3/hdllib.cfg

@@ -16,6 +16,9 @@ synth_files =
 test_bench_files = 
     tb/vhdl/tb_unb1_ddr3.vhd
 
+modelsim_compile_ip_files =
+    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+    
 synth_top_level_entity =
 
 quartus_copy_files =
@@ -24,16 +27,13 @@ quartus_copy_files =
 quartus_qsf_files =
     $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
+quartus_qip_files =
+    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.qip
+
 quartus_tcl_files =
     quartus/unb1_ddr3_pins.tcl
     quartus/unb1_ddr3_pins_constraints.tcl
     
-quartus_vhdl_files = 
-
-quartus_qip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
-    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.qip
-
-modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+quartus_sdc_files =
+    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc