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Commit 3fbe87cd authored by Pepping's avatar Pepping
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UPdated TB for wholoeboard simulatipon

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boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd
+ 184
− 73
View file @ 3fbe87cd
......@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
-- Purpose: Verify that unb1_terminal_bg_mesh_db can simulate
-- Description: No verification and no need to run a main.c. Just check that it
-- loads OK and runs OK (i.e. that the DUT IO are toggling) for a few us.
-- Description:
--
-- Usage:
-- > as 3
-- > as 8
-- > run 10 us
LIBRARY IEEE, common_lib, unb1_board_lib;
......@@ -33,6 +33,7 @@ USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
USE unb1_board_lib.tb_unb1_board_pkg.ALL;
ENTITY tb_unb1_terminal_bg_mesh_db IS
END tb_unb1_terminal_bg_mesh_db;
......@@ -41,11 +42,14 @@ ARCHITECTURE tb OF tb_unb1_terminal_bg_mesh_db IS
CONSTANT c_sim : BOOLEAN := TRUE;
CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
CONSTANT c_id_fn0 : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000100";
CONSTANT c_id_bn3 : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000111";
CONSTANT c_sim_level : NATURAL := 1;
CONSTANT c_nof_bn : NATURAL := 1;
CONSTANT c_nof_fn : NATURAL := 1;
CONSTANT c_nof_nodes : NATURAL := c_nof_bn + c_nof_fn;
CONSTANT c_ena_mesh_reorder: BOOLEAN := TRUE;
CONSTANT c_sim_unb_nr : NATURAL := 0;
CONSTANT c_sim_node_nr : NATURAL := 0;
CONSTANT c_cable_delay : TIME := 12 ns;
......@@ -53,6 +57,8 @@ ARCHITECTURE tb OF tb_unb1_terminal_bg_mesh_db IS
CONSTANT c_eth_clk_period : TIME := 40 ns; -- 25 MHz XO on UniBoard
CONSTANT c_tr_clk_period : TIME := 6400 ps; -- 156.25 MHz XO on UniBoard
TYPE t_mesh_arr IS ARRAY (c_nof_nodes-1 DOWNTO 0) OF STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
-- DUT
SIGNAL WDI : STD_LOGIC;
SIGNAL ext_pps : STD_LOGIC;
......@@ -68,24 +74,31 @@ ARCHITECTURE tb OF tb_unb1_terminal_bg_mesh_db IS
SIGNAL sens_sda : STD_LOGIC;
SIGNAL eth_clk : STD_LOGIC := '0';
SIGNAL eth_txp : STD_LOGIC;
SIGNAL eth_rxp : STD_LOGIC;
SIGNAL eth_txp : STD_LOGIC_VECTOR(c_nof_nodes-1 DOWNTO 0);
SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_nof_nodes-1 DOWNTO 0);
SIGNAL tr_clk : STD_LOGIC := '0';
SIGNAL FN_BN_0_TX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
SIGNAL FN_BN_0_RX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
SIGNAL FN_BN_1_TX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
SIGNAL FN_BN_1_RX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
SIGNAL FN_BN_2_TX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
SIGNAL FN_BN_2_RX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
SIGNAL FN_BN_3_TX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
SIGNAL FN_BN_3_RX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
SIGNAL FN_BN_0_TX_arr : t_mesh_arr;
SIGNAL FN_BN_0_RX_arr : t_mesh_arr;
SIGNAL FN_BN_1_TX_arr : t_mesh_arr;
SIGNAL FN_BN_1_RX_arr : t_mesh_arr;
SIGNAL FN_BN_2_TX_arr : t_mesh_arr;
SIGNAL FN_BN_2_RX_arr : t_mesh_arr;
SIGNAL FN_BN_3_TX_arr : t_mesh_arr;
SIGNAL FN_BN_3_RX_arr : t_mesh_arr;
------------------------------------------------------------------------------
-- BN & FN mesh side serial I/O
------------------------------------------------------------------------------
SIGNAL bn_out_mesh_serial_3arr : t_unb1_board_mesh_sl_3arr;
SIGNAL bn_in_mesh_serial_3arr : t_unb1_board_mesh_sl_3arr;
SIGNAL fn_in_mesh_serial_3arr : t_unb1_board_mesh_sl_3arr;
SIGNAL fn_out_mesh_serial_3arr : t_unb1_board_mesh_sl_3arr;
BEGIN
-- Run 1 ms
ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- 1GbE XO clock (25 MHz)
tr_clk <= NOT tr_clk AFTER c_tr_clk_period/2; -- Transceiver clock (156.25 MHz)
......@@ -99,18 +112,18 @@ BEGIN
sens_sda <= 'H'; -- pull up
VERSION <= c_version;
ID <= c_id_fn0;
------------------------------------------------------------------------------
-- UniBoard FPGA Node
-- UniBoard
------------------------------------------------------------------------------
u_dut : ENTITY work.unb1_terminal_bg_mesh_db
gen_bn: FOR BN IN 0 TO c_nof_bn-1 GENERATE
u_bn : ENTITY work.unb1_terminal_bg_mesh_db
GENERIC MAP (
-- General
g_sim => c_sim,
g_sim_level => 1,
g_sim_level => c_sim_level,
g_sim_unb_nr => c_sim_unb_nr,
g_sim_node_nr => c_sim_node_nr
g_sim_node_nr => (BN + 4)
)
PORT MAP (
-- GENERAL
......@@ -122,7 +135,7 @@ BEGIN
-- Others
VERSION => VERSION,
ID => ID,
ID => TO_UVEC(BN + 4, c_unb1_board_aux.id_w), -- BN chip ID 4,5,6,7
TESTIO => TESTIO,
-- I2C Interface to Sensors
......@@ -131,33 +144,131 @@ BEGIN
-- 1GbE Control Interface
ETH_clk => eth_clk, -- ETH reference clock also used for system reference clock
ETH_SGIN => eth_rxp,
ETH_SGOUT => eth_txp,
ETH_SGIN => eth_rxp(BN + c_nof_fn),
ETH_SGOUT => eth_txp(BN + c_nof_fn),
-- Transceiver clocks
SB_CLK => tr_clk, -- TR clock FN-BN(mesh)
-- Mesh serial I/O
FN_BN_0_TX => FN_BN_0_TX,
FN_BN_0_RX => FN_BN_0_RX,
FN_BN_1_TX => FN_BN_1_TX,
FN_BN_1_RX => FN_BN_1_RX,
FN_BN_2_TX => FN_BN_2_TX,
FN_BN_2_RX => FN_BN_2_RX,
FN_BN_3_TX => FN_BN_3_TX,
FN_BN_3_RX => FN_BN_3_RX
FN_BN_0_TX => FN_BN_0_TX_arr(BN + c_nof_fn),
FN_BN_0_RX => FN_BN_0_RX_arr(BN + c_nof_fn),
FN_BN_1_TX => FN_BN_1_TX_arr(BN + c_nof_fn),
FN_BN_1_RX => FN_BN_1_RX_arr(BN + c_nof_fn),
FN_BN_2_TX => FN_BN_2_TX_arr(BN + c_nof_fn),
FN_BN_2_RX => FN_BN_2_RX_arr(BN + c_nof_fn),
FN_BN_3_TX => FN_BN_3_TX_arr(BN + c_nof_fn),
FN_BN_3_RX => FN_BN_3_RX_arr(BN + c_nof_fn)
);
------------------------------------------------------------------------------
-- Loopback model
------------------------------------------------------------------------------
-- Use mesh_io block to create 3arr format for the mesh model.
u_mesh_io : ENTITY unb1_board_lib.unb1_board_mesh_io
GENERIC MAP (
g_bus_w => c_unb1_board_tr_mesh.bus_w
)
PORT MAP (
tx_serial_2arr => bn_in_mesh_serial_3arr(BN),
rx_serial_2arr => bn_out_mesh_serial_3arr(BN),
-- Serial I/O
FN_BN_0_TX => FN_BN_0_RX_arr(BN + c_nof_fn),
FN_BN_0_RX => FN_BN_0_TX_arr(BN + c_nof_fn),
FN_BN_1_TX => FN_BN_1_RX_arr(BN + c_nof_fn),
FN_BN_1_RX => FN_BN_1_TX_arr(BN + c_nof_fn),
FN_BN_2_TX => FN_BN_2_RX_arr(BN + c_nof_fn),
FN_BN_2_RX => FN_BN_2_TX_arr(BN + c_nof_fn),
FN_BN_3_TX => FN_BN_3_RX_arr(BN + c_nof_fn),
FN_BN_3_RX => FN_BN_3_TX_arr(BN + c_nof_fn)
);
END GENERATE;
gen_fn: FOR FN IN 0 TO c_nof_fn-1 GENERATE
u_fn : ENTITY work.unb1_terminal_bg_mesh_db
GENERIC MAP (
-- General
g_sim => c_sim,
g_sim_level => c_sim_level,
g_sim_unb_nr => c_sim_unb_nr,
g_sim_node_nr => FN
)
PORT MAP (
-- GENERAL
WDI => WDI,
CLK => ext_clk,
PPS => ext_pps,
INTA => INTA,
INTB => INTB,
eth_rxp <= TRANSPORT eth_txp AFTER c_cable_delay;
-- Others
VERSION => VERSION,
ID => TO_UVEC(FN, c_unb1_board_aux.id_w), -- FN chip ID 0,1,2,3,
TESTIO => TESTIO,
-- I2C Interface to Sensors
sens_sc => sens_scl,
sens_sd => sens_sda,
-- 1GbE Control Interface
ETH_clk => eth_clk, -- ETH reference clock also used for system reference clock
ETH_SGIN => eth_rxp(FN),
ETH_SGOUT => eth_txp(FN),
-- Transceiver clocks
SB_CLK => tr_clk, -- TR clock FN-BN(mesh)
FN_BN_0_RX <= TRANSPORT FN_BN_0_TX AFTER c_cable_delay;
FN_BN_1_RX <= TRANSPORT FN_BN_1_TX AFTER c_cable_delay;
FN_BN_2_RX <= TRANSPORT FN_BN_2_TX AFTER c_cable_delay;
FN_BN_3_RX <= TRANSPORT FN_BN_3_TX AFTER c_cable_delay;
-- Mesh serial I/O
FN_BN_0_TX => FN_BN_0_TX_arr(FN),
FN_BN_0_RX => FN_BN_0_RX_arr(FN),
FN_BN_1_TX => FN_BN_1_TX_arr(FN),
FN_BN_1_RX => FN_BN_1_RX_arr(FN),
FN_BN_2_TX => FN_BN_2_TX_arr(FN),
FN_BN_2_RX => FN_BN_2_RX_arr(FN),
FN_BN_3_TX => FN_BN_3_TX_arr(FN),
FN_BN_3_RX => FN_BN_3_RX_arr(FN)
);
-- Use mesh_io block to create 3arr format for the mesh model.
u_mesh_io : ENTITY unb1_board_lib.unb1_board_mesh_io
GENERIC MAP (
g_bus_w => c_unb1_board_tr_mesh.bus_w
)
PORT MAP (
tx_serial_2arr => fn_in_mesh_serial_3arr(FN),
rx_serial_2arr => fn_out_mesh_serial_3arr(FN),
-- Serial I/O
FN_BN_0_TX => FN_BN_0_RX_arr(FN),
FN_BN_0_RX => FN_BN_0_TX_arr(FN),
FN_BN_1_TX => FN_BN_1_RX_arr(FN),
FN_BN_1_RX => FN_BN_1_TX_arr(FN),
FN_BN_2_TX => FN_BN_2_RX_arr(FN),
FN_BN_2_RX => FN_BN_2_TX_arr(FN),
FN_BN_3_TX => FN_BN_3_RX_arr(FN),
FN_BN_3_RX => FN_BN_3_TX_arr(FN)
);
END GENERATE;
-- Direct interconnect BN0<->FN0.
no_mesh : IF c_nof_bn=1 AND c_nof_fn=1 GENERATE
fn_in_mesh_serial_3arr(0) <= bn_out_mesh_serial_3arr(0);
bn_in_mesh_serial_3arr(0) <= fn_out_mesh_serial_3arr(0);
END GENERATE;
-- Mesh model
gen_mesh : IF c_nof_bn>1 OR c_nof_fn>1 GENERATE
u_mesh_model_serial : ENTITY unb1_board_lib.unb1_board_mesh_model_sl
GENERIC MAP(
g_reorder => c_ena_mesh_reorder
)
PORT MAP (
-- FN to BN
fn_tx_sl_3arr => fn_out_mesh_serial_3arr,
bn_rx_sl_3arr => bn_in_mesh_serial_3arr,
-- BN to FN
bn_tx_sl_3arr => bn_out_mesh_serial_3arr,
fn_rx_sl_3arr => fn_in_mesh_serial_3arr
);
END GENERATE;
END tb;
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