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Commit 7afdbd07 authored by Daniel van der Schuur's avatar Daniel van der Schuur
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-Moved MMM to the bottom in top level as it is the least relevant; 

-Fixed BG address width;
-(also committing myhdl_mms_diag_block_gen.py, just to sync SVN)
parent 0c1125cd
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applications/apertif/designs/apertif_unb1_fn_bf_emu/src/myhdl/myhdl_mms_diag_block_gen.py
+ 9
− 2
View file @ 7afdbd07
...@@ -79,8 +79,15 @@ def myhdl_mms_diag_block_gen(g_nof_streams, g_buf_dat_w, g_buf_addr_w, g_file_na ...@@ -79,8 +79,15 @@ def myhdl_mms_diag_block_gen(g_nof_streams, g_buf_dat_w, g_buf_addr_w, g_file_na
# Workaround for lack of user defined type support: define the substrings here # Workaround for lack of user defined type support: define the substrings here
out_sosi_arr_substrings = "" out_sosi_arr_substrings = ""
for i in range(g_nof_streams): for i in range(g_nof_streams):
out_sosi_arr_substring = " out_sosi_arr(%d) => out_sosi_arr(%d),\n" %(i,i) out_sosi_arr_substring_data = " out_sosi_arr(%d).data(%d-1 DOWNTO 0) => out_sosi_arr(%d).data,\n" %(i,g_buf_dat_w,i)
out_sosi_arr_substrings+=out_sosi_arr_substring out_sosi_arr_substring_sop = " out_sosi_arr(%d).sop => out_sosi_arr(%d).sop,\n" %(i,i)
out_sosi_arr_substring_eop = " out_sosi_arr(%d).eop => out_sosi_arr(%d).eop,\n" %(i,i)
out_sosi_arr_substring_valid = " out_sosi_arr(%d).valid => out_sosi_arr(%d).valid,\n" %(i,i)
out_sosi_arr_substrings+=(out_sosi_arr_substring_data+\
out_sosi_arr_substring_sop+\
out_sosi_arr_substring_eop+\
out_sosi_arr_substring_valid)
# Remove the last ',' (and the last newline char) from the string # Remove the last ',' (and the last newline char) from the string
out_sosi_arr_substrings=out_sosi_arr_substrings[:-2] out_sosi_arr_substrings=out_sosi_arr_substrings[:-2]
return wrap return wrap
......
applications/apertif/designs/apertif_unb1_fn_bf_emu/src/vhdl/apertif_unb1_fn_bf_emu.vhd
+ 94
− 102
View file @ 7afdbd07
...@@ -199,99 +199,6 @@ ARCHITECTURE str OF apertif_unb1_fn_bf_emu IS ...@@ -199,99 +199,6 @@ ARCHITECTURE str OF apertif_unb1_fn_bf_emu IS
BEGIN BEGIN
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl : ENTITY unb1_board_lib.ctrl_unb1_board
GENERIC MAP (
g_sim => g_sim,
g_design_name => g_design_name,
g_design_note => g_design_note,
g_stamp_date => g_stamp_date,
g_stamp_time => g_stamp_time,
g_stamp_svn => g_stamp_svn,
g_fw_version => c_fw_version,
g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
g_dp_clk_use_pll => c_dp_clk_use_pll,
g_use_phy => c_use_phy,
g_udp_offload => TRUE,
g_aux => c_unb1_board_aux,
g_udp_offload_nof_streams => c_eth_nof_udp_ports,
g_xo_clk_use_pll => FALSE
)
PORT MAP (
-- Clock an reset signals
cs_sim => cs_sim,
xo_clk => xo_clk,
xo_rst => xo_rst,
xo_rst_n => xo_rst_n,
mm_clk => mm_clk,
mm_locked => mm_locked,
mm_rst => mm_rst,
dp_rst => ctrl_dp_rst,
dp_clk => ctrl_dp_clk,
dp_pps => dp_pps,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
this_chip_id => this_chip_id,
-- Toggle WDI
pout_debug_wave => pout_debug_wave,
pout_wdi => pout_wdi,
-- MM buses
-- . Manual WDI override
reg_wdi_mosi => reg_wdi_mosi,
reg_wdi_miso => reg_wdi_miso,
-- . System_info
reg_unb_system_info_mosi => reg_unb_system_info_mosi,
reg_unb_system_info_miso => reg_unb_system_info_miso,
rom_unb_system_info_mosi => rom_unb_system_info_mosi,
rom_unb_system_info_miso => rom_unb_system_info_miso,
-- . UniBoard I2C sensors
reg_unb_sens_mosi => reg_unb_sens_mosi,
reg_unb_sens_miso => reg_unb_sens_miso,
-- . PPSH
reg_ppsh_mosi => reg_ppsh_mosi,
reg_ppsh_miso => reg_ppsh_miso,
-- eth1g
eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
eth1g_mm_rst => eth1g_mm_rst,
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
eth1g_reg_mosi => eth1g_reg_mosi,
eth1g_reg_miso => eth1g_reg_miso,
eth1g_reg_interrupt => eth1g_reg_interrupt,
eth1g_ram_mosi => eth1g_ram_mosi,
eth1g_ram_miso => eth1g_ram_miso,
-- FPGA pins
-- . General
CLK => CLK,
PPS => PPS,
WDI => WDI,
INTA => INTA,
INTB => INTB,
-- . Others
VERSION => VERSION,
ID => ID,
TESTIO => TESTIO,
-- . I2C Interface to Sensors
sens_sc => sens_sc,
sens_sd => sens_sd,
-- . 1GbE Control Interface
ETH_clk => ETH_clk,
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT
);
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- Interface : 10GbE -- Interface : 10GbE
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
...@@ -395,7 +302,7 @@ BEGIN ...@@ -395,7 +302,7 @@ BEGIN
GENERIC MAP ( GENERIC MAP (
g_nof_streams => 4, g_nof_streams => 4,
g_buf_dat_w => 16, g_buf_dat_w => 16,
g_buf_addr_w => 256, g_buf_addr_w => ceil_log2(256),
g_file_name_prefix => "hex/bg_data", g_file_name_prefix => "hex/bg_data",
g_diag_block_gen_rst => c_bg_ctrl g_diag_block_gen_rst => c_bg_ctrl
) )
...@@ -435,7 +342,10 @@ BEGIN ...@@ -435,7 +342,10 @@ BEGIN
reg_dp_offload_tx_hdr_dat_mosi => c_mem_mosi_rst, reg_dp_offload_tx_hdr_dat_mosi => c_mem_mosi_rst,
reg_dp_offload_tx_hdr_dat_miso => OPEN reg_dp_offload_tx_hdr_dat_miso => OPEN
); );
-----------------------------------------------------------------------------
-- MM Master
-----------------------------------------------------------------------------
u_mmm : ENTITY work.mmm_apertif_unb1_fn_bf_emu u_mmm : ENTITY work.mmm_apertif_unb1_fn_bf_emu
GENERIC MAP( GENERIC MAP(
-- General -- General
...@@ -500,17 +410,99 @@ BEGIN ...@@ -500,17 +410,99 @@ BEGIN
eth1g_ram_mosi => eth1g_ram_mosi, eth1g_ram_mosi => eth1g_ram_mosi,
eth1g_ram_miso => eth1g_ram_miso eth1g_ram_miso => eth1g_ram_miso
); );
END;
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl : ENTITY unb1_board_lib.ctrl_unb1_board
GENERIC MAP (
g_sim => g_sim,
g_design_name => g_design_name,
g_design_note => g_design_note,
g_stamp_date => g_stamp_date,
g_stamp_time => g_stamp_time,
g_stamp_svn => g_stamp_svn,
g_fw_version => c_fw_version,
g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
g_dp_clk_use_pll => c_dp_clk_use_pll,
g_use_phy => c_use_phy,
g_udp_offload => TRUE,
g_aux => c_unb1_board_aux,
g_udp_offload_nof_streams => c_eth_nof_udp_ports,
g_xo_clk_use_pll => FALSE
)
PORT MAP (
-- Clock an reset signals
cs_sim => cs_sim,
xo_clk => xo_clk,
xo_rst => xo_rst,
xo_rst_n => xo_rst_n,
mm_clk => mm_clk,
mm_locked => mm_locked,
mm_rst => mm_rst,
dp_rst => ctrl_dp_rst,
dp_clk => ctrl_dp_clk,
dp_pps => dp_pps,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
this_chip_id => this_chip_id,
-- Toggle WDI
pout_debug_wave => pout_debug_wave,
pout_wdi => pout_wdi,
-- MM buses
-- . Manual WDI override
reg_wdi_mosi => reg_wdi_mosi,
reg_wdi_miso => reg_wdi_miso,
-- . System_info
reg_unb_system_info_mosi => reg_unb_system_info_mosi,
reg_unb_system_info_miso => reg_unb_system_info_miso,
rom_unb_system_info_mosi => rom_unb_system_info_mosi,
rom_unb_system_info_miso => rom_unb_system_info_miso,
-- . UniBoard I2C sensors
reg_unb_sens_mosi => reg_unb_sens_mosi,
reg_unb_sens_miso => reg_unb_sens_miso,
-- . PPSH
reg_ppsh_mosi => reg_ppsh_mosi,
reg_ppsh_miso => reg_ppsh_miso,
-- eth1g
eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
eth1g_mm_rst => eth1g_mm_rst,
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
eth1g_reg_mosi => eth1g_reg_mosi,
eth1g_reg_miso => eth1g_reg_miso,
eth1g_reg_interrupt => eth1g_reg_interrupt,
eth1g_ram_mosi => eth1g_ram_mosi,
eth1g_ram_miso => eth1g_ram_miso,
-- FPGA pins
-- . General
CLK => CLK,
PPS => PPS,
WDI => WDI,
INTA => INTA,
INTB => INTB,
-- . Others
VERSION => VERSION,
ID => ID,
TESTIO => TESTIO,
-- . I2C Interface to Sensors
sens_sc => sens_sc,
sens_sd => sens_sd,
-- . 1GbE Control Interface
ETH_clk => ETH_clk,
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT
);
END;
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