Commits · 2b15c467b5a33cfc7e7b8a16440fcd799136ba09 · RTSD / HDL · GitLab

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Dec 23, 2014
- Support g_wr_flush_mode = VAL, SOP, SYN. · 2b15c467
  Eric Kooistra authored 10 years ago
  
  2b15c467
- Added dvr_wr_fifo_usedw output for monitoring purposes, eg. used for verification in tb_io_ddr.vhd. · 0769c3b1
  Eric Kooistra authored 10 years ago
  
  0769c3b1
- Redefined write flush modes. Now the flush is still under control by... · 122facc2
  Eric Kooistra authored 10 years ago
  122facc2
- Clarified clock domains and use ctlr_clk_out and ctlr_clk_in to make ctlr_clk... · 3516f313
  Eric Kooistra authored 10 years ago
  3516f313
Dec 22, 2014
- Use 'RANGE instead of g_wr_fifo_depth to know width of wr_fifo_usedw. · e92d0677
  Eric Kooistra authored 10 years ago
  
  e92d0677
- Use mosi/miso and sosi/siso records on the ports. · 6bda9022
  Eric Kooistra authored 10 years ago
  
  6bda9022
- Prepare for DDR mosi/miso ports by adding ports ctlr_rddata,rdval and ctlr_address,wrdata. · 7383de11
  Eric Kooistra authored 10 years ago
  
  7383de11
- Use func_tech_ddr_ctrl_address() for ctlr_mosi.address. · 16ad05ed
  Eric Kooistra authored 10 years ago
  
  16ad05ed
Dec 19, 2014
- Instantiate tech_ddr_lib.tech_ddr. Keep ctlr_gen_clk internal.diff · 87345d92
  Eric Kooistra authored 10 years ago
  
  87345d92
Dec 18, 2014
- Ported $UNB ddr3.vhd to $RADIOHDL io_ddr.vhd. Initial version, still needs to... · f894602f
  Eric Kooistra authored 10 years ago
  f894602f