Resolve L2SDP-660
8 unresolved threads
8 unresolved threads
Closes L2SDP-660
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requested review from @walle
assigned to @wee
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80 -- signals for readability 81 SIGNAL d_reg : t_reg := c_t_reg_init; 82 SIGNAL q_reg : t_reg := c_t_reg_init; 83 84 BEGIN 85 86 q_reg <= d_reg WHEN rising_edge(clk); 87 88 -- Increments the address each time in_sosi.valid = '1', if address = c_max_adr the address is reset to 0. 89 p_adr : PROCESS(rst, in_sosi, in_of, q_reg) 90 91 VARIABLE v : t_reg; 92 93 BEGIN 94 v := q_reg; 95 v.out_mosi.wrdata(c_data_w-1 DOWNTO 0) := v.s_in_sosi.data(c_data_w - 1 DOWNTO 0); changed this line in version 9 of the diff
23 -- Description: 24 -- The data from the t_dp_sosi_arr gets put into one data vector. 25 -- 26 -- Remark: 27 -- Use VHDL coding template from: 28 -- https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding 29 30 LIBRARY IEEE, dp_lib; 31 USE IEEE.std_logic_1164.ALL; 32 USE dp_lib.dp_stream_pkg.ALL; 33 34 ENTITY ddrctrl_pack IS 35 GENERIC ( 36 37 g_nof_streams : POSITIVE := 12; -- number of input streams 38 g_data_w : NATURAL := 14 -- data with of input data vectors changed this line in version 9 of the diff
29 30 LIBRARY IEEE, dp_lib; 31 USE IEEE.std_logic_1164.ALL; 32 USE dp_lib.dp_stream_pkg.ALL; 33 34 ENTITY ddrctrl_pack IS 35 GENERIC ( 36 37 g_nof_streams : POSITIVE := 12; -- number of input streams 38 g_data_w : NATURAL := 14 -- data with of input data vectors 39 40 ); 41 PORT ( 42 43 in_sosi_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- input data 44 out_data : OUT STD_LOGIC_VECTOR((g_nof_streams*g_data_w)-1 DOWNTO 0) -- output data changed this line in version 9 of the diff
30 -- The output vector must be larger than the input vector. 31 32 LIBRARY IEEE, dp_lib, tech_ddr_lib; 33 USE IEEE.std_logic_1164.ALL; 34 USE dp_lib.dp_stream_pkg.ALL; 35 USE tech_ddr_lib.tech_ddr_pkg.ALL; 36 37 ENTITY ddrctrl_repack IS 38 GENERIC ( 39 g_tech_ddr : t_c_tech_ddr; -- type of memory 40 g_in_data_w : NATURAL := 168 -- the input data with 41 ); 42 PORT ( 43 clk : IN STD_LOGIC; 44 rst : IN STD_LOGIC; 45 in_data : IN STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0); -- input data changed this line in version 9 of the diff
94 v.c_v_count := q_reg.c_v_count+1; -- increase the counter of c_v with 1 95 v.out_sosi.valid := '0'; -- out_sosi.valid 0 96 97 WHEN FIRST_OUTPUT => -- if the input data exceeds output data vector width but not the c_v width 98 v.c_v(g_in_data_w*(q_reg.c_v_count+1)+q_reg.a_of-1 DOWNTO g_in_data_w*q_reg.c_v_count+q_reg.a_of) := in_data(g_in_data_w-1 DOWNTO 0); -- fill c_v 99 v.c_v_count := q_reg.c_v_count + 1; -- increase the counter of c_v with 1 100 v.out_sosi.data(c_out_data_w - 1 DOWNTO 0) := v.c_v(c_out_data_w - 1 DOWNTO 0); -- fill out_sosi.data with 1st part of c_v 101 v.out_sosi.valid := '1'; -- out_sosi.valid 1 102 v.out_data_count := q_reg.out_data_count+1; -- increase the counter of out_sosi.data with 1 103 104 WHEN OVERFLOW_OUTPUT => -- if the input data exceeds the output data vector width and the c_v width 105 v.a_of := q_reg.a_of + (g_in_data_w*(q_reg.c_v_count+1)) - (c_out_data_w*(q_reg.out_data_count+1)); -- check how much overflow there is and safe it in a_of 106 v.out_of := v.a_of; -- set the output overflow to the overflow that maches the out_sosi.data vector 107 v.c_v(k_c_v_w-1 DOWNTO k_c_v_w-(g_in_data_w-v.a_of)) := in_data(g_in_data_w-v.a_of-1 DOWNTO 0); -- fill the rest of c_v untill the end 108 v.c_v(v.a_of-1 DOWNTO 0) := in_data(g_in_data_w-1 DOWNTO g_in_data_w-v.a_of); -- fill the start of c_v untill the a_of 109 v.out_sosi.data(c_out_data_w-1 DOWNTO 0) := v.c_v(k_c_v_w-1 DOWNTO c_out_data_w); -- fill out_sosi.data with 2nd part of c_v changed this line in version 9 of the diff
96 97 WHEN FIRST_OUTPUT => -- if the input data exceeds output data vector width but not the c_v width 98 v.c_v(g_in_data_w*(q_reg.c_v_count+1)+q_reg.a_of-1 DOWNTO g_in_data_w*q_reg.c_v_count+q_reg.a_of) := in_data(g_in_data_w-1 DOWNTO 0); -- fill c_v 99 v.c_v_count := q_reg.c_v_count + 1; -- increase the counter of c_v with 1 100 v.out_sosi.data(c_out_data_w - 1 DOWNTO 0) := v.c_v(c_out_data_w - 1 DOWNTO 0); -- fill out_sosi.data with 1st part of c_v 101 v.out_sosi.valid := '1'; -- out_sosi.valid 1 102 v.out_data_count := q_reg.out_data_count+1; -- increase the counter of out_sosi.data with 1 103 104 WHEN OVERFLOW_OUTPUT => -- if the input data exceeds the output data vector width and the c_v width 105 v.a_of := q_reg.a_of + (g_in_data_w*(q_reg.c_v_count+1)) - (c_out_data_w*(q_reg.out_data_count+1)); -- check how much overflow there is and safe it in a_of 106 v.out_of := v.a_of; -- set the output overflow to the overflow that maches the out_sosi.data vector 107 v.c_v(k_c_v_w-1 DOWNTO k_c_v_w-(g_in_data_w-v.a_of)) := in_data(g_in_data_w-v.a_of-1 DOWNTO 0); -- fill the rest of c_v untill the end 108 v.c_v(v.a_of-1 DOWNTO 0) := in_data(g_in_data_w-1 DOWNTO g_in_data_w-v.a_of); -- fill the start of c_v untill the a_of 109 v.out_sosi.data(c_out_data_w-1 DOWNTO 0) := v.c_v(k_c_v_w-1 DOWNTO c_out_data_w); -- fill out_sosi.data with 2nd part of c_v 110 v.out_sosi.valid := '1'; -- out_sosi.valid 1 111 v.c_v_count := 0; -- reset counter changed this line in version 9 of the diff
101 in_data_enable <= '1'; 102 in_data <= NOT in_data; 103 in_of <= in_of + 1; 104 WAIT FOR c_clk_period*1; 105 in_data_enable <= '0'; 106 WAIT FOR c_clk_period*2; 107 END LOOP; 108 109 -- stopping the test 110 WAIT FOR c_clk_period*4; 111 tb_end <= '1'; 112 ASSERT FALSE REPORT "Test: OK" SEVERITY FAILURE; 113 END PROCESS; 114 115 -- generating compare data for out_mosi 116 p_out_mosi : PROCESS Gaat dit goed? Ik zou verwachten dat er of "clk" in de sensitivity list staat of dat er aan het eind een WAIT; staat. Ook bij meerdere processes
Edited by Reinier van der Walle
33 33 -- Remarks: 34 34 -- * Choose smallest maximum SOSI slv lengths that fit all use cases, because unconstrained record fields slv is not allowed 35 35 -- * The large SOSI data field width of 256b has some disadvantages: 36 -- . about 10% extra simulation time and PC memory usage compared to 72b (measured using tb_unb_tse_board) 36 -- . about 1ni0% extra simulation time and PC memory usage compared to 72b (measured using tb_unb_tse_board) changed this line in version 10 of the diff
mentioned in commit 7a5501e1
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