@@ -45,6 +45,7 @@ ENTITY ddrctrl_address_counter IS
g_sim_model:BOOLEAN:=TRUE-- determens if this is a simulation
);
PORT(
clk:INSTD_LOGIC;
rst:INSTD_LOGIC;
in_sosi:INt_dp_sosi;-- input data
out_mosi:OUTt_mem_ctlr_mosi:=c_mem_ctlr_mosi_rst-- output data
@@ -57,30 +58,30 @@ ARCHITECTURE rtl OF ddrctrl_address_counter IS
-- constants for readability
CONSTANTc_data_w:NATURAL:=func_tech_ddr_ctlr_data_w(g_tech_ddr);-- the with of the input data and output data, 576
CONSTANTc_adr_w:NATURAL:=sel_a_b(g_sim_model,4,func_tech_ddr_ctlr_address_w(g_tech_ddr));-- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
CONSTANTc_max_adr:NATURAL:=2**(c_adr_w)-1;-- the maximal address that is possible within the vector length of the address
CONSTANTc_max_adr:NATURAL:=2**(c_adr_w)-1;-- the maximal address that is possible within the vector length of the address
-- signal for storing address
SIGNALs_adr:NATURALrange0to2**(c_adr_w)-1:=0;-- a signal that contains the address