Resolve L2SDP-660

Closes L2SDP-660

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author: Job van Wee
+-- Purpose: Folding a stream of data into a mm data configuration so it can be
+-- stored in a DDR RAM-stick.
+--
+-- Description:
+--  First the data from the sosi array gets collected into one data vector.
+--  After that this data vector gets resized to the right size data vector in 
+--  order to make it storable in a DDR RAM-stick.
+--  After that a address gets assigned to the data so the data can be found back.
+--
+-- Remark:
+--  Use VHDL coding template from:
+--  https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
+--  The maximum value of the address is determend by g_tech_ddr.
+
+LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+
+ENTITY ddrctrl IS
+  GENERIC (
+    g_tech_ddr        : t_c_tech_ddr;                                   -- type of memory
+    g_sim_model       : BOOLEAN       := TRUE;                          -- determens if this is a simulation
+    g_nof_streams     : NATURAL       := 12;                            -- number of input streams
+    g_data_w          : NATURAL       := 14                             -- data with of input data vectors
+  );
+  PORT (
+    clk               : IN  STD_LOGIC := '0';
+    rst               : IN  STD_LOGIC;
+    in_sosi_arr       : IN  t_dp_sosi_arr;                              -- input data
+    out_of            : OUT NATURAL;                                    -- amount of internal overflow this output
+    out_mosi          : OUT t_mem_ctlr_mosi                             -- output data
+  );
+END ddrctrl;
+
+
+ARCHITECTURE str OF ddrctrl IS
+
+  -- constant for readability
+  CONSTANT  c_out_data_w : NATURAL    := g_nof_streams*g_data_w;        -- the input data with for ddrctrl_repack
+
+
+  -- signals for connecting the components
+  SIGNAL    data         : STD_LOGIC_VECTOR(c_out_data_w-1 DOWNTO 0);
+  SIGNAL    sosi         : t_dp_sosi  := c_dp_sosi_init;
+  SIGNAL    a_of           : NATURAL    := 0;
+
+BEGIN
+
+  -- makes one data vector out of all the data from the t_dp_sosi_arr
+  u_pack : ENTITY work.ddrctrl_pack
+  GENERIC MAP(
+
+    g_nof_streams     => g_nof_streams,                                 -- number of input streams
+    g_data_w          => g_data_w                                       -- data with of input data vectors
+
+  )
+  PORT MAP(
+
+    in_sosi_arr       => in_sosi_arr,                                   -- input data
+    out_data          => data                                           -- output data
+
+  );
+
+  -- resizes the input data vector so that the output data vector can be stored into the ddr memory
+  u_repack : ENTITY work.ddrctrl_repack
+  GENERIC MAP(
+    g_tech_ddr        => g_tech_ddr,                                    -- type of memory
+    g_in_data_w       => c_out_data_w                                   -- the input data with
+  )
+  PORT MAP(
+    clk               => clk,
+    rst               => rst,
+    in_data           => data,                                          -- input data
+    out_of            => a_of,                                          -- amount of internal overflow
+    out_sosi          => sosi                                           -- output data
+  );
+
+  -- creates address by counting input valids
+  u_address_counter : ENTITY work.ddrctrl_address_counter
+  GENERIC MAP(
+    g_tech_ddr        => g_tech_ddr,                                    -- type of memory
+    g_sim_model       => g_sim_model                                    -- determens if this is a simulation
+  )
+  PORT MAP(
+    clk               => clk,
+    rst               => rst,
+    in_sosi           => sosi,                                          -- input data
+    in_of             => a_of,
+    out_mosi          => out_mosi,                                      -- output data
+    out_of            => out_of
+  );
+
+END str;