Resolve L2SDP-660

Closes L2SDP-660

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_address_counter.vhd

@@ -18,7 +18,7 @@
 --
 -------------------------------------------------------------------------------
 -- Author: Job van Wee
--- Purpose: Create address by counting input valids
+-- Purpose: Creates address by counting input valids
 --
 -- Description:
 --  The counter starts on the first valid = '1' clockcylce, the counter stops 
@@ -41,43 +41,44 @@ USE dp_lib.dp_stream_pkg.ALL;
 
 ENTITY ddrctrl_address_counter IS
   GENERIC (
-    g_tech_ddr        : t_c_tech_ddr;
-    g_sim_model       : BOOLEAN := TRUE
+    g_tech_ddr        : t_c_tech_ddr;                                                                                             -- type of memory
+    g_sim_model       : BOOLEAN                           := TRUE                                                                 -- determens if this is a simulation
   );
   PORT (
-    clk               : IN  STD_LOGIC;
     rst               : IN  STD_LOGIC;
-    in_sosi           : IN  t_dp_sosi;
-    out_mosi          : OUT t_mem_ctlr_mosi := c_mem_ctlr_mosi_rst
+    in_sosi           : IN  t_dp_sosi;                                                                                            -- input data
+    out_mosi          : OUT t_mem_ctlr_mosi               := c_mem_ctlr_mosi_rst                                                  -- output data
   );
 END ddrctrl_address_counter;
 
 
 ARCHITECTURE rtl OF ddrctrl_address_counter IS
 
-  CONSTANT c_data_w   : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); --576
-  CONSTANT c_adr_w    : NATURAL := sel_a_b(g_sim_model, 4, func_tech_ddr_ctlr_address_w( g_tech_ddr )); --27;
-  CONSTANT c_max_adr  : NATURAL := 2**(c_adr_w) - 1;
+  -- constants for readability
+  CONSTANT c_data_w   : NATURAL                           := func_tech_ddr_ctlr_data_w( g_tech_ddr );                             -- the with of the input data and output data, 576
+  CONSTANT c_adr_w    : NATURAL                           := sel_a_b(g_sim_model, 4, func_tech_ddr_ctlr_address_w( g_tech_ddr )); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
+  CONSTANT c_max_adr  : NATURAL                           := 2**(c_adr_w) - 1;                                                    -- the maximal address that is possible within the vector length of the address
 
-  SIGNAL   s_adr      : NATURAL range 0 to 2**(c_adr_w)-1 := 0;
+  -- signal for storing address
+  SIGNAL   s_adr      : NATURAL range 0 to 2**(c_adr_w)-1 := 0;                                                                   -- a signal that contains the address
 
 BEGIN
 
+  -- The data is directly put through.
   out_mosi.wrdata(c_data_w - 1 DOWNTO 0) <= in_sosi.data(c_data_w - 1 DOWNTO 0);
   out_mosi.wr                            <= in_sosi.valid;
   out_mosi.address(c_adr_w -1 DOWNTO 0)  <= TO_UVEC(s_adr, c_adr_w);
 
-  p_clk : PROCESS(clk)
+  -- Increments the address each time in_sosi.valid = '1', if address = c_max_adr the address is reset to 0.
+  p_adr : PROCESS(rst, in_sosi.valid)
   BEGIN
-    IF rising_edge(clk) THEN
-      IF rst = '1' THEN
+    IF rst = '1' THEN
+      s_adr <= 0;
+    ELSIF rising_edge(in_sosi.valid) THEN
+      IF s_adr = c_max_adr THEN
         s_adr <= 0;
-      ELSIF in_sosi.valid = '1' THEN
-        IF (s_adr = c_max_adr) THEN
-          s_adr <= 0;
-        ELSE
-          s_adr <= s_adr + 1;
-        END IF;
+      ELSE
+        s_adr <= s_adr + 1;
       END IF;
     END IF;
   END PROCESS;