Prepared combinatorial master multiplexer. It compiles OK, but the verification using a test bench still needs to be done.

Added common_mem_bus.vhd with test bench. This implements a MM bus that can be used to replace the MM bus that we make with Qsys.

-Added test bench for common_pulse_delay.

Removed stratix4 architecture for common_add_sub. Changed all uses for common_add_sub to rtl implementation.

Removed common_top.vhd and dp_top.vhd from the hdllib.cfg. Such top level components for trial synthesis need to have their own unb1_<name> or unb2_<name> or stratixiv_<name> directory with hdllib.cfg in designs/.

SVN copied data and hex directories so that they can be referred to from $RADIOHDL instead of from $UNB.
SVN copied python, doc, matlab sub directories in tb or src to $RADIOHDL as well.
Only common/hdllib.cfg still refers to $UNB because some low level components (multipliers) are not technology independent yet.

Ported common_lfsr_sequences_pkg.vhd to RadioHDL and added nxt_cntr2 with alterantive in_step increment to common_lfsr_nxt_seq().

Renamed key hdl_lib_uses into hdl_lib_uses_synth and added new key hdl_lib_uses_sim for extra test_bench_files library dependencies.

Added tb_common_pulser_us_ms_s.vhd.

Renamed build_sim_dir into build_dir_sim, similar build_dir_synth. Use <tool_name>_copy_key based on build type 'sim' or 'synth' from hdltool.cfg. Renamed sim_tool_name into tool_name_sim in hdltool.cfg, similar for synth_tool_name.