Added regression_test_vhdl for common, reorder, uth.

libraries/base/common/hdllib.cfg

@@ -194,6 +194,27 @@ test_bench_files =
     tb/vhdl/tb_tb_common_rl_register.vhd
     tb/vhdl/tb_tb_common_transpose.vhd
 
+regression_test_vhdl = 
+    tb/vhdl/tb_common_fifo_rd.vhd
+    tb/vhdl/tb_common_mem_mux.vhd
+    tb/vhdl/tb_common_paged_ram_crw_crw.vhd
+    tb/vhdl/tb_common_pulser_us_ms_s.vhd
+    tb/vhdl/tb_common_select_m_symbols.vhd
+    tb/vhdl/tb_common_shiftram.vhd
+    tb/vhdl/tb_common_shiftreg.vhd
+    tb/vhdl/tb_common_transpose_symbol.vhd
+    tb/vhdl/tb_resize.vhd
+
+    tb/vhdl/tb_tb_common_adder_tree.vhd
+    tb/vhdl/tb_tb_common_add_sub.vhd
+    tb/vhdl/tb_tb_common_fanout_tree.vhd
+    tb/vhdl/tb_tb_common_multiplexer.vhd
+    tb/vhdl/tb_tb_common_operation_tree.vhd
+    tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd
+    tb/vhdl/tb_tb_common_reorder_symbol.vhd
+    tb/vhdl/tb_tb_common_rl.vhd
+    tb/vhdl/tb_tb_common_rl_register.vhd
+    tb/vhdl/tb_tb_common_transpose.vhd
     
 [modelsim_project_file]
 

libraries/base/common/tb/vhdl/tb_common_add_sub.vhd

@@ -58,6 +58,7 @@ ARCHITECTURE tb OF tb_common_add_sub IS
     RETURN TO_SVEC(v_result, g_out_dat_w);
   END;
 
+  SIGNAL tb_end          : STD_LOGIC := '0';
   SIGNAL rst             : STD_LOGIC;
   SIGNAL clk             : STD_LOGIC := '0';
   SIGNAL in_a            : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
@@ -68,9 +69,9 @@ ARCHITECTURE tb OF tb_common_add_sub IS
 
 BEGIN
 
-  clk  <= NOT clk  AFTER clk_period/2;
+  clk  <= NOT clk OR tb_end AFTER clk_period/2;
   
-  -- run 1 us
+  -- run 1 us or -all
   p_in_stimuli : PROCESS
   BEGIN
     rst <= '1';
@@ -123,6 +124,8 @@ BEGIN
         WAIT UNTIL rising_edge(clk);
       END LOOP;
     END LOOP;
+    WAIT UNTIL rising_edge(clk);
+    tb_end <= '1';
     WAIT;
   END PROCESS;
   

libraries/base/common/tb/vhdl/tb_tb_common_add_sub.vhd

@@ -26,6 +26,7 @@ ENTITY tb_tb_common_add_sub IS
 END tb_tb_common_add_sub;
 
 ARCHITECTURE tb OF tb_tb_common_add_sub IS
+  SIGNAL tb_end : STD_LOGIC := '0';  -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
 BEGIN
   -- g_direction    : STRING := "SUB";  -- "SUB" or "ADD"
   -- g_sel_add      : STD_LOGIC :='1';  -- '0' = sub, '1' = add, only valid for g_direction = "BOTH"

libraries/base/common/tb/vhdl/tb_tb_common_adder_tree.vhd

@@ -27,6 +27,7 @@ ENTITY tb_tb_common_adder_tree IS
 END tb_tb_common_adder_tree;
 
 ARCHITECTURE tb OF tb_tb_common_adder_tree IS
+  SIGNAL tb_end : STD_LOGIC := '0';  -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
 BEGIN
   -- Usage:
   -- > as 4

libraries/base/common/tb/vhdl/tb_tb_common_fanout_tree.vhd

@@ -27,6 +27,7 @@ ENTITY tb_tb_common_fanout_tree IS
 END tb_tb_common_fanout_tree;
 
 ARCHITECTURE tb OF tb_tb_common_fanout_tree IS
+  SIGNAL tb_end : STD_LOGIC := '0';  -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
 BEGIN
   -- Usage:
   -- > as 3

libraries/base/common/tb/vhdl/tb_tb_common_multiplexer.vhd

@@ -27,6 +27,7 @@ ENTITY tb_tb_common_multiplexer IS
 END tb_tb_common_multiplexer;
 
 ARCHITECTURE tb OF tb_tb_common_multiplexer IS
+  SIGNAL tb_end : STD_LOGIC := '0';  -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
 BEGIN
   -- Usage:
   -- > as 3

libraries/base/common/tb/vhdl/tb_tb_common_operation_tree.vhd

@@ -26,6 +26,7 @@ ENTITY tb_tb_common_operation_tree IS
 END tb_tb_common_operation_tree;
 
 ARCHITECTURE tb OF tb_tb_common_operation_tree IS
+  SIGNAL tb_end : STD_LOGIC := '0';  -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
 BEGIN
   -- Usage:
   -- > as 2

libraries/base/common/tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd

@@ -27,6 +27,7 @@ ENTITY tb_tb_common_paged_ram_ww_rr IS
 END tb_tb_common_paged_ram_ww_rr;
 
 ARCHITECTURE tb OF tb_tb_common_paged_ram_ww_rr IS
+  SIGNAL tb_end : STD_LOGIC := '0';  -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
 BEGIN
   -- Usage:
   -- > as 3

libraries/base/common/tb/vhdl/tb_tb_common_reorder_symbol.vhd

@@ -26,6 +26,7 @@ ENTITY tb_tb_common_reorder_symbol IS
 END tb_tb_common_reorder_symbol;
 
 ARCHITECTURE tb OF tb_tb_common_reorder_symbol IS
+  SIGNAL tb_end : STD_LOGIC := '0';  -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
 BEGIN
   -- Usage:
   -- > as 3

libraries/base/common/tb/vhdl/tb_tb_common_rl.vhd

@@ -30,6 +30,7 @@ ARCHITECTURE tb OF tb_tb_common_rl IS
 
   CONSTANT c_nof_blocks  : NATURAL := 1000;
   CONSTANT c_fifo_size   : NATURAL := 64;
+  SIGNAL tb_end : STD_LOGIC := '0';  -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
   
 BEGIN
   -- Usage:

libraries/base/common/tb/vhdl/tb_tb_common_rl_register.vhd

@@ -30,6 +30,7 @@ ARCHITECTURE tb OF tb_tb_common_rl_register IS
 
   CONSTANT c_nof_blocks  : NATURAL := 1000;
   CONSTANT c_fifo_size   : NATURAL := 64;
+  SIGNAL tb_end : STD_LOGIC := '0';  -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
 
 BEGIN
   -- Usage:

libraries/base/common/tb/vhdl/tb_tb_common_transpose.vhd

@@ -31,7 +31,7 @@ ENTITY tb_tb_common_transpose IS
 END tb_tb_common_transpose;
 
 ARCHITECTURE tb OF tb_tb_common_transpose IS
-
+  SIGNAL tb_end : STD_LOGIC := '0';  -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
 BEGIN
 
 --                                                            g_pipeline_shiftreg  : NATURAL := 0;

libraries/base/common_mult/hdllib.cfg

@@ -18,6 +18,12 @@ test_bench_files =
 
     tb/vhdl/tb_tb_common_mult.vhd
 
+regression_test_vhdl = 
+    tb/vhdl/tb_common_mult_add2.vhd
+    tb/vhdl/tb_common_complex_mult.vhd
+
+    tb/vhdl/tb_tb_common_mult.vhd
+
     
 [modelsim_project_file]
 

libraries/base/reorder/hdllib.cfg

@@ -32,6 +32,9 @@ test_bench_files =
     tb/vhdl/tb_mmf_reorder_matrix.vhd     
     tb/vhdl/tb_mmf_reorder_row.vhd     
 
+regression_test_vhdl = 
+    tb/vhdl/tb_tb_reorder_col.vhd    
+
 
 [modelsim_project_file]
 modelsim_compile_ip_files =

libraries/base/reorder/tb/vhdl/tb_tb_reorder_col.vhd

@@ -29,6 +29,7 @@ ARCHITECTURE tb OF tb_tb_reorder_col IS
 
   CONSTANT c_nof_sync       : NATURAL := 20;
   CONSTANT c_reverse_ss_map : BOOLEAN := TRUE;
+  SIGNAL tb_end : STD_LOGIC := '0';  -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
   
 BEGIN
 

libraries/base/uth/hdllib.cfg

@@ -22,6 +22,11 @@ test_bench_files =
     tb/vhdl/tb_tb_uth_terminals.vhd
     tb/vhdl/tb_tb_tb_uth_regression.vhd
 
+regression_test_vhdl = 
+    tb/vhdl/tb_tb_uth.vhd
+    tb/vhdl/tb_tb_uth_dp_packet.vhd
+    tb/vhdl/tb_tb_uth_terminals.vhd
+
     
 [modelsim_project_file]
 

libraries/base/uth/tb/vhdl/tb_tb_uth.vhd

@@ -35,6 +35,7 @@ ARCHITECTURE tb OF tb_tb_uth IS
 
   CONSTANT c_phy_link_valid_support : BOOLEAN := TRUE;
   CONSTANT c_nof_repeat             : NATURAL := 10;
+  SIGNAL tb_end : STD_LOGIC := '0';  -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
 
 BEGIN
 

libraries/base/uth/tb/vhdl/tb_tb_uth_dp_packet.vhd

@@ -35,6 +35,7 @@ ARCHITECTURE tb OF tb_tb_uth_dp_packet IS
 
   CONSTANT c_phy_link_valid_support : BOOLEAN := TRUE;
   CONSTANT c_nof_repeat             : NATURAL := 10;
+  SIGNAL tb_end : STD_LOGIC := '0';  -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
   
 BEGIN
 

libraries/base/uth/tb/vhdl/tb_tb_uth_terminals.vhd

@@ -35,6 +35,7 @@ ARCHITECTURE tb OF tb_tb_uth_terminals IS
 
   CONSTANT c_phy_link_valid_support : BOOLEAN := TRUE;
   CONSTANT c_nof_repeat             : NATURAL := 100;
+  SIGNAL tb_end : STD_LOGIC := '0';  -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
 
 BEGIN