L2SDP-180, processed review comments.

libraries/base/common/hdllib.cfg

@@ -217,6 +217,7 @@ regression_test_vhdl =
     tb/vhdl/tb_common_shiftram.vhd
     tb/vhdl/tb_common_shiftreg.vhd
     tb/vhdl/tb_common_transpose_symbol.vhd
+    tb/vhdl/tb_common_variable_delay.vhd
     tb/vhdl/tb_resize.vhd
     #tb/vhdl/tb_round.vhd           -- has no self verification yet
     tb/vhdl/tb_requantize.vhd

libraries/base/common/src/vhdl/common_variable_delay.vhd

@@ -23,7 +23,7 @@
 -- . Delay input pulse by number of given delay cycles
 -- Description:
 -- . delay input pulse by nof_cycles_delay
--- . output pulse is derived form low-high transition of input pulse.
+-- . output pulse is derived from low-high transition of input pulse.
 -- . during delay other input pulses are ignored
 -- --------------------------------------------------------------------------
 
@@ -33,11 +33,14 @@ USE work.common_pkg.ALL;
 
 
 ENTITY common_variable_delay IS
+  GENERIC (
+    g_max_delay : NATURAL := 200 * 10**6
+  );
   PORT (
     rst        : IN  STD_LOGIC;
     clk        : IN  STD_LOGIC;
 
-    delay      : IN  NATURAL := 0;
+    delay      : IN  NATURAL RANGE 0 TO g_max_delay := 0;
     enable     : IN  STD_LOGIC := '0';
     in_val     : IN  STD_LOGIC;
     out_val    : OUT STD_LOGIC
@@ -48,40 +51,40 @@ END common_variable_delay;
 ARCHITECTURE rtl OF common_variable_delay IS
 
   SIGNAL i_out_val       : STD_LOGIC;
-  SIGNAL nxt_i_out_val   : STD_LOGIC;
+  SIGNAL nxt_out_val     : STD_LOGIC;
   SIGNAL delay_cnt       : NATURAL;
   SIGNAL nxt_delay_cnt   : NATURAL;
-  SIGNAL in_val_lock     : STD_LOGIC;
-  SIGNAL nxt_in_val_lock : STD_LOGIC;
+  SIGNAL in_val_lock     : STD_LOGIC := '0';
+  SIGNAL prev_in_val     : STD_LOGIC := '0';
 
 BEGIN
-  out_val <= i_out_val; -- AND enable;
+  out_val <= i_out_val;
   
-  p_delay: PROCESS(enable, delay, in_val, i_out_val, delay_cnt, in_val_lock)
+  p_delay: PROCESS(enable, in_val, prev_in_val, in_val_lock, nxt_delay_cnt, delay_cnt, delay, i_out_val)
   BEGIN
-    nxt_i_out_val   <= '0';
-    nxt_delay_cnt   <= delay_cnt + 1;
-    nxt_in_val_lock <= in_val_lock;
 
     IF enable = '1' THEN
-      IF rising_edge(in_val) THEN
-        nxt_in_val_lock <= '1';
-        IF delay = 0 THEN
-          nxt_delay_cnt <= 0;  
-        END IF;
+      IF in_val = '1' AND prev_in_val = '0' THEN  -- detect rising_edge of in_val
+        in_val_lock <= '1';
       END IF;
 
-      IF nxt_in_val_lock = '0' THEN
+      IF in_val_lock = '1' THEN
+        IF delay_cnt = delay THEN
+          nxt_out_val <= '1';
+        END IF;  
+        nxt_delay_cnt <= delay_cnt + 1;
+      ELSE
         nxt_delay_cnt <= 0;
       END IF;
 
-      IF nxt_delay_cnt = (delay+1) THEN
-        nxt_i_out_val   <= '1';
-        nxt_in_val_lock <= '0';
+      IF i_out_val = '1' THEN 
+        nxt_out_val <= '0';
+        in_val_lock <= '0';
       END IF;
     ELSE
       nxt_delay_cnt <= 0;
-      nxt_in_val_lock <= '0';
+      nxt_out_val   <= '0';
+      in_val_lock   <= '0';
     END IF;
 
   END PROCESS; 
@@ -91,11 +94,11 @@ BEGIN
     IF rst = '1' THEN
       i_out_val   <= '0';
       delay_cnt   <= 0;
-      in_val_lock <= '0';
+      prev_in_val <= '0';
     ELSIF rising_edge(clk) THEN
-      i_out_val   <= nxt_i_out_val;
+      i_out_val   <= nxt_out_val;
       delay_cnt   <= nxt_delay_cnt;
-      in_val_lock <= nxt_in_val_lock;
+      prev_in_val <= in_val;
     END IF;
   END PROCESS;
 

libraries/base/common/src/vhdl/mms_common_variable_delay.vhd

@@ -57,7 +57,6 @@ ARCHITECTURE rtl OF mms_common_variable_delay IS
 
   SIGNAL enable : STD_LOGIC := '0';
 
-
 BEGIN
   enable <= sl(enable_reg);
   

libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd

@@ -40,7 +40,7 @@ ARCHITECTURE tb OF tb_common_variable_delay IS
 
   CONSTANT c_clk_period       : TIME    := 10 ns;
   CONSTANT c_trigger_interval : NATURAL := 40;  -- in clk's
-  CONSTANT c_trigger_latency  : NATURAL := 3;  -- in clk's
+  CONSTANT c_trigger_latency  : NATURAL := 1;  -- in clk's
   CONSTANT c_delay_arr        : t_natural_arr(0 TO 3) := (0, 1, 3, 12);
   
   SIGNAL tb_end : STD_LOGIC := '0';
@@ -58,17 +58,7 @@ BEGIN
   rst <= '1', '0' AFTER c_clk_period*4;
 
   -- generate trigger signal
-  p_trigger : PROCESS
-  BEGIN
-    WAIT UNTIL rst = '0';
-    proc_common_wait_some_cycles(clk, 10);
-    WAIT UNTIL rising_edge(clk);
-    WHILE tb_end = '0' LOOP
-      trigger <= NOT trigger;
-      proc_common_wait_some_cycles(clk, c_trigger_interval/2);
-    END LOOP;
-    WAIT;
-  END PROCESS;
+  proc_common_gen_pulse(c_trigger_interval/2, c_trigger_interval, '1', rst, clk, trigger);
 
   
   p_in_stimuli : PROCESS

libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd

@@ -86,17 +86,7 @@ BEGIN
   END PROCESS;
 
   -- generate trigger signal
-  p_trigger : PROCESS
-  BEGIN
-    WAIT UNTIL rst = '0';
-    proc_common_wait_some_cycles(clk, 10);
-    WAIT UNTIL rising_edge(clk);
-    WHILE tb_end = '0' LOOP
-      trigger <= NOT trigger;
-      proc_common_wait_some_cycles(clk, c_trigger_interval/2);
-    END LOOP;
-    WAIT;
-  END PROCESS;
+  proc_common_gen_pulse(c_trigger_interval/2, c_trigger_interval, '1', rst, clk, trigger);
 
   -- device under test
   u_dut : ENTITY work.mms_common_variable_delay