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Commit 9027f957 authored by Eric Kooistra's avatar Eric Kooistra
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SVN copied all VHDL files that were still referred to from $UNB to $RADIOHDL. 

SVN copied data and hex directories so that they can be referred to from $RADIOHDL instead of from $UNB.
SVN copied python, doc, matlab sub directories in tb or src to $RADIOHDL as well.
Only common/hdllib.cfg still refers to $UNB because some low level components (multipliers) are not technology independent yet.
parent ecf1a915
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applications/apertif/systems/apertif_bg_xc/hdllib.cfg
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− 1
View file @ 9027f957
......@@ -7,7 +7,7 @@ hdl_lib_technology = ip_stratixiv
modelsim_copy_files =
../../designs/apertif_unb1_fn_bf_emu/src/hex/ hex/
$UNB/Firmware/dsp/filter/build/data/ mif
$RADIOHDL/libraries/dsp/filter/src/hex/ mif
synth_files =
......
libraries/base/common/data/tb_requantize_s_dat.out 0 → 100644
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libraries/base/common/data/tb_requantize_s_ovr.out 0 → 100644
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libraries/base/common/data/tb_requantize_u_dat.out 0 → 100644
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libraries/base/common/data/tb_requantize_u_ovr.out 0 → 100644
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libraries/base/common/doc/ASTRON_RP_415_common_mem.doc 0 → 100644
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libraries/base/common/doc/ASTRON_RP_415_common_mem.pdf 0 → 100644
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libraries/base/common/doc/ASTRON_RP_415_common_mem.vsd 0 → 100644
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libraries/base/common/doc/common.txt 0 → 100644
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Contents:
1) Introduction
2) Pipeline
3) Math +, *
4) RAM
5) FIFO
6) IO
7) Auxiliary
1) Introduction
The common(pkg) contains useful constants and functions. The common library
contains entities that may be use in any VHDL design. Each entity typically
has several architectures:
. rtl = Register Transfer Level VHDL that will cause the synthesis tool
to infer appropriate build in blocks and logic
. stratix4 = Block created with the Altera MegaWizard for Stratix IV
. virtex4 = Block created with the Xilinx Core Generator for Virtex 4
2) Pipeline
The pipeline entity supports any width >= 1 and any pipeline >= 0. Note:
. A pipeline of 0 implies a wire (a combinatorial short)
. For large pipeline values one better uses a FIFO
3) Math +, *
The math entities provides:
. Basic building blocks for +, * and several combinations of *, + that can be
mapped efficiently on FPGA DSP resources.
. Some higher level DSP blocks that like e.g. common_adder_tree.
4) RAM
The used memory naming convention is as follows (by example):
. r = single port read only memory (ROM)
. rw = single port ram, shared address for both write read address
. r_w = dual port ram with separate write address and read address
. rw_rw = dual port ram with separate address per port
. cr_cw = dual port ram with separate clock and address per port one r one w
. crw_crw = dual port ram with separate clock and address per port both rw
Note:
- Using a r_w RAM with the same address effectively makes it a rw RAM
- Using a rw_rw RAM with only a write port and a read port effectively makes it
a r_w RAM
- Using a crw_crw RAM with the same clock effectively makes it a rw_rw RAM
==> The crw_crw RAM covers all other variants either by
. not using some input (set to constant value)
. not using some output ports (left open)
. connecting some input ports together (clk or address).
For clarity and optimal synthesis it may be wise to at least have:
. common_rom.vhd
. common_ram_r_w.vhd -- covers also rw
. common_ram_crw_crw.vhd -- covers also rw_rw
The memories all have the same data width for both read and write and also for
both ports. Different aspect ratio memories (e.g. write byte, read word) are
less common, so they can be added to the common library when needed. Typcially
different aspect ratio memories can not be inferred from RTL code.
The memory also have the following control signals:
. rst = asynchronous reset
. clken = clock enable per clock domain
. wr_en = write enable per port
. rd_en = read enable per port
. rd_val = read valid per port
Typcially the rd_en is not needed (i.e. always '1'), the read data then always
shows the data for the read address. The rd_en is then only used to drive
rd_val to account for the memory read latency.
The RAM contents can not be reset, only the I/O registers. Reseting the data
I/O registers is of little use. Therefore use RAM without reset, except for
letting apply the rst input to rd_val.
5) FIFO
Single clock (sc) and dual clock (dc) FIFOs will be needed.
a) common_fifo_sc.vhd
b) common_fifo_dc.vhd
6) IO
a) common_inout -- tristate buffer
7) Auxiliary
a) common_switch
b) common_pulse_extend
c) common_counter
libraries/base/common/hdllib.cfg
+ 159
− 157
View file @ 9027f957
......@@ -6,15 +6,15 @@ hdl_lib_uses_sim =
hdl_lib_technology =
synth_files =
$UNB/Firmware/modules/common/src/vhdl/common_pkg.vhd
$UNB/Firmware/modules/common/src/vhdl/common_str_pkg.vhd
src/vhdl/common_pkg.vhd
src/vhdl/common_str_pkg.vhd
src/vhdl/common_mem_pkg.vhd
$UNB/Firmware/modules/common/src/vhdl/common_field_pkg.vhd
src/vhdl/common_field_pkg.vhd
src/vhdl/common_lfsr_sequences_pkg.vhd
src/vhdl/common_interface_layers_pkg.vhd
src/vhdl/common_network_layers_pkg.vhd
src/vhdl/common_network_total_header_pkg.vhd
$UNB/Firmware/modules/common/src/vhdl/common_components_pkg.vhd
src/vhdl/common_components_pkg.vhd
$UNB/Firmware/modules/MegaWizard/arith/lut_add_sub.vhd
$UNB/Firmware/modules/MegaWizard/arith/dsp_add_sub.vhd
......@@ -22,17 +22,17 @@ synth_files =
$UNB/Firmware/modules/MegaWizard/arith/dsp_mult_add4.vhd
$UNB/Firmware/modules/MegaWizard/arith/dsp_complex_mult.vhd
#$UNB/Firmware/modules/common/src/ip/MegaWizard/iobuf_in.vhd
#src/ip/MegaWizard/iobuf_in.vhd
$UNB/Firmware/modules/common/src/vhdl/common_async.vhd
$UNB/Firmware/modules/common/src/vhdl/common_async_slv.vhd
$UNB/Firmware/modules/common/src/vhdl/common_areset.vhd
$UNB/Firmware/modules/common/src/vhdl/common_acapture.vhd
$UNB/Firmware/modules/common/src/vhdl/common_acapture_slv.vhd
$UNB/Firmware/modules/common/src/vhdl/common_pipeline.vhd
$UNB/Firmware/modules/common/src/vhdl/common_pipeline_sl.vhd
$UNB/Firmware/modules/common/src/vhdl/common_pipeline_integer.vhd
$UNB/Firmware/modules/common/src/vhdl/common_pipeline_natural.vhd
src/vhdl/common_async.vhd
src/vhdl/common_async_slv.vhd
src/vhdl/common_areset.vhd
src/vhdl/common_acapture.vhd
src/vhdl/common_acapture_slv.vhd
src/vhdl/common_pipeline.vhd
src/vhdl/common_pipeline_sl.vhd
src/vhdl/common_pipeline_integer.vhd
src/vhdl/common_pipeline_natural.vhd
src/vhdl/common_ram_crw_crw_ratio.vhd
src/vhdl/common_ram_cr_cw_ratio.vhd
......@@ -51,175 +51,177 @@ synth_files =
src/vhdl/common_ddio_in.vhd
src/vhdl/common_ddio_out.vhd
$UNB/Firmware/modules/common/src/vhdl/common_wideband_data_scope.vhd
#$UNB/Firmware/modules/common/src/vhdl/common_iobuf_in.vhd
src/vhdl/common_wideband_data_scope.vhd
#src/vhdl/common_iobuf_in.vhd
#$UNB/Firmware/modules/common/src/vhdl/common_iobuf_in_a_stratix4.vhd
$UNB/Firmware/modules/common/src/vhdl/common_inout.vhd
$UNB/Firmware/modules/common/src/vhdl/common_fanout.vhd
$UNB/Firmware/modules/common/src/vhdl/common_fanout_tree.vhd
$UNB/Firmware/modules/common/src/vhdl/common_ddreg.vhd
$UNB/Firmware/modules/common/src/vhdl/common_ddreg_slv.vhd
$UNB/Firmware/modules/common/src/vhdl/common_evt.vhd
$UNB/Firmware/modules/common/src/vhdl/common_flank_to_pulse.vhd
$UNB/Firmware/modules/common/src/vhdl/common_toggle.vhd
$UNB/Firmware/modules/common/src/vhdl/common_switch.vhd
$UNB/Firmware/modules/common/src/vhdl/common_request.vhd
$UNB/Firmware/modules/common/src/vhdl/common_pulse_extend.vhd
$UNB/Firmware/modules/common/src/vhdl/common_spulse.vhd
$UNB/Firmware/modules/common/src/vhdl/common_counter.vhd
$UNB/Firmware/modules/common/src/vhdl/common_init.vhd
src/vhdl/common_inout.vhd
src/vhdl/common_fanout.vhd
src/vhdl/common_fanout_tree.vhd
src/vhdl/common_ddreg.vhd
src/vhdl/common_ddreg_slv.vhd
src/vhdl/common_evt.vhd
src/vhdl/common_flank_to_pulse.vhd
src/vhdl/common_toggle.vhd
src/vhdl/common_switch.vhd
src/vhdl/common_request.vhd
src/vhdl/common_pulse_extend.vhd
src/vhdl/common_spulse.vhd
src/vhdl/common_counter.vhd
src/vhdl/common_init.vhd
src/vhdl/common_pulser.vhd
src/vhdl/common_pulser_us_ms_s.vhd
src/vhdl/common_led_controller.vhd
$UNB/Firmware/modules/common/src/vhdl/common_debounce.vhd
$UNB/Firmware/modules/common/src/vhdl/common_frame_busy.vhd
$UNB/Firmware/modules/common/src/vhdl/common_stable_delayed.vhd
$UNB/Firmware/modules/common/src/vhdl/common_stable_monitor.vhd
$UNB/Firmware/modules/common/src/vhdl/common_interval_monitor.vhd
$UNB/Firmware/modules/common/src/vhdl/common_clock_active_detector.vhd
$UNB/Firmware/modules/common/src/vhdl/common_clock_phase_detector.vhd
$UNB/Firmware/modules/common/src/vhdl/common_resize.vhd
$UNB/Firmware/modules/common/src/vhdl/common_round.vhd
$UNB/Firmware/modules/common/src/vhdl/common_requantize.vhd
$UNB/Firmware/modules/common/src/vhdl/common_clip.vhd
$UNB/Firmware/modules/common/src/vhdl/common_pipeline_symbol.vhd
$UNB/Firmware/modules/common/src/vhdl/common_shiftreg.vhd
$UNB/Firmware/modules/common/src/vhdl/common_shiftreg_symbol.vhd
$UNB/Firmware/modules/common/src/vhdl/common_add_symbol.vhd
$UNB/Firmware/modules/common/src/vhdl/common_select_symbol.vhd
$UNB/Firmware/modules/common/src/vhdl/common_select_m_symbols.vhd
$UNB/Firmware/modules/common/src/vhdl/common_reorder_symbol.vhd
$UNB/Firmware/modules/common/src/vhdl/common_multiplexer.vhd
$UNB/Firmware/modules/common/src/vhdl/common_demultiplexer.vhd
$UNB/Firmware/modules/common/src/vhdl/common_transpose_symbol.vhd
$UNB/Firmware/modules/common/src/vhdl/common_transpose.vhd
$UNB/Firmware/modules/common/src/vhdl/common_complex_round.vhd
$UNB/Firmware/modules/common/src/vhdl/common_add_sub.vhd
src/vhdl/common_debounce.vhd
src/vhdl/common_frame_busy.vhd
src/vhdl/common_stable_delayed.vhd
src/vhdl/common_stable_monitor.vhd
src/vhdl/common_interval_monitor.vhd
src/vhdl/common_clock_active_detector.vhd
src/vhdl/common_clock_phase_detector.vhd
src/vhdl/common_resize.vhd
src/vhdl/common_round.vhd
src/vhdl/common_requantize.vhd
src/vhdl/common_clip.vhd
src/vhdl/common_pipeline_symbol.vhd
src/vhdl/common_shiftreg.vhd
src/vhdl/common_shiftreg_symbol.vhd
src/vhdl/common_add_symbol.vhd
src/vhdl/common_select_symbol.vhd
src/vhdl/common_select_m_symbols.vhd
src/vhdl/common_reorder_symbol.vhd
src/vhdl/common_multiplexer.vhd
src/vhdl/common_demultiplexer.vhd
src/vhdl/common_transpose_symbol.vhd
src/vhdl/common_transpose.vhd
src/vhdl/common_complex_round.vhd
src/vhdl/common_add_sub.vhd
$UNB/Firmware/modules/common/src/vhdl/common_add_sub_a_stratix4.vhd
$UNB/Firmware/modules/common/src/vhdl/common_add_sub_a_rtl.vhd
$UNB/Firmware/modules/common/src/vhdl/common_complex_add_sub.vhd
$UNB/Firmware/modules/common/src/vhdl/common_accumulate.vhd
$UNB/Firmware/modules/common/src/vhdl/common_int2float.vhd
$UNB/Firmware/modules/common/src/vhdl/common_adder_staged.vhd
$UNB/Firmware/modules/common/src/vhdl/common_adder_tree.vhd
$UNB/Firmware/modules/common/src/vhdl/common_adder_tree_a_recursive.vhd
$UNB/Firmware/modules/common/src/vhdl/common_adder_tree_a_str.vhd
$UNB/Firmware/modules/common/src/vhdl/common_operation.vhd
$UNB/Firmware/modules/common/src/vhdl/common_operation_tree.vhd
$UNB/Firmware/modules/common/src/vhdl/common_mult.vhd
src/vhdl/common_complex_add_sub.vhd
src/vhdl/common_accumulate.vhd
src/vhdl/common_int2float.vhd
src/vhdl/common_adder_staged.vhd
src/vhdl/common_adder_tree.vhd
src/vhdl/common_adder_tree_a_recursive.vhd
src/vhdl/common_adder_tree_a_str.vhd
src/vhdl/common_operation.vhd
src/vhdl/common_operation_tree.vhd
src/vhdl/common_mult.vhd
$UNB/Firmware/modules/common/src/vhdl/common_mult_a_stratix4.vhd
$UNB/Firmware/modules/common/src/vhdl/common_mult_a_rtl.vhd
$UNB/Firmware/modules/common/src/vhdl/common_mult_add2.vhd
src/vhdl/common_mult_add2.vhd
$UNB/Firmware/modules/common/src/vhdl/common_mult_add2_a_stratix4.vhd
$UNB/Firmware/modules/common/src/vhdl/common_mult_add2_a_rtl_stratix4.vhd
$UNB/Firmware/modules/common/src/vhdl/common_mult_add2_a_rtl.vhd
$UNB/Firmware/modules/common/src/vhdl/common_mult_add4.vhd
src/vhdl/common_mult_add4.vhd
$UNB/Firmware/modules/common/src/vhdl/common_mult_add4_a_stratix4.vhd
$UNB/Firmware/modules/common/src/vhdl/common_mult_add4_a_rtl.vhd
$UNB/Firmware/modules/common/src/vhdl/common_complex_mult.vhd
src/vhdl/common_complex_mult.vhd
$UNB/Firmware/modules/common/src/vhdl/common_complex_mult_a_stratix4.vhd
$UNB/Firmware/modules/common/src/vhdl/common_complex_mult_a_str_stratix4.vhd
$UNB/Firmware/modules/common/src/vhdl/common_complex_mult_add.vhd
src/vhdl/common_complex_mult_add.vhd
$UNB/Firmware/modules/common/src/vhdl/common_complex_mult_add_parallel.vhd
$UNB/Firmware/modules/common/src/vhdl/common_complex_mult_add_pipeline.vhd
$UNB/Firmware/modules/common/src/vhdl/common_rl_decrease.vhd
$UNB/Firmware/modules/common/src/vhdl/common_rl_increase.vhd
$UNB/Firmware/modules/common/src/vhdl/common_rl_register.vhd
$UNB/Firmware/modules/common/src/vhdl/common_fifo_rd.vhd
$UNB/Firmware/modules/common/src/vhdl/common_blockreg.vhd
$UNB/Firmware/modules/common/src/vhdl/common_fifo_dc_lock_control.vhd
src/vhdl/common_rl_decrease.vhd
src/vhdl/common_rl_increase.vhd
src/vhdl/common_rl_register.vhd
src/vhdl/common_fifo_rd.vhd
src/vhdl/common_blockreg.vhd
src/vhdl/common_fifo_dc_lock_control.vhd
src/vhdl/common_mem_mux.vhd
src/vhdl/common_mem_demux.vhd
$UNB/Firmware/modules/common/src/vhdl/common_reg_cross_domain.vhd
$UNB/Firmware/modules/common/src/vhdl/common_reg_r_w.vhd
$UNB/Firmware/modules/common/src/vhdl/common_reg_r_w_dc.vhd
$UNB/Firmware/modules/common/src/vhdl/common_interleave.vhd
$UNB/Firmware/modules/common/src/vhdl/common_deinterleave.vhd
$UNB/Firmware/modules/common/src/vhdl/common_reinterleave.vhd
$UNB/Firmware/modules/common/src/vhdl/common_paged_reg.vhd
$UNB/Firmware/modules/common/src/vhdl/common_paged_ram_crw_crw.vhd
$UNB/Firmware/modules/common/src/vhdl/common_paged_ram_rw_rw.vhd
$UNB/Firmware/modules/common/src/vhdl/common_paged_ram_r_w.vhd
$UNB/Firmware/modules/common/src/vhdl/common_paged_ram_ww_rr.vhd
$UNB/Firmware/modules/common/src/vhdl/common_paged_ram_w_rr.vhd
$UNB/Firmware/modules/common/src/vhdl/common_zip.vhd
$UNB/Firmware/modules/common/src/vhdl/common_duty_cycle.vhd
$UNB/Firmware/modules/common/src/vhdl/common_bit_delay.vhd
$UNB/Firmware/modules/common/src/vhdl/common_delay.vhd
$UNB/Firmware/modules/common/src/vhdl/common_shiftram.vhd
$UNB/Firmware/modules/common/src/vhdl/mms_common_reg.vhd
$UNB/Firmware/modules/common/src/vhdl/mms_common_stable_monitor.vhd
$UNB/Firmware/modules/common/src/vhdl/avs_common_mm.vhd
$UNB/Firmware/modules/common/src/vhdl/avs_common_mm_irq.vhd
$UNB/Firmware/modules/common/src/vhdl/avs_common_mm_readlatency0.vhd
$UNB/Firmware/modules/common/src/vhdl/avs_common_mm_readlatency2.vhd
$UNB/Firmware/modules/common/src/vhdl/avs_common_reg_r_w.vhd
$UNB/Firmware/modules/common/build/synth/quartus/common_top.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_pkg.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_mem_pkg.vhd
src/vhdl/common_reg_cross_domain.vhd
src/vhdl/common_reg_r_w.vhd
src/vhdl/common_reg_r_w_dc.vhd
src/vhdl/common_interleave.vhd
src/vhdl/common_deinterleave.vhd
src/vhdl/common_reinterleave.vhd
src/vhdl/common_paged_reg.vhd
src/vhdl/common_paged_ram_crw_crw.vhd
src/vhdl/common_paged_ram_rw_rw.vhd
src/vhdl/common_paged_ram_r_w.vhd
src/vhdl/common_paged_ram_ww_rr.vhd
src/vhdl/common_paged_ram_w_rr.vhd
src/vhdl/common_zip.vhd
src/vhdl/common_duty_cycle.vhd
src/vhdl/common_bit_delay.vhd
src/vhdl/common_delay.vhd
src/vhdl/common_shiftram.vhd
src/vhdl/mms_common_reg.vhd
src/vhdl/mms_common_stable_monitor.vhd
src/vhdl/avs_common_mm.vhd
src/vhdl/avs_common_mm_irq.vhd
src/vhdl/avs_common_mm_readlatency0.vhd
src/vhdl/avs_common_mm_readlatency2.vhd
src/vhdl/avs_common_reg_r_w.vhd
build/synth/quartus/common_top.vhd
tb/vhdl/tb_common_pkg.vhd
tb/vhdl/tb_common_mem_pkg.vhd
test_bench_files =
$UNB/Firmware/modules/common/tb/vhdl/tb_common_acapture.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_add_sub.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_adder_tree.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_async.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_clock_phase_detector.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_complex_mult.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_complex_mult_add_parallel.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_complex_mult_add_pipeline.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_counter.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_ddreg.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_debounce.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_duty_cycle.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_fanout_tree.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_fifo_dc_mixed_widths.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_fifo_rd.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_flank_to_pulse.vhd
#$UNB/Firmware/modules/common/tb/vhdl/tb_common_iobuf_in.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_init.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_int2float.vhd
tb/vhdl/tb_common_acapture.vhd
tb/vhdl/tb_common_add_sub.vhd
tb/vhdl/tb_common_adder_tree.vhd
tb/vhdl/tb_common_async.vhd
tb/vhdl/tb_common_clock_phase_detector.vhd
tb/vhdl/tb_common_complex_mult.vhd
tb/vhdl/tb_common_complex_mult_add_parallel.vhd
tb/vhdl/tb_common_complex_mult_add_pipeline.vhd
tb/vhdl/tb_common_counter.vhd
tb/vhdl/tb_common_ddreg.vhd
tb/vhdl/tb_common_debounce.vhd
tb/vhdl/tb_common_duty_cycle.vhd
tb/vhdl/tb_common_fanout_tree.vhd
tb/vhdl/tb_common_fifo_dc_mixed_widths.vhd
tb/vhdl/tb_common_fifo_rd.vhd
tb/vhdl/tb_common_flank_to_pulse.vhd
#tb/vhdl/tb_common_iobuf_in.vhd
tb/vhdl/tb_common_init.vhd
tb/vhdl/tb_common_int2float.vhd
tb/vhdl/tb_common_led_controller.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_mem_mux.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_mult.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_mult_add2.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_multiplexer.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_operation_tree.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_paged_ram_crw_crw.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_paged_ram_ww_rr.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_pulse_extend.vhd
tb/vhdl/tb_common_mem_mux.vhd
tb/vhdl/tb_common_mult.vhd
tb/vhdl/tb_common_mult_add2.vhd
tb/vhdl/tb_common_multiplexer.vhd
tb/vhdl/tb_common_operation_tree.vhd
tb/vhdl/tb_common_paged_ram_crw_crw.vhd
tb/vhdl/tb_common_paged_ram_ww_rr.vhd
tb/vhdl/tb_common_pulse_extend.vhd
tb/vhdl/tb_common_pulser.vhd
tb/vhdl/tb_common_pulser_us_ms_s.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_reg_cross_domain.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_reinterleave.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_reorder_symbol.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_rl.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_rl_register.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_select_m_symbols.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_shiftram.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_shiftreg.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_spulse.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_switch.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_toggle.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_transpose.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_transpose_symbol.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_zip.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_requantize.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_resize.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_round.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_tb_common_add_sub.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_tb_common_adder_tree.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_tb_common_fanout_tree.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_tb_common_mult.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_tb_common_multiplexer.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_tb_common_operation_tree.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_tb_common_reinterleave.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_tb_common_reorder_symbol.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_tb_common_rl.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_tb_common_rl_register.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_tb_common_transpose.vhd
tb/vhdl/tb_common_reg_cross_domain.vhd
tb/vhdl/tb_common_reinterleave.vhd
tb/vhdl/tb_common_reorder_symbol.vhd
tb/vhdl/tb_common_rl.vhd
tb/vhdl/tb_common_rl_register.vhd
tb/vhdl/tb_common_select_m_symbols.vhd
tb/vhdl/tb_common_shiftram.vhd
tb/vhdl/tb_common_shiftreg.vhd
tb/vhdl/tb_common_spulse.vhd
tb/vhdl/tb_common_switch.vhd
tb/vhdl/tb_common_toggle.vhd
tb/vhdl/tb_common_transpose.vhd
tb/vhdl/tb_common_transpose_symbol.vhd
tb/vhdl/tb_common_zip.vhd
tb/vhdl/tb_requantize.vhd
tb/vhdl/tb_resize.vhd
tb/vhdl/tb_round.vhd
tb/vhdl/tb_tb_common_add_sub.vhd
tb/vhdl/tb_tb_common_adder_tree.vhd
tb/vhdl/tb_tb_common_fanout_tree.vhd
tb/vhdl/tb_tb_common_mult.vhd
tb/vhdl/tb_tb_common_multiplexer.vhd
tb/vhdl/tb_tb_common_operation_tree.vhd
tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd
tb/vhdl/tb_tb_common_reinterleave.vhd
tb/vhdl/tb_tb_common_reorder_symbol.vhd
tb/vhdl/tb_tb_common_rl.vhd
tb/vhdl/tb_tb_common_rl_register.vhd
tb/vhdl/tb_tb_common_transpose.vhd
libraries/base/common/src/vhdl/avs_common_mm.vhd 0 → 100644
+ 77
− 0
View file @ 9027f957
-------------------------------------------------------------------------------
--
-- Copyright (C) 2011
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose: AVS wrapper to make a MM slave port available as conduit
-- Description:
-- Via this wrapper any MM slave register or RAM component can be made
-- accessible to SOPC Builder. This avoids having to make a dedicated
-- *_hw.tcl for each module or component that has MM slave ports.
-- Remark:
-- . The avs_common_mm_hw.tcl will determines the read latency, which is
-- typically 1.
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY avs_common_mm IS
GENERIC (
g_adr_w : NATURAL := 5;
g_dat_w : NATURAL := 32
);
PORT (
-- MM side
csi_system_reset : IN STD_LOGIC;
csi_system_clk : IN STD_LOGIC;
avs_mem_address : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
avs_mem_write : IN STD_LOGIC;
avs_mem_writedata : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
avs_mem_read : IN STD_LOGIC;
avs_mem_readdata : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
-- User side
coe_reset_export : OUT STD_LOGIC;
coe_clk_export : OUT STD_LOGIC;
coe_address_export : OUT STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
coe_write_export : OUT STD_LOGIC;
coe_writedata_export : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
coe_read_export : OUT STD_LOGIC;
coe_readdata_export : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
);
END avs_common_mm;
ARCHITECTURE wrap OF avs_common_mm IS
BEGIN
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
coe_address_export <= avs_mem_address;
coe_write_export <= avs_mem_write;
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
END wrap;
\ No newline at end of file
libraries/base/common/src/vhdl/avs_common_mm_hw.tcl 0 → 100644
+ 195
− 0
View file @ 9027f957
# TCL File Generated by Component Editor 10.0
# Wed Apr 20 10:30:05 CEST 2011
# DO NOT MODIFY
# +-----------------------------------
# |
# | avs_common_mm "avs_common_mm" v1.0
# | ASTRON 2011.04.20.10:30:05
# | MM slave port to conduit with read latency 1
# |
# | D:/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd
# |
# | ./avs_common_mm.vhd syn, sim
# |
# +-----------------------------------
# +-----------------------------------
# | request TCL package from ACDS 10.0
# |
package require -exact sopc 10.0
# |
# +-----------------------------------
# +-----------------------------------
# | module avs_common_mm
# |
set_module_property DESCRIPTION "MM slave port to conduit with read latency 1"
set_module_property NAME avs_common_mm
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property GROUP Uniboard
set_module_property AUTHOR ASTRON
set_module_property DISPLAY_NAME avs_common_mm
set_module_property TOP_LEVEL_HDL_FILE avs_common_mm.vhd
set_module_property TOP_LEVEL_HDL_MODULE avs_common_mm
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL TRUE
# |
# +-----------------------------------
# +-----------------------------------
# | files
# |
add_file avs_common_mm.vhd {SYNTHESIS SIMULATION}
# |
# +-----------------------------------
# +-----------------------------------
# | parameters
# |
add_parameter g_adr_w NATURAL 5
set_parameter_property g_adr_w DEFAULT_VALUE 5
set_parameter_property g_adr_w DISPLAY_NAME g_adr_w
set_parameter_property g_adr_w TYPE NATURAL
set_parameter_property g_adr_w UNITS None
set_parameter_property g_adr_w AFFECTS_GENERATION false
set_parameter_property g_adr_w HDL_PARAMETER true
add_parameter g_dat_w NATURAL 32
set_parameter_property g_dat_w DEFAULT_VALUE 32
set_parameter_property g_dat_w DISPLAY_NAME g_dat_w
set_parameter_property g_dat_w TYPE NATURAL
set_parameter_property g_dat_w UNITS None
set_parameter_property g_dat_w AFFECTS_GENERATION false
set_parameter_property g_dat_w HDL_PARAMETER true
# |
# +-----------------------------------
# +-----------------------------------
# | display items
# |
# |
# +-----------------------------------
# +-----------------------------------
# | connection point system
# |
add_interface system clock end
set_interface_property system ENABLED true
add_interface_port system csi_system_reset reset Input 1
add_interface_port system csi_system_clk clk Input 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point mem
# |
add_interface mem avalon end
set_interface_property mem addressAlignment DYNAMIC
set_interface_property mem associatedClock system
set_interface_property mem burstOnBurstBoundariesOnly false
set_interface_property mem explicitAddressSpan 0
set_interface_property mem holdTime 0
set_interface_property mem isMemoryDevice false
set_interface_property mem isNonVolatileStorage false
set_interface_property mem linewrapBursts false
set_interface_property mem maximumPendingReadTransactions 0
set_interface_property mem printableDevice false
set_interface_property mem readLatency 1
set_interface_property mem readWaitStates 0
set_interface_property mem readWaitTime 0
set_interface_property mem setupTime 0
set_interface_property mem timingUnits Cycles
set_interface_property mem writeWaitTime 0
set_interface_property mem ASSOCIATED_CLOCK system
set_interface_property mem ENABLED true
add_interface_port mem avs_mem_address address Input g_adr_w
add_interface_port mem avs_mem_write write Input 1
add_interface_port mem avs_mem_writedata writedata Input g_dat_w
add_interface_port mem avs_mem_read read Input 1
add_interface_port mem avs_mem_readdata readdata Output g_dat_w
# |
# +-----------------------------------
# +-----------------------------------
# | connection point reset
# |
add_interface reset conduit end
set_interface_property reset ENABLED true
add_interface_port reset coe_reset_export export Output 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point clk
# |
add_interface clk conduit end
set_interface_property clk ENABLED true
add_interface_port clk coe_clk_export export Output 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point address
# |
add_interface address conduit end
set_interface_property address ENABLED true
add_interface_port address coe_address_export export Output g_adr_w
# |
# +-----------------------------------
# +-----------------------------------
# | connection point write
# |
add_interface write conduit end
set_interface_property write ENABLED true
add_interface_port write coe_write_export export Output 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point writedata
# |
add_interface writedata conduit end
set_interface_property writedata ENABLED true
add_interface_port writedata coe_writedata_export export Output g_dat_w
# |
# +-----------------------------------
# +-----------------------------------
# | connection point read
# |
add_interface read conduit end
set_interface_property read ENABLED true
add_interface_port read coe_read_export export Output 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point readdata
# |
add_interface readdata conduit end
set_interface_property readdata ENABLED true
add_interface_port readdata coe_readdata_export export Input g_dat_w
# |
# +-----------------------------------
libraries/base/common/src/vhdl/avs_common_mm_irq.vhd 0 → 100644
+ 80
− 0
View file @ 9027f957
-------------------------------------------------------------------------------
--
-- Copyright (C) 2011
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose: AVS wrapper to make a MM slave port with IRQ available as conduit
-- Description:
-- Remark:
-- . Same function as avs_common_mm.vhd, but with the IRQ.
-- . The avs_common_mm_irq_hw.tcl determines the read latency, which is 1.
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY avs_common_mm_irq IS
GENERIC (
g_adr_w : NATURAL := 5;
g_dat_w : NATURAL := 32
);
PORT (
-- MM side
csi_system_reset : IN STD_LOGIC;
csi_system_clk : IN STD_LOGIC;
avs_mem_address : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
avs_mem_write : IN STD_LOGIC;
avs_mem_writedata : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
avs_mem_read : IN STD_LOGIC;
avs_mem_readdata : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
ins_interrupt_irq : OUT STD_LOGIC;
-- User side
coe_reset_export : OUT STD_LOGIC;
coe_clk_export : OUT STD_LOGIC;
coe_address_export : OUT STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
coe_write_export : OUT STD_LOGIC;
coe_writedata_export : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
coe_read_export : OUT STD_LOGIC;
coe_readdata_export : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
coe_irq_export : IN STD_LOGIC
);
END avs_common_mm_irq;
ARCHITECTURE wrap OF avs_common_mm_irq IS
BEGIN
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
coe_address_export <= avs_mem_address;
coe_write_export <= avs_mem_write;
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
ins_interrupt_irq <= coe_irq_export; -- can not use coe_interrupt_export as name, because *_interrupt_* is already the MM side name
END wrap;
\ No newline at end of file
libraries/base/common/src/vhdl/avs_common_mm_irq_hw.tcl 0 → 100644
+ 220
− 0
View file @ 9027f957
# TCL File Generated by Component Editor 10.0
# Wed Apr 20 10:33:25 CEST 2011
# DO NOT MODIFY
# +-----------------------------------
# |
# | avs_common_mm_irq "avs_common_mm_irq" v1.0
# | ASTRON 2011.04.20.10:33:25
# | MM slave port to conduit with IRQ and read latency 1
# |
# | D:/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_irq.vhd
# |
# | ./avs_common_mm_irq.vhd syn, sim
# |
# +-----------------------------------
# +-----------------------------------
# | request TCL package from ACDS 10.0
# |
package require -exact sopc 10.0
# |
# +-----------------------------------
# +-----------------------------------
# | module avs_common_mm_irq
# |
set_module_property DESCRIPTION "MM slave port to conduit with IRQ and read latency 1"
set_module_property NAME avs_common_mm_irq
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property GROUP Uniboard
set_module_property AUTHOR ASTRON
set_module_property DISPLAY_NAME avs_common_mm_irq
set_module_property TOP_LEVEL_HDL_FILE avs_common_mm_irq.vhd
set_module_property TOP_LEVEL_HDL_MODULE avs_common_mm_irq
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL TRUE
# |
# +-----------------------------------
# +-----------------------------------
# | files
# |
add_file avs_common_mm_irq.vhd {SYNTHESIS SIMULATION}
# |
# +-----------------------------------
# +-----------------------------------
# | parameters
# |
add_parameter g_adr_w NATURAL 5
set_parameter_property g_adr_w DEFAULT_VALUE 5
set_parameter_property g_adr_w DISPLAY_NAME g_adr_w
set_parameter_property g_adr_w TYPE NATURAL
set_parameter_property g_adr_w UNITS None
set_parameter_property g_adr_w AFFECTS_GENERATION false
set_parameter_property g_adr_w HDL_PARAMETER true
add_parameter g_dat_w NATURAL 32
set_parameter_property g_dat_w DEFAULT_VALUE 32
set_parameter_property g_dat_w DISPLAY_NAME g_dat_w
set_parameter_property g_dat_w TYPE NATURAL
set_parameter_property g_dat_w UNITS None
set_parameter_property g_dat_w AFFECTS_GENERATION false
set_parameter_property g_dat_w HDL_PARAMETER true
# |
# +-----------------------------------
# +-----------------------------------
# | display items
# |
# |
# +-----------------------------------
# +-----------------------------------
# | connection point system
# |
add_interface system clock end
set_interface_property system ENABLED true
add_interface_port system csi_system_reset reset Input 1
add_interface_port system csi_system_clk clk Input 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point mem
# |
add_interface mem avalon end
set_interface_property mem addressAlignment DYNAMIC
set_interface_property mem associatedClock system
set_interface_property mem burstOnBurstBoundariesOnly false
set_interface_property mem explicitAddressSpan 0
set_interface_property mem holdTime 0
set_interface_property mem isMemoryDevice false
set_interface_property mem isNonVolatileStorage false
set_interface_property mem linewrapBursts false
set_interface_property mem maximumPendingReadTransactions 0
set_interface_property mem printableDevice false
set_interface_property mem readLatency 1
set_interface_property mem readWaitStates 0
set_interface_property mem readWaitTime 0
set_interface_property mem setupTime 0
set_interface_property mem timingUnits Cycles
set_interface_property mem writeWaitTime 0
set_interface_property mem ASSOCIATED_CLOCK system
set_interface_property mem ENABLED true
add_interface_port mem avs_mem_address address Input g_adr_w
add_interface_port mem avs_mem_write write Input 1
add_interface_port mem avs_mem_writedata writedata Input g_dat_w
add_interface_port mem avs_mem_read read Input 1
add_interface_port mem avs_mem_readdata readdata Output g_dat_w
# |
# +-----------------------------------
# +-----------------------------------
# | connection point interrupt
# |
add_interface interrupt interrupt end
set_interface_property interrupt associatedAddressablePoint mem
set_interface_property interrupt associatedClock system
set_interface_property interrupt ASSOCIATED_CLOCK system
set_interface_property interrupt ENABLED true
add_interface_port interrupt ins_interrupt_irq irq Output 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point reset
# |
add_interface reset conduit end
set_interface_property reset ENABLED true
add_interface_port reset coe_reset_export export Output 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point clk
# |
add_interface clk conduit end
set_interface_property clk ENABLED true
add_interface_port clk coe_clk_export export Output 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point address
# |
add_interface address conduit end
set_interface_property address ENABLED true
add_interface_port address coe_address_export export Output g_adr_w
# |
# +-----------------------------------
# +-----------------------------------
# | connection point write
# |
add_interface write conduit end
set_interface_property write ENABLED true
add_interface_port write coe_write_export export Output 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point writedata
# |
add_interface writedata conduit end
set_interface_property writedata ENABLED true
add_interface_port writedata coe_writedata_export export Output g_dat_w
# |
# +-----------------------------------
# +-----------------------------------
# | connection point read
# |
add_interface read conduit end
set_interface_property read ENABLED true
add_interface_port read coe_read_export export Output 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point readdata
# |
add_interface readdata conduit end
set_interface_property readdata ENABLED true
add_interface_port readdata coe_readdata_export export Input g_dat_w
# |
# +-----------------------------------
# +-----------------------------------
# | connection point irq
# |
add_interface irq conduit end
set_interface_property irq ENABLED true
add_interface_port irq coe_irq_export export Input 1
# |
# +-----------------------------------
libraries/base/common/src/vhdl/avs_common_mm_readlatency0.vhd 0 → 100644
+ 79
− 0
View file @ 9027f957
-------------------------------------------------------------------------------
--
-- Copyright (C) 2011
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose: Same function as avs_common_mm.vhd, but with the read latency set
-- to 0 instead of 1 in the hardware description TCL file.
-- Description:
-- The avs_common_mm_readlatency0_hw.tcl determines the read latency. This
-- component wraps the default avs_common_mm which has readlatency 1 in its
-- avs_common_mm_hw.tcl.
-- Read latency 0 implies that the MM bus needs to use the waitrequest signal.
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY avs_common_mm_readlatency0 IS
GENERIC (
g_adr_w : NATURAL := 5;
g_dat_w : NATURAL := 32
);
PORT (
-- MM side
csi_system_reset : IN STD_LOGIC;
csi_system_clk : IN STD_LOGIC;
avs_mem_address : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
avs_mem_write : IN STD_LOGIC;
avs_mem_writedata : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
avs_mem_read : IN STD_LOGIC;
avs_mem_readdata : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
avs_mem_waitrequest : OUT STD_LOGIC;
-- User side
coe_reset_export : OUT STD_LOGIC;
coe_clk_export : OUT STD_LOGIC;
coe_address_export : OUT STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
coe_write_export : OUT STD_LOGIC;
coe_writedata_export : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
coe_read_export : OUT STD_LOGIC;
coe_readdata_export : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
coe_waitrequest_export : IN STD_LOGIC := '0'
);
END avs_common_mm_readlatency0;
ARCHITECTURE wrap OF avs_common_mm_readlatency0 IS
BEGIN
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
coe_address_export <= avs_mem_address;
coe_write_export <= avs_mem_write;
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
avs_mem_waitrequest <= coe_waitrequest_export;
END wrap;
\ No newline at end of file
libraries/base/common/src/vhdl/avs_common_mm_readlatency0_hw.tcl 0 → 100644
+ 206
− 0
View file @ 9027f957
# TCL File Generated by Component Editor 10.0
# Wed Apr 20 10:35:12 CEST 2011
# DO NOT MODIFY
# +-----------------------------------
# |
# | avs_common_mm_readlatency0 "avs_common_mm_readlatency0" v1.0
# | ASTRON 2011.04.20.10:35:12
# | MM slave port to conduit with waitrequest, so read latency 0
# |
# | D:/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_readlatency0.vhd
# |
# | ./avs_common_mm_readlatency0.vhd syn, sim
# |
# +-----------------------------------
# +-----------------------------------
# | request TCL package from ACDS 10.0
# |
package require -exact sopc 10.0
# |
# +-----------------------------------
# +-----------------------------------
# | module avs_common_mm_readlatency0
# |
set_module_property DESCRIPTION "MM slave port to conduit with waitrequest, so read latency 0"
set_module_property NAME avs_common_mm_readlatency0
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property GROUP Uniboard
set_module_property AUTHOR ASTRON
set_module_property DISPLAY_NAME avs_common_mm_readlatency0
set_module_property TOP_LEVEL_HDL_FILE avs_common_mm_readlatency0.vhd
set_module_property TOP_LEVEL_HDL_MODULE avs_common_mm_readlatency0
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL TRUE
# |
# +-----------------------------------
# +-----------------------------------
# | files
# |
add_file avs_common_mm_readlatency0.vhd {SYNTHESIS SIMULATION}
# |
# +-----------------------------------
# +-----------------------------------
# | parameters
# |
add_parameter g_adr_w NATURAL 5
set_parameter_property g_adr_w DEFAULT_VALUE 5
set_parameter_property g_adr_w DISPLAY_NAME g_adr_w
set_parameter_property g_adr_w TYPE NATURAL
set_parameter_property g_adr_w UNITS None
set_parameter_property g_adr_w AFFECTS_GENERATION false
set_parameter_property g_adr_w HDL_PARAMETER true
add_parameter g_dat_w NATURAL 32
set_parameter_property g_dat_w DEFAULT_VALUE 32
set_parameter_property g_dat_w DISPLAY_NAME g_dat_w
set_parameter_property g_dat_w TYPE NATURAL
set_parameter_property g_dat_w UNITS None
set_parameter_property g_dat_w AFFECTS_GENERATION false
set_parameter_property g_dat_w HDL_PARAMETER true
# |
# +-----------------------------------
# +-----------------------------------
# | display items
# |
# |
# +-----------------------------------
# +-----------------------------------
# | connection point system
# |
add_interface system clock end
set_interface_property system ENABLED true
add_interface_port system csi_system_reset reset Input 1
add_interface_port system csi_system_clk clk Input 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point mem
# |
add_interface mem avalon end
set_interface_property mem addressAlignment DYNAMIC
set_interface_property mem associatedClock system
set_interface_property mem burstOnBurstBoundariesOnly false
set_interface_property mem explicitAddressSpan 0
set_interface_property mem holdTime 0
set_interface_property mem isMemoryDevice false
set_interface_property mem isNonVolatileStorage false
set_interface_property mem linewrapBursts false
set_interface_property mem maximumPendingReadTransactions 0
set_interface_property mem printableDevice false
set_interface_property mem readLatency 0
set_interface_property mem readWaitTime 1
set_interface_property mem setupTime 0
set_interface_property mem timingUnits Cycles
set_interface_property mem writeWaitTime 0
set_interface_property mem ASSOCIATED_CLOCK system
set_interface_property mem ENABLED true
add_interface_port mem avs_mem_address address Input g_adr_w
add_interface_port mem avs_mem_write write Input 1
add_interface_port mem avs_mem_writedata writedata Input g_dat_w
add_interface_port mem avs_mem_read read Input 1
add_interface_port mem avs_mem_readdata readdata Output g_dat_w
add_interface_port mem avs_mem_waitrequest waitrequest Output 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point reset
# |
add_interface reset conduit end
set_interface_property reset ENABLED true
add_interface_port reset coe_reset_export export Output 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point clk
# |
add_interface clk conduit end
set_interface_property clk ENABLED true
add_interface_port clk coe_clk_export export Output 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point address
# |
add_interface address conduit end
set_interface_property address ENABLED true
add_interface_port address coe_address_export export Output g_adr_w
# |
# +-----------------------------------
# +-----------------------------------
# | connection point write
# |
add_interface write conduit end
set_interface_property write ENABLED true
add_interface_port write coe_write_export export Output 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point writedata
# |
add_interface writedata conduit end
set_interface_property writedata ENABLED true
add_interface_port writedata coe_writedata_export export Output g_dat_w
# |
# +-----------------------------------
# +-----------------------------------
# | connection point read
# |
add_interface read conduit end
set_interface_property read ENABLED true
add_interface_port read coe_read_export export Output 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point readdata
# |
add_interface readdata conduit end
set_interface_property readdata ENABLED true
add_interface_port readdata coe_readdata_export export Input g_dat_w
# |
# +-----------------------------------
# +-----------------------------------
# | connection point waitrequest
# |
add_interface waitrequest conduit end
set_interface_property waitrequest ENABLED true
add_interface_port waitrequest coe_waitrequest_export export Input 1
# |
# +-----------------------------------
libraries/base/common/src/vhdl/avs_common_mm_readlatency2.vhd 0 → 100644
+ 75
− 0
View file @ 9027f957
-------------------------------------------------------------------------------
--
-- Copyright (C) 2011
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose: Same function as avs_common_mm.vhd, but with the read latency set
-- to 2 instead of 1 in the hardware description TCL file.
-- Description:
-- The avs_common_mm_readlatency2_hw.tcl determines the read latency. This
-- component wraps the default avs_common_mm which has readlatency 1 in its
-- avs_common_mm_hw.tcl.
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY avs_common_mm_readlatency2 IS
GENERIC (
g_adr_w : NATURAL := 5;
g_dat_w : NATURAL := 32
);
PORT (
-- MM side
csi_system_reset : IN STD_LOGIC;
csi_system_clk : IN STD_LOGIC;
avs_mem_address : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
avs_mem_write : IN STD_LOGIC;
avs_mem_writedata : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
avs_mem_read : IN STD_LOGIC;
avs_mem_readdata : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
-- User side
coe_reset_export : OUT STD_LOGIC;
coe_clk_export : OUT STD_LOGIC;
coe_address_export : OUT STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
coe_write_export : OUT STD_LOGIC;
coe_writedata_export : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
coe_read_export : OUT STD_LOGIC;
coe_readdata_export : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
);
END avs_common_mm_readlatency2;
ARCHITECTURE wrap OF avs_common_mm_readlatency2 IS
BEGIN
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
coe_address_export <= avs_mem_address;
coe_write_export <= avs_mem_write;
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
END wrap;
\ No newline at end of file
libraries/base/common/src/vhdl/avs_common_mm_readlatency2_hw.tcl 0 → 100644
+ 195
− 0
View file @ 9027f957
# TCL File Generated by Component Editor 10.0
# Wed Apr 20 10:36:07 CEST 2011
# DO NOT MODIFY
# +-----------------------------------
# |
# | avs_common_mm_readlatency2 "avs_common_mm_readlatency2" v1.0
# | ASTRON 2011.04.20.10:36:07
# | MM slave port to conduit with read latency 2
# |
# | D:/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_readlatency2.vhd
# |
# | ./avs_common_mm_readlatency2.vhd syn, sim
# |
# +-----------------------------------
# +-----------------------------------
# | request TCL package from ACDS 10.0
# |
package require -exact sopc 10.0
# |
# +-----------------------------------
# +-----------------------------------
# | module avs_common_mm_readlatency2
# |
set_module_property DESCRIPTION "MM slave port to conduit with read latency 2"
set_module_property NAME avs_common_mm_readlatency2
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property GROUP Uniboard
set_module_property AUTHOR ASTRON
set_module_property DISPLAY_NAME avs_common_mm_readlatency2
set_module_property TOP_LEVEL_HDL_FILE avs_common_mm_readlatency2.vhd
set_module_property TOP_LEVEL_HDL_MODULE avs_common_mm_readlatency2
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL TRUE
# |
# +-----------------------------------
# +-----------------------------------
# | files
# |
add_file avs_common_mm_readlatency2.vhd {SYNTHESIS SIMULATION}
# |
# +-----------------------------------
# +-----------------------------------
# | parameters
# |
add_parameter g_adr_w NATURAL 5
set_parameter_property g_adr_w DEFAULT_VALUE 5
set_parameter_property g_adr_w DISPLAY_NAME g_adr_w
set_parameter_property g_adr_w TYPE NATURAL
set_parameter_property g_adr_w UNITS None
set_parameter_property g_adr_w AFFECTS_GENERATION false
set_parameter_property g_adr_w HDL_PARAMETER true
add_parameter g_dat_w NATURAL 32
set_parameter_property g_dat_w DEFAULT_VALUE 32
set_parameter_property g_dat_w DISPLAY_NAME g_dat_w
set_parameter_property g_dat_w TYPE NATURAL
set_parameter_property g_dat_w UNITS None
set_parameter_property g_dat_w AFFECTS_GENERATION false
set_parameter_property g_dat_w HDL_PARAMETER true
# |
# +-----------------------------------
# +-----------------------------------
# | display items
# |
# |
# +-----------------------------------
# +-----------------------------------
# | connection point system
# |
add_interface system clock end
set_interface_property system ENABLED true
add_interface_port system csi_system_reset reset Input 1
add_interface_port system csi_system_clk clk Input 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point mem
# |
add_interface mem avalon end
set_interface_property mem addressAlignment DYNAMIC
set_interface_property mem associatedClock system
set_interface_property mem burstOnBurstBoundariesOnly false
set_interface_property mem explicitAddressSpan 0
set_interface_property mem holdTime 0
set_interface_property mem isMemoryDevice false
set_interface_property mem isNonVolatileStorage false
set_interface_property mem linewrapBursts false
set_interface_property mem maximumPendingReadTransactions 0
set_interface_property mem printableDevice false
set_interface_property mem readLatency 2
set_interface_property mem readWaitStates 0
set_interface_property mem readWaitTime 0
set_interface_property mem setupTime 0
set_interface_property mem timingUnits Cycles
set_interface_property mem writeWaitTime 0
set_interface_property mem ASSOCIATED_CLOCK system
set_interface_property mem ENABLED true
add_interface_port mem avs_mem_address address Input g_adr_w
add_interface_port mem avs_mem_write write Input 1
add_interface_port mem avs_mem_writedata writedata Input g_dat_w
add_interface_port mem avs_mem_read read Input 1
add_interface_port mem avs_mem_readdata readdata Output g_dat_w
# |
# +-----------------------------------
# +-----------------------------------
# | connection point reset
# |
add_interface reset conduit end
set_interface_property reset ENABLED true
add_interface_port reset coe_reset_export export Output 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point clk
# |
add_interface clk conduit end
set_interface_property clk ENABLED true
add_interface_port clk coe_clk_export export Output 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point address
# |
add_interface address conduit end
set_interface_property address ENABLED true
add_interface_port address coe_address_export export Output g_adr_w
# |
# +-----------------------------------
# +-----------------------------------
# | connection point write
# |
add_interface write conduit end
set_interface_property write ENABLED true
add_interface_port write coe_write_export export Output 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point writedata
# |
add_interface writedata conduit end
set_interface_property writedata ENABLED true
add_interface_port writedata coe_writedata_export export Output g_dat_w
# |
# +-----------------------------------
# +-----------------------------------
# | connection point read
# |
add_interface read conduit end
set_interface_property read ENABLED true
add_interface_port read coe_read_export export Output 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point readdata
# |
add_interface readdata conduit end
set_interface_property readdata ENABLED true
add_interface_port readdata coe_readdata_export export Input g_dat_w
# |
# +-----------------------------------
libraries/base/common/src/vhdl/avs_common_mm_readlatency4.vhd 0 → 100644
+ 75
− 0
View file @ 9027f957
-------------------------------------------------------------------------------
--
-- Copyright (C) 2011
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose: Same function as avs_common_mm.vhd, but with the read latency set
-- to 4 instead of 1 in the hardware description TCL file.
-- Description:
-- The avs_common_mm_readlatency4_hw.tcl determines the read latency. This
-- component wraps the default avs_common_mm which has readlatency 1 in its
-- avs_common_mm_hw.tcl.
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY avs_common_mm_readlatency4 IS
GENERIC (
g_adr_w : NATURAL := 5;
g_dat_w : NATURAL := 32
);
PORT (
-- MM side
csi_system_reset : IN STD_LOGIC;
csi_system_clk : IN STD_LOGIC;
avs_mem_address : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
avs_mem_write : IN STD_LOGIC;
avs_mem_writedata : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
avs_mem_read : IN STD_LOGIC;
avs_mem_readdata : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
-- User side
coe_reset_export : OUT STD_LOGIC;
coe_clk_export : OUT STD_LOGIC;
coe_address_export : OUT STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
coe_write_export : OUT STD_LOGIC;
coe_writedata_export : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
coe_read_export : OUT STD_LOGIC;
coe_readdata_export : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
);
END avs_common_mm_readlatency4;
ARCHITECTURE wrap OF avs_common_mm_readlatency4 IS
BEGIN
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
coe_address_export <= avs_mem_address;
coe_write_export <= avs_mem_write;
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
END wrap;
\ No newline at end of file
libraries/base/common/src/vhdl/avs_common_mm_readlatency4_hw.tcl 0 → 100644
+ 195
− 0
View file @ 9027f957
# TCL File Generated by Component Editor 10.0
# Wed Apr 20 10:36:07 CEST 2011
# DO NOT MODIFY
# +-----------------------------------
# |
# | avs_common_mm_readlatency2 "avs_common_mm_readlatency4" v1.0
# | ASTRON 2011.04.20.10:36:07
# | MM slave port to conduit with read latency 4
# |
# | D:/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_readlatency2.vhd
# |
# | ./avs_common_mm_readlatency4.vhd syn, sim
# |
# +-----------------------------------
# +-----------------------------------
# | request TCL package from ACDS 10.0
# |
package require -exact sopc 10.0
# |
# +-----------------------------------
# +-----------------------------------
# | module avs_common_mm_readlatency4
# |
set_module_property DESCRIPTION "MM slave port to conduit with read latency 4"
set_module_property NAME avs_common_mm_readlatency4
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property GROUP Uniboard
set_module_property AUTHOR ASTRON
set_module_property DISPLAY_NAME avs_common_mm_readlatency4
set_module_property TOP_LEVEL_HDL_FILE avs_common_mm_readlatency4.vhd
set_module_property TOP_LEVEL_HDL_MODULE avs_common_mm_readlatency4
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL TRUE
# |
# +-----------------------------------
# +-----------------------------------
# | files
# |
add_file avs_common_mm_readlatency4.vhd {SYNTHESIS SIMULATION}
# |
# +-----------------------------------
# +-----------------------------------
# | parameters
# |
add_parameter g_adr_w NATURAL 5
set_parameter_property g_adr_w DEFAULT_VALUE 5
set_parameter_property g_adr_w DISPLAY_NAME g_adr_w
set_parameter_property g_adr_w TYPE NATURAL
set_parameter_property g_adr_w UNITS None
set_parameter_property g_adr_w AFFECTS_GENERATION false
set_parameter_property g_adr_w HDL_PARAMETER true
add_parameter g_dat_w NATURAL 32
set_parameter_property g_dat_w DEFAULT_VALUE 32
set_parameter_property g_dat_w DISPLAY_NAME g_dat_w
set_parameter_property g_dat_w TYPE NATURAL
set_parameter_property g_dat_w UNITS None
set_parameter_property g_dat_w AFFECTS_GENERATION false
set_parameter_property g_dat_w HDL_PARAMETER true
# |
# +-----------------------------------
# +-----------------------------------
# | display items
# |
# |
# +-----------------------------------
# +-----------------------------------
# | connection point system
# |
add_interface system clock end
set_interface_property system ENABLED true
add_interface_port system csi_system_reset reset Input 1
add_interface_port system csi_system_clk clk Input 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point mem
# |
add_interface mem avalon end
set_interface_property mem addressAlignment DYNAMIC
set_interface_property mem associatedClock system
set_interface_property mem burstOnBurstBoundariesOnly false
set_interface_property mem explicitAddressSpan 0
set_interface_property mem holdTime 0
set_interface_property mem isMemoryDevice false
set_interface_property mem isNonVolatileStorage false
set_interface_property mem linewrapBursts false
set_interface_property mem maximumPendingReadTransactions 0
set_interface_property mem printableDevice false
set_interface_property mem readLatency 4
set_interface_property mem readWaitStates 0
set_interface_property mem readWaitTime 0
set_interface_property mem setupTime 0
set_interface_property mem timingUnits Cycles
set_interface_property mem writeWaitTime 0
set_interface_property mem ASSOCIATED_CLOCK system
set_interface_property mem ENABLED true
add_interface_port mem avs_mem_address address Input g_adr_w
add_interface_port mem avs_mem_write write Input 1
add_interface_port mem avs_mem_writedata writedata Input g_dat_w
add_interface_port mem avs_mem_read read Input 1
add_interface_port mem avs_mem_readdata readdata Output g_dat_w
# |
# +-----------------------------------
# +-----------------------------------
# | connection point reset
# |
add_interface reset conduit end
set_interface_property reset ENABLED true
add_interface_port reset coe_reset_export export Output 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point clk
# |
add_interface clk conduit end
set_interface_property clk ENABLED true
add_interface_port clk coe_clk_export export Output 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point address
# |
add_interface address conduit end
set_interface_property address ENABLED true
add_interface_port address coe_address_export export Output g_adr_w
# |
# +-----------------------------------
# +-----------------------------------
# | connection point write
# |
add_interface write conduit end
set_interface_property write ENABLED true
add_interface_port write coe_write_export export Output 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point writedata
# |
add_interface writedata conduit end
set_interface_property writedata ENABLED true
add_interface_port writedata coe_writedata_export export Output g_dat_w
# |
# +-----------------------------------
# +-----------------------------------
# | connection point read
# |
add_interface read conduit end
set_interface_property read ENABLED true
add_interface_port read coe_read_export export Output 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point readdata
# |
add_interface readdata conduit end
set_interface_property readdata ENABLED true
add_interface_port readdata coe_readdata_export export Input g_dat_w
# |
# +-----------------------------------
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