Renamed build_sim_dir into build_dir_sim, similar build_dir_synth. Use...

Renamed build_sim_dir into build_dir_sim, similar build_dir_synth. Use <tool_name>_copy_key based on build type 'sim' or 'synth' from hdltool.cfg. Renamed sim_tool_name into tool_name_sim in hdltool.cfg, similar for synth_tool_name.

boards/uniboard1/designs/unb1_minimal/hdllib.cfg

@@ -3,8 +3,8 @@ hdl_library_clause_name = unb1_minimal_lib
 hdl_lib_uses = common mm i2c unb1_board
 hdl_lib_technology = ip_stratixiv
 
-build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = $HDL_BUILD_DIR
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
     $HDL_BUILD_DIR/quartus/unb1_minimal/sopc_unb1_minimal.vhd
@@ -17,7 +17,7 @@ test_bench_files =
 synth_top_level_entity =
 synth_revision = 
 
-synth_copy_files =
+quartus_copy_files =
     quartus/sopc_unb1_minimal.sopc .
 
 quartus_qsf_files =

boards/uniboard1/designs/unb1_test/hdllib.cfg

@@ -3,8 +3,8 @@ hdl_library_clause_name = unb1_test_lib
 hdl_lib_uses = common mm i2c unb1_board remu epcs dp eth tr_xaui tr_10GbE mdio diagnostics
 hdl_lib_technology = ip_stratixiv
 
-build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = $HDL_BUILD_DIR
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
     $HDL_BUILD_DIR/quartus/unb1_test/sopc_unb1_test.vhd
@@ -17,7 +17,7 @@ test_bench_files =
 synth_top_level_entity =
 synth_revision = 
 
-synth_copy_files =
+quartus_copy_files =
     quartus/sopc_unb1_test.sopc .
 
 quartus_qsf_files =

boards/uniboard1/libraries/unb1_board/hdllib.cfg

@@ -3,8 +3,8 @@ hdl_library_clause_name = unb1_board_lib
 hdl_lib_uses = common dp diag uth ppsh i2c tr_nonbonded eth remu
 hdl_lib_technology = ip_stratixiv
 
-build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = $HDL_BUILD_DIR
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/designs/unb_common/../../modules/MegaWizard/pll/clk200_pll.vhd

libraries/base/common/hdllib.cfg

@@ -3,8 +3,8 @@ hdl_library_clause_name = common_lib
 hdl_lib_uses = technology tech_memory tech_fifo tech_iobuf tst
 hdl_lib_technology = 
 
-build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = $HDL_BUILD_DIR
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/modules/common/src/vhdl/common_pkg.vhd

libraries/base/diag/hdllib.cfg

@@ -3,8 +3,8 @@ hdl_library_clause_name = diag_lib
 hdl_lib_uses = dp common
 hdl_lib_technology = 
 
-build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = $HDL_BUILD_DIR
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/modules/Lofar/diag/src/vhdl/diag_bypass.vhd

libraries/base/diagnostics/hdllib.cfg

@@ -3,8 +3,8 @@ hdl_library_clause_name = diagnostics_lib
 hdl_lib_uses = common dp diag
 hdl_lib_technology = 
 
-build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = $HDL_BUILD_DIR
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/modules/diagnostics/src/vhdl/diagnostics.vhd

libraries/base/dp/hdllib.cfg

@@ -3,8 +3,8 @@ hdl_library_clause_name = dp_lib
 hdl_lib_uses = mm common easics
 hdl_lib_technology = 
 
-build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = $HDL_BUILD_DIR
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/modules/dp/src/vhdl/dp_stream_pkg.vhd

libraries/base/mm/hdllib.cfg

@@ -3,8 +3,8 @@ hdl_library_clause_name = mm_lib
 hdl_lib_uses = common
 hdl_lib_technology = 
 
-build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = $HDL_BUILD_DIR
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/modules/mm/src/vhdl/mm_fields.vhd

libraries/base/sens/hdllib.cfg

@@ -3,8 +3,8 @@ hdl_library_clause_name = sens_lib
 hdl_lib_uses = common i2c
 hdl_lib_technology = 
 
-build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = $HDL_BUILD_DIR
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/modules/Lofar/sens/src/vhdl/sens_ctrl.vhd

libraries/base/tst/hdllib.cfg

@@ -3,8 +3,8 @@ hdl_library_clause_name = tst_lib
 hdl_lib_uses = 
 hdl_lib_technology = 
 
-build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = $HDL_BUILD_DIR
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/modules/Lofar/tst/src/vhdl/tst_output.vhd

libraries/base/uth/hdllib.cfg

@@ -3,8 +3,8 @@ hdl_library_clause_name = uth_lib
 hdl_lib_uses = common dp easics
 hdl_lib_technology = 
 
-build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = $HDL_BUILD_DIR
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/modules/uth/src/vhdl/uth_pkg.vhd

libraries/external/easics/hdllib.cfg

@@ -3,8 +3,8 @@ hdl_library_clause_name = easics_lib
 hdl_lib_uses = 
 hdl_lib_technology = 
 
-build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = $HDL_BUILD_DIR
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC64_D8.vhd

libraries/external/numonyx_m25p128/hdllib.cfg

@@ -3,8 +3,8 @@ hdl_library_clause_name = numonyx_m25p128_lib
 hdl_lib_uses = 
 hdl_lib_technology = 
 
-build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = $HDL_BUILD_DIR
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
     

libraries/io/epcs/hdllib.cfg

@@ -3,8 +3,8 @@ hdl_library_clause_name = epcs_lib
 hdl_lib_uses = common dp tech_flash
 hdl_lib_technology = 
 
-build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = $HDL_BUILD_DIR
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/modules/epcs/src/vhdl/epcs_reg.vhd

libraries/io/eth/hdllib.cfg

@@ -3,8 +3,8 @@ hdl_library_clause_name = eth_lib
 hdl_lib_uses = dp common tech_tse
 hdl_lib_technology = 
 
-build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir= $HDL_BUILD_DIR
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
     src/vhdl/eth_pkg.vhd

libraries/io/i2c/hdllib.cfg

@@ -3,8 +3,8 @@ hdl_library_clause_name = i2c_lib
 hdl_lib_uses = common
 hdl_lib_technology = 
 
-build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = $HDL_BUILD_DIR
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/modules/Lofar/i2c/src/vhdl/i2c_pkg.vhd

libraries/io/mdio/hdllib.cfg

@@ -3,8 +3,8 @@ hdl_library_clause_name = mdio_lib
 hdl_lib_uses = common mm
 hdl_lib_technology = 
 
-build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = 
 
 synth_files =
     $UNB/Firmware/modules/Lofar/mdio/src/vhdl/mdio_pkg.vhd

libraries/io/mdio/quartus/mdio_lib.qip

 # synth_files
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_pkg.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_mm.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_ctlr.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_phy_reg.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_phy.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_vitesse_vsc8486_pkg.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/avs_mdio.vhd
+set_global_assignment -name VHDL_FILE /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_pkg.vhd
+set_global_assignment -name VHDL_FILE /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_mm.vhd
+set_global_assignment -name VHDL_FILE /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_ctlr.vhd
+set_global_assignment -name VHDL_FILE /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_phy_reg.vhd
+set_global_assignment -name VHDL_FILE /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_phy.vhd
+set_global_assignment -name VHDL_FILE /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_vitesse_vsc8486_pkg.vhd
+set_global_assignment -name VHDL_FILE /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio.vhd
+set_global_assignment -name VHDL_FILE /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/avs_mdio.vhd

libraries/io/ppsh/hdllib.cfg

@@ -3,8 +3,8 @@ hdl_library_clause_name = ppsh_lib
 hdl_lib_uses = common
 hdl_lib_technology = 
 
-build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = $HDL_BUILD_DIR
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/modules/ppsh/src/vhdl/ppsh.vhd

libraries/io/remu/hdllib.cfg

@@ -3,8 +3,8 @@ hdl_library_clause_name = remu_lib
 hdl_lib_uses = common tech_flash
 hdl_lib_technology = 
 
-build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = $HDL_BUILD_DIR
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/modules/remu/src/vhdl/remu_reg.vhd