Commits · b02115b8dbe48923ef6f4daebce99ab9d95f0afb · RTSD / HDL

"jupyter-notebooks/RECV_notebook.ipynb" did not exist on "7b7a82a25b8bf4d38453d20d7014405fcc7376ec"

Feb 20, 2015
- Added g_sim because memory model should not be included in the synthesis · b02115b8
  Zanting authored 10 years ago
  
  b02115b8
Jan 20, 2015
- Added ip_arria10 DDR4 IP for 4Gbyte, 1600 MTps. · 0c910766
  Eric Kooistra authored 10 years ago
  
  0c910766
Jan 08, 2015
- Added g_sim, when TRUE then use internal DDR memory model in tech_ddr... · e8956d9d
  Eric Kooistra authored 10 years ago
  e8956d9d
- Pass on local_init_done from IP via ctlr_miso.done instead of via separate signal ctlr_init_done. · 37b92e7f
  Eric Kooistra authored 10 years ago
  
  37b92e7f
- Clarified ctlr_init_done. · c576df23
  Eric Kooistra authored 10 years ago
  
  c576df23
- Define t_mem_ctlr_mosi/miso in common_mem_pkg, to use that instead of the... · b559785d
  Eric Kooistra authored 10 years ago
  b559785d
Jan 05, 2015
- Rename ctrl into ctlr. · d61c490e
  Eric Kooistra authored 10 years ago
  
  d61c490e
Dec 19, 2014
- Use ddr that supports both ddr3 or ddr4 at this level. · f46f0d8b
  Eric Kooistra authored 10 years ago
  
  f46f0d8b
Dec 18, 2014
- Moved ddr3/ VHDL files to ddr/. · 6d479748
  Eric Kooistra authored 10 years ago
  
  6d479748
- Rename g_ddr into g_tech_ddr · bb69952f
  Eric Kooistra authored 10 years ago
  
  bb69952f
- Gather all DDR parameters in one t_c_tech_ddr record · 3c8fc0e5
  Eric Kooistra authored 10 years ago
  
  3c8fc0e5
Dec 17, 2014
- Added DDR3 IP technology wrapper for straticiv using UniPhy. · 880633c0
  Eric Kooistra authored 10 years ago
  
  880633c0