When diag_en='1' then the the tx_seq data overrules the usr_sosi_arr. Dependent on g_use_usr_input the overrule now differs.

-Also set BG gap size to 256-176.

Connected the eth1_tse_clk

-removed comments 

Added draft src/vhdl/mms_io_ddr_diag.vhd, it intstantiates the BG, DB and IO_DDR as is and it compiles.

-Defaulted BG en_sync to '1' in sim.

Section 8.10.4:
* Described 10 G Tx‐only interface between UniBoard and GPU for SC3.
* It may appear possible to have SC3 commensal with Apertif X, but it is not possible to say until more actual implementation resource usage figures are available.
* Described option of having 16 extra UniBoards (or 4 extra UniBoard2) dedicated for Arts.
* Added conclusion that all four SC of Arts will use the Uniboards to connect to the Apertif BF.

-Reduced BG output block size to 2*64.

-Also committed generated hex files.