-Fixed off-by-one in BSN output assignment (imaginary part).

applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd

@@ -131,7 +131,7 @@ END apertif_unb1_correlator;
 ARCHITECTURE str OF apertif_unb1_correlator IS
 
   -- Firmware version x.y
-  CONSTANT c_fw_version             : t_unb1_board_fw_version := (0, 2);
+  CONSTANT c_fw_version             : t_unb1_board_fw_version := (0, 3);
   -- Enable block generators
   CONSTANT c_use_phy                : t_c_unb1_board_use_phy  := (1, sel_a_b(g_use_bg, 0, 1), 0, 0, 0, 0, 0, 1);
   
@@ -574,7 +574,7 @@ BEGIN
         FOR j IN 0 TO c_nof_bf_modules-1 LOOP
           interleaved_arr(i*c_nof_bf_modules + j)      <= dp_bsn_align_src_out_arr(i); -- SOSI ctrl
           interleaved_arr(i*c_nof_bf_modules + j).data <= (OTHERS=>'0');
-          interleaved_arr(i*c_nof_bf_modules + j).im   <= RESIZE_DP_DSP_DATA(dp_bsn_align_src_out_arr(i).data( (c_nof_complex*j+1)*c_compl_dat_w+c_compl_dat_w DOWNTO c_nof_complex*j*c_compl_dat_w+c_compl_dat_w));
+          interleaved_arr(i*c_nof_bf_modules + j).im   <= RESIZE_DP_DSP_DATA(dp_bsn_align_src_out_arr(i).data( (c_nof_complex*j+1)*c_compl_dat_w+c_compl_dat_w-1 DOWNTO c_nof_complex*j*c_compl_dat_w+c_compl_dat_w));
           interleaved_arr(i*c_nof_bf_modules + j).re   <= RESIZE_DP_DSP_DATA(dp_bsn_align_src_out_arr(i).data( (c_nof_complex*j+1)*c_compl_dat_w-1               DOWNTO c_nof_complex*j*c_compl_dat_w));
         END LOOP;
       END LOOP;