Skip to content
Snippets Groups Projects
Commit e04d0952 authored by Pieter Donker's avatar Pieter Donker
Browse files

add altera_libraries

parent 81cffcb7
No related branches found
No related tags found
No related merge requests found
Showing
with 662 additions and 0 deletions
#------------------------------------------------------------------------------
#
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on generated file mentor/msim_setup.tcl.
# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vmap alt_em10g32_170 ./work/
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/alt_em10g32.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/alt_em10g32unit.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_clk_rst.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_clock_crosser.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_crc32.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_crc32_gf_mult32_kc.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_creg_map.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_creg_top.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_frm_decoder.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_rs_gmii_mii_layer.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_pipeline_base.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_reset_synchronizer.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rr_clock_crosser.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rst_cnt.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_fctl_filter_crcpad_rem.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_fctl_overflow.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_fctl_preamble.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_frm_control.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_pfc_flow_control.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_pfc_pause_conversion.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_pkt_backpressure_control.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_rs_gmii16b.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_rs_gmii16b_top.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_rs_gmii_mii.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_rs_layer.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_rs_xgmii.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_status_aligner.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_top.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_stat_mem.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_stat_reg.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_data_frm_gen.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_srcaddr_inserter.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_err_aligner.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_flow_control.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_frm_arbiter.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_frm_muxer.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_pause_beat_conversion.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_pause_frm_gen.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_pause_req.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_pfc_frm_gen.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rr_buffer.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_rs_gmii16b.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_rs_gmii16b_top.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_rs_layer.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_rs_xgmii_layer.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_sc_fifo.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_top.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_gmii_decoder.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_gmii_decoder_dfa.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii_encoder.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii_encoder_dfa.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_gmii_mii_decoder_if.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii_mii_encoder_if.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_mm_adapter/altera_eth_avalon_mm_adapter.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_avalon_st_adapter.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_rx.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_tx.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/alt_em10g32_vldpkt_rddly.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter_rx.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter_tx.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_sideband_crosser.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_sideband_crosser_sync.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_64_xgmii_conversion.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_to_64_xgmii_conversion.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_64_to_32_xgmii_conversion.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_dcfifo_32_to_64_xgmii_conversion.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_dcfifo_64_to_32_xgmii_conversion.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_32_to_64_adapter.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_64_to_32_adapter.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_data_format_adapter.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_altsyncram_bundle.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_altsyncram.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_lat_calc.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_hecc.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_secc.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo_hecc.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo_secc.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_ecc_dec_18_12.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_ecc_dec_39_32.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_ecc_enc_12_18.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_ecc_enc_32_39.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_rs_xgmii_layer_ultra.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_rs_xgmii_ultra.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avst_to_gmii_if.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_gmii_to_avst_if.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_gmii_tsu.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_gmii16b_tsu.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_lpm_mult.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_ptp_aligner.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_ptp_detector.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_ptp_top.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii_crc_inserter.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii16b_crc_inserter.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii_ptp_inserter.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii16b_ptp_inserter.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii16b_ptp_inserter_1g2p5g10g.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_ptp_processor.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_ptp_top.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_xgmii_crc_inserter.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_xgmii_ptp_inserter.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_xgmii_tsu.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_crc328generator.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_crc32ctl8.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_crc32galois8.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_gmii_crc_inserter.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_gmii16b_crc_inserter.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_gmii16b_crc32.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/alt_em10g32_avalon_dc_fifo.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/alt_em10g32_dcfifo_synchronizer_bundle.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/alt_em10g32_std_synchronizer.v" -work alt_em10g32_170
vlog "$IP_DIR/../alt_em10g32_170/sim/altera_std_synchronizer_nocut.v" -work alt_em10g32_170
hdl_lib_name = ip_arria10_e1sg_alt_em10g32_170
hdl_library_clause_name = alt_em10g32_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
#$HDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
[modelsim_project_file]
modelsim_compile_ip_files =
$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl
#------------------------------------------------------------------------------
#
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on generated file mentor/msim_setup.tcl.
# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
#
set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vmap alt_mem_if_jtag_master_170 ./work/
vcom "$IP_DIR/../alt_mem_if_jtag_master_170/sim/ip_arria10_e1sg_ddr4_8g_1600_alt_mem_if_jtag_master_170_biwt3uq.vhd" -work alt_mem_if_jtag_master_170
hdl_lib_name = ip_arria10_e1sg_alt_mem_if_jtag_master_170
hdl_library_clause_name = alt_mem_if_jtag_master_170
hdl_lib_uses_synth =
hdl_lib_uses_sim = ip_arria10_e1sg_altera_jtag_dc_streaming_170 ip_arria10_e1sg_timing_adapter_170 ip_arria10_e1sg_altera_avalon_sc_fifo_170 ip_arria10_e1sg_altera_avalon_st_bytes_to_packets_170 ip_arria10_e1sg_altera_avalon_st_packets_to_bytes_170 ip_arria10_e1sg_altera_avalon_packets_to_master_170 ip_arria10_e1sg_channel_adapter_170 ip_arria10_e1sg_altera_reset_controller_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl
#------------------------------------------------------------------------------
#
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on generated file mentor/msim_setup.tcl.
# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vmap altclkctrl_170 ./work/
vcom "$IP_DIR/../altclkctrl_170/sim/ip_arria10_e1sg_clkbuf_global_altclkctrl_170_7fwzyby.vhd" -work altclkctrl_170
hdl_lib_name = ip_arria10_e1sg_altclkctrl_170
hdl_library_clause_name = altclkctrl_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
synth_files =
test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl
#------------------------------------------------------------------------------
#
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on generated file mentor/msim_setup.tcl.
# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vmap altera_asmi_parallel_170 ./work/
vcom "$IP_DIR/../altera_asmi_parallel_170/sim/ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_170_eou4tfa.vhd" -work altera_asmi_parallel_170
hdl_lib_name = ip_arria10_e1sg_altera_asmi_parallel_170
hdl_library_clause_name = altera_asmi_parallel_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
synth_files =
test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl
#------------------------------------------------------------------------------
#
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on generated file mentor/msim_setup.tcl.
# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vmap altera_avalon_mm_bridge_170 ./work/
vlog "$IP_DIR/../altera_avalon_mm_bridge_170/sim/altera_avalon_mm_bridge.v" -work altera_avalon_mm_bridge_170
hdl_lib_name = ip_arria10_e1sg_altera_avalon_mm_bridge_170
hdl_library_clause_name = altera_avalon_mm_bridge_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
#$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
[modelsim_project_file]
modelsim_compile_ip_files =
$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl
#------------------------------------------------------------------------------
#
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on generated file mentor/msim_setup.tcl.
# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
#
vmap altera_avalon_onchip_memory2_170 ./work/
set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
hdl_lib_name = ip_arria10_e1sg_altera_avalon_onchip_memory2_170
hdl_library_clause_name = altera_avalon_onchip_memory2_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
synth_files =
test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl
#------------------------------------------------------------------------------
#
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on generated file mentor/msim_setup.tcl.
# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
#
set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vmap altera_avalon_packets_to_master_170 ./work/
vlog "$IP_DIR/../altera_avalon_packets_to_master_170/sim/altera_avalon_packets_to_master.v" -work altera_avalon_packets_to_master_170
hdl_lib_name = ip_arria10_e1sg_altera_avalon_packets_to_master_170
hdl_library_clause_name = altera_avalon_packets_to_master_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
synth_files =
test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl
#------------------------------------------------------------------------------
#
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on generated file mentor/msim_setup.tcl.
# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
#
set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vmap altera_avalon_sc_fifo_170 ./work/
vlog "$IP_DIR/../altera_avalon_sc_fifo_170/sim/altera_avalon_sc_fifo.v" -work altera_avalon_sc_fifo_170
hdl_lib_name = ip_arria10_e1sg_altera_avalon_sc_fifo_170
hdl_library_clause_name = altera_avalon_sc_fifo_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
synth_files =
test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl
#------------------------------------------------------------------------------
#
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on generated file mentor/msim_setup.tcl.
# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
#
set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vmap altera_avalon_st_bytes_to_packets_170 ./work/
vlog "$IP_DIR/../altera_avalon_st_bytes_to_packets_170/sim/altera_avalon_st_bytes_to_packets.v" -work altera_avalon_st_bytes_to_packets_170
hdl_lib_name = ip_arria10_e1sg_altera_avalon_st_bytes_to_packets_170
hdl_library_clause_name = altera_avalon_st_bytes_to_packets_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
synth_files =
test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl
#------------------------------------------------------------------------------
#
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on generated file mentor/msim_setup.tcl.
# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
#
set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vmap altera_avalon_st_packets_to_bytes_170 ./work/
vlog "$IP_DIR/../altera_avalon_st_packets_to_bytes_170/sim/altera_avalon_st_packets_to_bytes.v" -work altera_avalon_st_packets_to_bytes_170
hdl_lib_name = ip_arria10_e1sg_altera_avalon_st_packets_to_bytes_170
hdl_library_clause_name = altera_avalon_st_packets_to_bytes_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
synth_files =
test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment