From e04d0952f6f126d29d091553e05a450bf2a0f856 Mon Sep 17 00:00:00 2001 From: donker <donker@astron.nl> Date: Wed, 9 Oct 2019 09:40:33 +0200 Subject: [PATCH] add altera_libraries --- .../alt_em10g32_170/compile_ip.tcl | 149 ++++++++++++++++ .../alt_em10g32_170/hdllib.cfg | 20 +++ .../alt_mem_if_jtag_master_170/compile_ip.tcl | 38 ++++ .../alt_mem_if_jtag_master_170/hdllib.cfg | 17 ++ .../altclkctrl_170/compile_ip.tcl | 35 ++++ .../altclkctrl_170/hdllib.cfg | 17 ++ .../altera_asmi_parallel_170/compile_ip.tcl | 37 ++++ .../altera_asmi_parallel_170/hdllib.cfg | 15 ++ .../compile_ip.tcl | 35 ++++ .../altera_avalon_mm_bridge_170/hdllib.cfg | 20 +++ .../compile_ip.tcl | 46 +++++ .../hdllib.cfg | 16 ++ .../compile_ip.tcl | 37 ++++ .../hdllib.cfg | 16 ++ .../altera_avalon_sc_fifo_170/compile_ip.tcl | 40 +++++ .../altera_avalon_sc_fifo_170/hdllib.cfg | 16 ++ .../compile_ip.tcl | 37 ++++ .../hdllib.cfg | 16 ++ .../compile_ip.tcl | 39 +++++ .../hdllib.cfg | 16 ++ .../altera_emif_170/compile_ip.tcl | 162 ++++++++++++++++++ .../altera_emif_170/hdllib.cfg | 16 ++ .../altera_emif_arch_nf_170/compile_ip.tcl | 98 +++++++++++ .../altera_emif_arch_nf_170/hdllib.cfg | 20 +++ .../compile_ip.tcl | 47 +++++ .../altera_emif_cal_slave_nf_170/hdllib.cfg | 16 ++ .../altera_eth_tse_170/compile_ip.tcl | 40 +++++ .../altera_eth_tse_170/hdllib.cfg | 27 +++ .../compile_ip.tcl | 33 ++++ .../hdllib.cfg | 17 ++ .../altera_eth_tse_mac_170/compile_ip.tcl | 148 ++++++++++++++++ .../altera_eth_tse_mac_170/hdllib.cfg | 16 ++ .../compile_ip.tcl | 40 +++++ .../hdllib.cfg | 17 ++ .../compile_ip.tcl | 35 ++++ .../hdllib.cfg | 17 ++ .../compile_ip.tcl | 114 ++++++++++++ .../hdllib.cfg | 17 ++ .../compile_ip.tcl | 116 +++++++++++++ .../hdllib.cfg | 17 ++ .../altera_iopll_170/compile_ip.tcl | 41 +++++ .../altera_iopll_170/hdllib.cfg | 17 ++ .../altera_ip_col_if_170/compile_ip.tcl | 37 ++++ .../altera_ip_col_if_170/hdllib.cfg | 16 ++ .../compile_ip.tcl | 45 +++++ .../altera_jtag_dc_streaming_170/hdllib.cfg | 16 ++ .../altera_lvds_170/compile_ip.tcl | 34 ++++ .../altera_lvds_170/hdllib.cfg | 17 ++ .../altera_lvds_core20_170/compile_ip.tcl | 39 +++++ .../altera_lvds_core20_170/hdllib.cfg | 17 ++ .../compile_ip.tcl | 36 ++++ .../hdllib.cfg | 16 ++ .../compile_ip.tcl | 36 ++++ .../hdllib.cfg | 16 ++ .../altera_mm_interconnect_170/compile_ip.tcl | 46 +++++ .../altera_mm_interconnect_170/hdllib.cfg | 16 ++ .../altera_remote_update_170/compile_ip.tcl | 37 ++++ .../altera_remote_update_170/hdllib.cfg | 15 ++ .../compile_ip.tcl | 40 +++++ .../altera_remote_update_core_170/hdllib.cfg | 12 ++ .../compile_ip.tcl | 37 ++++ .../altera_reset_controller_170/hdllib.cfg | 16 ++ .../compile_ip.tcl | 55 ++++++ .../altera_xcvr_atx_pll_a10_170/hdllib.cfg | 17 ++ .../altera_xcvr_fpll_a10_170/compile_ip.tcl | 50 ++++++ .../altera_xcvr_fpll_a10_170/hdllib.cfg | 17 ++ .../altera_xcvr_native_a10_170/compile_ip.tcl | 98 +++++++++++ .../altera_xcvr_native_a10_170/hdllib.cfg | 16 ++ .../compile_ip.tcl | 44 +++++ .../altera_xcvr_reset_control_170/hdllib.cfg | 16 ++ .../channel_adapter_170/compile_ip.tcl | 40 +++++ .../channel_adapter_170/hdllib.cfg | 16 ++ .../timing_adapter_170/compile_ip.tcl | 39 +++++ .../timing_adapter_170/hdllib.cfg | 16 ++ 74 files changed, 2701 insertions(+) create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/hdllib.cfg create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl create mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/hdllib.cfg diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl new file mode 100644 index 0000000000..ed9f1e35b6 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl @@ -0,0 +1,149 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap alt_em10g32_170 ./work/ + + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/alt_em10g32.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/alt_em10g32unit.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_clk_rst.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_clock_crosser.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_crc32.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_crc32_gf_mult32_kc.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_creg_map.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_creg_top.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_frm_decoder.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_rs_gmii_mii_layer.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_pipeline_base.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_reset_synchronizer.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rr_clock_crosser.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rst_cnt.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_fctl_filter_crcpad_rem.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_fctl_overflow.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_fctl_preamble.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_frm_control.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_pfc_flow_control.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_pfc_pause_conversion.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_pkt_backpressure_control.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_rs_gmii16b.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_rs_gmii16b_top.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_rs_gmii_mii.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_rs_layer.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_rs_xgmii.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_status_aligner.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_top.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_stat_mem.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_stat_reg.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_data_frm_gen.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_srcaddr_inserter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_err_aligner.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_flow_control.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_frm_arbiter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_frm_muxer.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_pause_beat_conversion.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_pause_frm_gen.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_pause_req.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_pfc_frm_gen.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rr_buffer.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_rs_gmii16b.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_rs_gmii16b_top.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_rs_layer.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_rs_xgmii_layer.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_sc_fifo.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_top.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_gmii_decoder.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_gmii_decoder_dfa.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii_encoder.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii_encoder_dfa.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_gmii_mii_decoder_if.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii_mii_encoder_if.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_mm_adapter/altera_eth_avalon_mm_adapter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_avalon_st_adapter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_rx.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_tx.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/alt_em10g32_vldpkt_rddly.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter_rx.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter_tx.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_sideband_crosser.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_sideband_crosser_sync.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_64_xgmii_conversion.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_to_64_xgmii_conversion.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_64_to_32_xgmii_conversion.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_dcfifo_32_to_64_xgmii_conversion.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_dcfifo_64_to_32_xgmii_conversion.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_32_to_64_adapter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_64_to_32_adapter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_data_format_adapter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_altsyncram_bundle.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_altsyncram.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_lat_calc.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_hecc.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_secc.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo_hecc.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo_secc.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_ecc_dec_18_12.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_ecc_dec_39_32.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_ecc_enc_12_18.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_ecc_enc_32_39.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_rs_xgmii_layer_ultra.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_rs_xgmii_ultra.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avst_to_gmii_if.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_gmii_to_avst_if.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_gmii_tsu.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_gmii16b_tsu.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_lpm_mult.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_ptp_aligner.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_ptp_detector.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_ptp_top.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii_crc_inserter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii16b_crc_inserter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii_ptp_inserter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii16b_ptp_inserter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii16b_ptp_inserter_1g2p5g10g.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_ptp_processor.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_ptp_top.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_xgmii_crc_inserter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_xgmii_ptp_inserter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_xgmii_tsu.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_crc328generator.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_crc32ctl8.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_crc32galois8.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_gmii_crc_inserter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_gmii16b_crc_inserter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_gmii16b_crc32.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/alt_em10g32_avalon_dc_fifo.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/alt_em10g32_dcfifo_synchronizer_bundle.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/alt_em10g32_std_synchronizer.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/altera_std_synchronizer_nocut.v" -work alt_em10g32_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/hdllib.cfg new file mode 100644 index 0000000000..fecc7601f5 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/hdllib.cfg @@ -0,0 +1,20 @@ +hdl_lib_name = ip_arria10_e1sg_alt_em10g32_170 +hdl_library_clause_name = alt_em10g32_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + # The generated testbench is listed here to create a simulation configuration for it. However + # the tb is commented because it is not useful, see generate_ip.sh. + #$HDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl new file mode 100644 index 0000000000..d35f46a0c1 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl @@ -0,0 +1,38 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap alt_mem_if_jtag_master_170 ./work/ + + vcom "$IP_DIR/../alt_mem_if_jtag_master_170/sim/ip_arria10_e1sg_ddr4_8g_1600_alt_mem_if_jtag_master_170_biwt3uq.vhd" -work alt_mem_if_jtag_master_170 + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/hdllib.cfg new file mode 100644 index 0000000000..189c63a2b6 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_alt_mem_if_jtag_master_170 +hdl_library_clause_name = alt_mem_if_jtag_master_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = ip_arria10_e1sg_altera_jtag_dc_streaming_170 ip_arria10_e1sg_timing_adapter_170 ip_arria10_e1sg_altera_avalon_sc_fifo_170 ip_arria10_e1sg_altera_avalon_st_bytes_to_packets_170 ip_arria10_e1sg_altera_avalon_st_packets_to_bytes_170 ip_arria10_e1sg_altera_avalon_packets_to_master_170 ip_arria10_e1sg_channel_adapter_170 ip_arria10_e1sg_altera_reset_controller_170 + +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl new file mode 100644 index 0000000000..e1cdadbeab --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl @@ -0,0 +1,35 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altclkctrl_170 ./work/ + vcom "$IP_DIR/../altclkctrl_170/sim/ip_arria10_e1sg_clkbuf_global_altclkctrl_170_7fwzyby.vhd" -work altclkctrl_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/hdllib.cfg new file mode 100644 index 0000000000..150dab1214 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altclkctrl_170 +hdl_library_clause_name = altclkctrl_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl new file mode 100644 index 0000000000..f344ad332c --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl @@ -0,0 +1,37 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +vlib ./work/ ;# Assume library work already exist + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_asmi_parallel_170 ./work/ + + + vcom "$IP_DIR/../altera_asmi_parallel_170/sim/ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_170_eou4tfa.vhd" -work altera_asmi_parallel_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/hdllib.cfg new file mode 100644 index 0000000000..0e8e55c1e6 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/hdllib.cfg @@ -0,0 +1,15 @@ +hdl_lib_name = ip_arria10_e1sg_altera_asmi_parallel_170 +hdl_library_clause_name = altera_asmi_parallel_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl new file mode 100644 index 0000000000..19c655935f --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl @@ -0,0 +1,35 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_avalon_mm_bridge_170 ./work/ + + vlog "$IP_DIR/../altera_avalon_mm_bridge_170/sim/altera_avalon_mm_bridge.v" -work altera_avalon_mm_bridge_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/hdllib.cfg new file mode 100644 index 0000000000..1f0e8108fd --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/hdllib.cfg @@ -0,0 +1,20 @@ +hdl_lib_name = ip_arria10_e1sg_altera_avalon_mm_bridge_170 +hdl_library_clause_name = altera_avalon_mm_bridge_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + # The generated testbench is listed here to create a simulation configuration for it. However + # the tb is commented because it is not useful, see generate_ip.sh. + #$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl new file mode 100644 index 0000000000..3da14b9e74 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl @@ -0,0 +1,46 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# +vmap altera_avalon_onchip_memory2_170 ./work/ + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170 + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/hdllib.cfg new file mode 100644 index 0000000000..2edea37fa9 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_avalon_onchip_memory2_170 +hdl_library_clause_name = altera_avalon_onchip_memory2_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl new file mode 100644 index 0000000000..2936776afa --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl @@ -0,0 +1,37 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_avalon_packets_to_master_170 ./work/ + + vlog "$IP_DIR/../altera_avalon_packets_to_master_170/sim/altera_avalon_packets_to_master.v" -work altera_avalon_packets_to_master_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/hdllib.cfg new file mode 100644 index 0000000000..0dc7501636 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_avalon_packets_to_master_170 +hdl_library_clause_name = altera_avalon_packets_to_master_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl new file mode 100644 index 0000000000..54dd8ac6a6 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl @@ -0,0 +1,40 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_avalon_sc_fifo_170 ./work/ + vlog "$IP_DIR/../altera_avalon_sc_fifo_170/sim/altera_avalon_sc_fifo.v" -work altera_avalon_sc_fifo_170 + + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/hdllib.cfg new file mode 100644 index 0000000000..f8ab200bc0 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_avalon_sc_fifo_170 +hdl_library_clause_name = altera_avalon_sc_fifo_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl new file mode 100644 index 0000000000..07d698207f --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl @@ -0,0 +1,37 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_avalon_st_bytes_to_packets_170 ./work/ + + vlog "$IP_DIR/../altera_avalon_st_bytes_to_packets_170/sim/altera_avalon_st_bytes_to_packets.v" -work altera_avalon_st_bytes_to_packets_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/hdllib.cfg new file mode 100644 index 0000000000..0662c5a3d2 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_avalon_st_bytes_to_packets_170 +hdl_library_clause_name = altera_avalon_st_bytes_to_packets_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl new file mode 100644 index 0000000000..89f59ac908 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl @@ -0,0 +1,39 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" +vmap altera_avalon_st_packets_to_bytes_170 ./work/ + + vlog "$IP_DIR/../altera_avalon_st_packets_to_bytes_170/sim/altera_avalon_st_packets_to_bytes.v" -work altera_avalon_st_packets_to_bytes_170 + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/hdllib.cfg new file mode 100644 index 0000000000..f8cf50573a --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_avalon_st_packets_to_bytes_170 +hdl_library_clause_name = altera_avalon_st_packets_to_bytes_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl new file mode 100644 index 0000000000..169d99bda6 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl @@ -0,0 +1,162 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# +vmap altera_emif_170 ./work/ +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_emif_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_170_verwnda.v" -work altera_emif_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_emif_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_170_2hmjbxa.v" -work altera_emif_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_emif_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_170_7ixm4xa.v" -work altera_emif_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_emif_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_170_xxodvzi.v" -work altera_emif_170 + +vmap altera_emif_arch_nf_170 ./work/ +# ddr4_4g_1600 +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti_top.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti_io_aux.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti.sv" -work altera_emif_arch_nf_170 + +# ddr4_4g_2000 +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq_top.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq_io_aux.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq.sv" -work altera_emif_arch_nf_170 + +# ddr4_8g_1600 +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei_top.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei_io_aux.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei.sv" -work altera_emif_arch_nf_170 + +# ddr4_8g_2400 +set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim" + + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_170_as3yf3i_top.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_170_as3yf3i_io_aux.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_170_as3yf3i.sv" -work altera_emif_arch_nf_170 + +# common dependencies + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_bufs.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_se_i.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_se_o.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_df_i.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_df_o.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_cp_i.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_bdir_df.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_bdir_se.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_unused.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_cal_counter.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll_fast_sim.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll_extra_clks.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_oct.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_core_clks_rsts.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hps_clks_rsts.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles_wrap.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles_abphy.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_abphy_mux.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_avl_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_sideband_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_mmr_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_amm_data_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_ast_data_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_afi_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_seq_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_regs.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_oct.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_oct_um_fsm.sv" -work altera_emif_arch_nf_170 + vlog "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_std_synchronizer_nocut.v" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/mem_array_abphy.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_abphy.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_encrypted_abphy.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_nf5es_encrypted_abphy.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/io_12_lane_bcm__nf5es_abphy.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/io_12_lane__nf5es_abphy.sv" -work altera_emif_arch_nf_170 + +vmap altera_emif_cal_slave_nf_170 ./work/ +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170 + +vmap altera_reset_controller_170 ./work/ +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_170 + vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_170 + +vmap altera_mm_interconnect_170 ./work/ +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_3gbam2q.vhd" -work altera_mm_interconnect_170 + vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170 + vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_lcqbbfq.vhd" -work altera_mm_interconnect_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170 + +vmap altera_avalon_onchip_memory2_170 ./work/ +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170 + + +vmap altera_avalon_mm_bridge_170 ./work/ +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + + vlog "$IP_DIR/../altera_avalon_mm_bridge_170/sim/altera_avalon_mm_bridge.v" -work altera_avalon_mm_bridge_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/hdllib.cfg new file mode 100644 index 0000000000..7e1017d4fd --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_emif_170 +hdl_library_clause_name = altera_emif_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = ip_arria10_e1sg_altera_merlin_master_translator_170 ip_arria10_e1sg_altera_merlin_slave_translator_170 +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl new file mode 100644 index 0000000000..b4f18e92ca --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl @@ -0,0 +1,98 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +vmap altera_emif_arch_nf_170 ./work/ + +# ddr4_4g_1600 +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti_top.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti_io_aux.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti.sv" -work altera_emif_arch_nf_170 + +# ddr4_4g_2000 +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq_top.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq_io_aux.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq.sv" -work altera_emif_arch_nf_170 + +# ddr4_8g_1600 +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei_top.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei_io_aux.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei.sv" -work altera_emif_arch_nf_170 + +# ddr4_8g_2400 +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_170_as3yf3i_top.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_170_as3yf3i_io_aux.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_170_as3yf3i.sv" -work altera_emif_arch_nf_170 + +# common dependencies + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_bufs.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_se_i.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_se_o.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_df_i.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_df_o.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_cp_i.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_bdir_df.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_bdir_se.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_unused.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_cal_counter.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll_fast_sim.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll_extra_clks.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_oct.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_core_clks_rsts.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hps_clks_rsts.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles_wrap.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles_abphy.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_abphy_mux.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_avl_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_sideband_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_mmr_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_amm_data_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_ast_data_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_afi_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_seq_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_regs.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_oct.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_oct_um_fsm.sv" -work altera_emif_arch_nf_170 + vlog "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_std_synchronizer_nocut.v" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/mem_array_abphy.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_abphy.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_encrypted_abphy.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_nf5es_encrypted_abphy.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/io_12_lane_bcm__nf5es_abphy.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/io_12_lane__nf5es_abphy.sv" -work altera_emif_arch_nf_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/hdllib.cfg new file mode 100644 index 0000000000..aa1549a765 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/hdllib.cfg @@ -0,0 +1,20 @@ +hdl_lib_name = ip_arria10_e1sg_altera_emif_arch_nf_170 +hdl_library_clause_name = altera_emif_arch_nf_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + # The generated testbench is listed here to create a simulation configuration for it. However + # the tb is commented because it is not useful, see generate_ip.sh. + #$HDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl new file mode 100644 index 0000000000..656287d795 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl @@ -0,0 +1,47 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# + +vmap altera_emif_cal_slave_nf_170 ./work/ + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170 + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/hdllib.cfg new file mode 100644 index 0000000000..c56bf53d57 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_emif_cal_slave_nf_170 +hdl_library_clause_name = altera_emif_cal_slave_nf_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl new file mode 100644 index 0000000000..1b531d9615 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl @@ -0,0 +1,40 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +vmap altera_eth_tse_170 ./work/ + +# tse_sgmii_gx +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" +vcom "$IP_DIR/../altera_eth_tse_170/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_170_bs6nd6i.vhd" -work altera_eth_tse_170 + +# tse_sgmii_lvds +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" +vcom "$IP_DIR/../altera_eth_tse_170/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_170_kv2t7sq.vhd" -work altera_eth_tse_170 + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/hdllib.cfg new file mode 100644 index 0000000000..a21ef74c59 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/hdllib.cfg @@ -0,0 +1,27 @@ +hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_170 +hdl_library_clause_name = altera_eth_tse_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +ip_arria10_e1sg_altera_eth_tse_mac_170 +ip_arria10_e1sg_altera_eth_tse_avalon_arbiter_170 +ip_arria10_e1sg_altera_eth_tse_pcs_pma_nf_phyip_170 +ip_arria10_e1sg_altera_eth_tse_pcs_pma_nf_lvds_170 +ip_arria10_e1sg_altera_xcvr_native_a10_170 +ip_arria10_e1sg_altera_eth_tse_nf_phyip_terminator_170 +ip_arria10_e1sg_altera_eth_tse_nf_lvds_terminator_170 +ip_arria10_e1sg_altera_lvds_170 +ip_arria10_e1sg_altera_reset_controller_170 + +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl new file mode 100644 index 0000000000..1e8b7658ab --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl @@ -0,0 +1,33 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" +vmap altera_eth_tse_avalon_arbiter_170 ./work/ + vlog "$IP_DIR/../altera_eth_tse_avalon_arbiter_170/sim/mentor/altera_eth_tse_avalon_arbiter.v" -work altera_eth_tse_avalon_arbiter_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/hdllib.cfg new file mode 100644 index 0000000000..71a9c4e0cc --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_avalon_arbiter_170 +hdl_library_clause_name = altera_eth_tse_avalon_arbiter_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl new file mode 100644 index 0000000000..fb9293c0bc --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl @@ -0,0 +1,148 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_eth_tse_mac_170 ./work/ + + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_eth_tse_mac.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_clk_cntl.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_crc328checker.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_crc328generator.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_crc32ctl8.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_crc32galois8.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_gmii_io.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_lb_read_cntl.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_lb_wrt_cntl.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_hashing.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_host_control.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_host_control_small.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mac_control.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_register_map.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_register_map_small.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_counter_cntl.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_shared_mac_control.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_shared_register_map.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_counter_cntl.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_lfsr_10.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_loopback_ff.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_altshifttaps.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_fifoless_mac_rx.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mac_rx.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_fifoless_mac_tx.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mac_tx.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_magic_detection.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mdio.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mdio_clk_gen.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mdio_cntl.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_mdio.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mii_rx_if.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mii_tx_if.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_pipeline_base.v" -work altera_eth_tse_mac_170 + vlog -sv "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_pipeline_stage.sv" -L altera_common_sv_packages -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_dpram_16x32.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_dpram_8x32.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_dpram_ecc_16x32.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_fifoless_retransmit_cntl.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_retransmit_cntl.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rgmii_in1.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rgmii_in4.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_nf_rgmii_module.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rgmii_module.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rgmii_out1.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rgmii_out4.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_ff.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_min_ff.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_ff_cntrl.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_ff_cntrl_32.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_ff_cntrl_32_shift16.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_ff_length.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_stat_extract.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_timing_adapter32.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_timing_adapter8.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_timing_adapter_fifo32.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_timing_adapter_fifo8.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_1geth.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_fifoless_1geth.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_w_fifo.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_w_fifo_10_100_1000.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_wo_fifo.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_wo_fifo_10_100_1000.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_gen_host.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_ff.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_min_ff.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_ff_cntrl.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_ff_cntrl_32.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_ff_cntrl_32_shift16.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_ff_length.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_ff_read_cntl.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_stat_extract.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_eth_tse_std_synchronizer_bundle.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_eth_tse_ptp_std_synchronizer.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_false_path_marker.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_clock_crosser.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_a_fifo_13.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_a_fifo_24.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_a_fifo_34.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_a_fifo_opt_1246.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_a_fifo_opt_14_44.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_a_fifo_opt_36_10.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_gray_cnt.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_sdpm_altsyncram.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_altsyncram_dpm_fifo.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_bin_cnt.v" -work altera_eth_tse_mac_170 + vlog -sv "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ph_calculator.sv" -L altera_common_sv_packages -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_sdpm_gen.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x10.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x10.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x10_wrapper.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x14.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x14.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x14_wrapper.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x2.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x2.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x2_wrapper.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x23.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x23.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x23_wrapper.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x36.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x36.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x36_wrapper.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x40.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x40.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x40_wrapper.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x30.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x30.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_status_crosser.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_mac_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/hdllib.cfg new file mode 100644 index 0000000000..c8e2e0ffd1 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_mac_170 +hdl_library_clause_name = altera_eth_tse_mac_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl new file mode 100644 index 0000000000..55bf61fc4c --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl @@ -0,0 +1,40 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" +vmap altera_eth_tse_nf_lvds_terminator_170 ./work/ + + + vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_170/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_nf_lvds_terminator_170 + vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_170/sim/mentor/altera_eth_tse_nf_lvds_terminator.v" -work altera_eth_tse_nf_lvds_terminator_170 + vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_170/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_nf_lvds_terminator_170 + vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_170/sim/mentor/altera_tse_nf_lvds_channel_reset_sequencer.v" -work altera_eth_tse_nf_lvds_terminator_170 + vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_170/sim/mentor/altera_tse_nf_lvds_common_reset_sequencer.v" -work altera_eth_tse_nf_lvds_terminator_170 + vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_170/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_nf_lvds_terminator_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/hdllib.cfg new file mode 100644 index 0000000000..ad8113152b --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_nf_lvds_terminator_170 +hdl_library_clause_name = altera_eth_tse_nf_lvds_terminator_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl new file mode 100644 index 0000000000..8fdd7610c6 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl @@ -0,0 +1,35 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_eth_tse_nf_phyip_terminator_170 ./work/ + + vlog "$IP_DIR/../altera_eth_tse_nf_phyip_terminator_170/sim/mentor/altera_eth_tse_nf_phyip_terminator.v" -work altera_eth_tse_nf_phyip_terminator_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/hdllib.cfg new file mode 100644 index 0000000000..4a68c345a3 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_nf_phyip_terminator_170 +hdl_library_clause_name = altera_eth_tse_nf_phyip_terminator_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl new file mode 100644 index 0000000000..227163ef15 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl @@ -0,0 +1,114 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_eth_tse_pcs_pma_nf_lvds_170 ./work/ + + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_eth_tse_pcs_pma_nf_lvds.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_align_sync.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_dec10b8b.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_dec_func.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_enc8b10b.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_autoneg.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_carrier_sense.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_clk_gen.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_sgmii_clk_div.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_sgmii_clk_enable.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_rx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_tx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_rx_encapsulation_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_pcs_control.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_pcs_host_control.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_mdio_reg.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_mii_rx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_mii_tx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_rx_sync.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_sgmii_clk_cntl.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_colision_detect.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_rx_fifo_rd.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_sgmii.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_sgmii_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_1000_base_x.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_1000_base_x_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_pcs.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_pcs_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_rx.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_tx.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_lvds_reset_sequencer.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_lvds_reverse_loopback.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_pma_lvds_rx_av.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_pma_lvds_rx.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_pma_lvds_tx.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_eth_tse_std_synchronizer_bundle.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_eth_tse_ptp_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_false_path_marker.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_clock_crosser.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_a_fifo_13.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_a_fifo_24.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_a_fifo_34.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_a_fifo_opt_1246.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_a_fifo_opt_14_44.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_a_fifo_opt_36_10.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_gray_cnt.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_sdpm_altsyncram.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_altsyncram_dpm_fifo.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_bin_cnt.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ph_calculator.sv" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_sdpm_gen.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_dec_x10.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x10.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x10_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_dec_x14.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x14.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x14_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_dec_x2.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x2.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x2_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_dec_x23.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x23.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x23_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_dec_x36.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x36.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x36_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_dec_x40.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x40.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x40_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_dec_x30.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x30.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_status_crosser.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/hdllib.cfg new file mode 100644 index 0000000000..0bb69ecf00 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_pcs_pma_nf_lvds_170 +hdl_library_clause_name = altera_eth_tse_pcs_pma_nf_lvds_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl new file mode 100644 index 0000000000..93abb8da7f --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl @@ -0,0 +1,116 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + + +vmap altera_eth_tse_pcs_pma_nf_phyip_170 ./work/ + + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages + + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_eth_tse_pcs_pma_nf_phyip.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_align_sync.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_dec10b8b.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_dec_func.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_enc8b10b.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_autoneg.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_carrier_sense.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_clk_gen.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_sgmii_clk_div.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_sgmii_clk_enable.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_rx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_tx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_rx_encapsulation_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_pcs_control.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_pcs_host_control.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_mdio_reg.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_mii_rx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_mii_tx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_rx_sync.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_sgmii_clk_cntl.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_colision_detect.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_rx_fifo_rd.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_sgmii.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_sgmii_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_1000_base_x.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_1000_base_x_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_pcs.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_pcs_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_rx.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_tx.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_reset_sequencer.sv" -L altera_common_sv_packages -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_reset_ctrl_lego.sv" -L altera_common_sv_packages -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_xcvr_resync.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_gxb_aligned_rxsync.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_eth_tse_std_synchronizer_bundle.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_eth_tse_ptp_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_false_path_marker.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_clock_crosser.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_a_fifo_13.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_a_fifo_24.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_a_fifo_34.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_a_fifo_opt_1246.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_a_fifo_opt_14_44.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_a_fifo_opt_36_10.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_gray_cnt.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_sdpm_altsyncram.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_altsyncram_dpm_fifo.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_bin_cnt.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ph_calculator.sv" -L altera_common_sv_packages -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_sdpm_gen.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_dec_x10.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x10.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x10_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_dec_x14.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x14.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x14_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_dec_x2.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x2.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x2_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_dec_x23.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x23.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x23_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_dec_x36.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x36.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x36_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_dec_x40.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x40.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x40_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_dec_x30.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x30.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_status_crosser.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/hdllib.cfg new file mode 100644 index 0000000000..14e02053d5 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_pcs_pma_nf_phyip_170 +hdl_library_clause_name = altera_eth_tse_pcs_pma_nf_phyip_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl new file mode 100644 index 0000000000..e6fc09b1ff --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl @@ -0,0 +1,41 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +vmap altera_iopll_170 ./work/ + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_iopll_170/sim/ip_arria10_e1sg_pll_clk25_altera_iopll_170_7lq52ua.vo" -work altera_iopll_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_iopll_170/sim/ip_arria10_e1sg_pll_clk125_altera_iopll_170_3a4ewza.vo" -work altera_iopll_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_iopll_170/sim/ip_arria10_e1sg_pll_clk200_altera_iopll_170_bqwoevq.vo" -work altera_iopll_170 + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/hdllib.cfg new file mode 100644 index 0000000000..d75309def4 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altera_iopll_170 +hdl_library_clause_name = altera_iopll_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl new file mode 100644 index 0000000000..4a89f0d423 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl @@ -0,0 +1,37 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_ip_col_if_170 ./work/ + + vlog "$IP_DIR/../altera_ip_col_if_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_ip_col_if_170_bnb3mmy.v" -work altera_ip_col_if_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/hdllib.cfg new file mode 100644 index 0000000000..540bef90d6 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_ip_col_if_170 +hdl_library_clause_name = altera_ip_col_if_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl new file mode 100644 index 0000000000..827770ab54 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl @@ -0,0 +1,45 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_jtag_dc_streaming_170 ./work/ + vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_jtag_interface.v" -work altera_jtag_dc_streaming_170 + vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_jtag_dc_streaming.v" -work altera_jtag_dc_streaming_170 + vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_jtag_sld_node.v" -work altera_jtag_dc_streaming_170 + vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_jtag_streaming.v" -work altera_jtag_dc_streaming_170 + vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_clock_crosser.v" -work altera_jtag_dc_streaming_170 + vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_std_synchronizer_nocut.v" -work altera_jtag_dc_streaming_170 + vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_pipeline_base.v" -work altera_jtag_dc_streaming_170 + vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_idle_remover.v" -work altera_jtag_dc_streaming_170 + vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_idle_inserter.v" -work altera_jtag_dc_streaming_170 + vlog -sv "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_pipeline_stage.sv" -work altera_jtag_dc_streaming_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/hdllib.cfg new file mode 100644 index 0000000000..58633386cd --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_jtag_dc_streaming_170 +hdl_library_clause_name = altera_jtag_dc_streaming_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl new file mode 100644 index 0000000000..9c08ddd0b0 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl @@ -0,0 +1,34 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" +vmap altera_lvds_170 ./work/ + vcom "$IP_DIR/../altera_lvds_170/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_170_m5pqrlq.vhd" -work altera_lvds_170 + vcom "$IP_DIR/../altera_lvds_170/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_170_o42lhkq.vhd" -work altera_lvds_170 + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/hdllib.cfg new file mode 100644 index 0000000000..5aafdf155e --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altera_lvds_170 +hdl_library_clause_name = altera_lvds_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = ip_arria10_e1sg_altera_lvds_core20_170 +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl new file mode 100644 index 0000000000..d6fd3f2e14 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl @@ -0,0 +1,39 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" +vmap altera_lvds_core20_170 ./work/ + + + vlog -sv "$IP_DIR/../altera_lvds_core20_170/sim/mentor/altera_lvds_core20.sv" -work altera_lvds_core20_170 + vlog "$IP_DIR/../altera_lvds_core20_170/sim/mentor/altera_lvds_core20_pll.v" -work altera_lvds_core20_170 + vcom "$IP_DIR/../altera_lvds_core20_170/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_core20_170_qagiwoa.vhd" -work altera_lvds_core20_170 + vlog -sv "$IP_DIR/../altera_lvds_core20_170/sim/mentor/altera_lvds_core20.sv" -work altera_lvds_core20_170 + vlog "$IP_DIR/../altera_lvds_core20_170/sim/mentor/altera_lvds_core20_pll.v" -work altera_lvds_core20_170 + vcom "$IP_DIR/../altera_lvds_core20_170/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_core20_170_o4ldvbi.vhd" -work altera_lvds_core20_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/hdllib.cfg new file mode 100644 index 0000000000..a72e4c297c --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altera_lvds_core20_170 +hdl_library_clause_name = altera_lvds_core20_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl new file mode 100644 index 0000000000..70d8705785 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl @@ -0,0 +1,36 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_merlin_master_translator_170 ./work/ + + vlog -sv "$IP_DIR/../altera_merlin_master_translator_170/sim/altera_merlin_master_translator.sv" -work altera_merlin_master_translator_170 + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/hdllib.cfg new file mode 100644 index 0000000000..1f2a23c00e --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_merlin_master_translator_170 +hdl_library_clause_name = altera_merlin_master_translator_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl new file mode 100644 index 0000000000..5677602798 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl @@ -0,0 +1,36 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_merlin_slave_translator_170 ./work/ + + vlog -sv "$IP_DIR/../altera_merlin_slave_translator_170/sim/mentor/altera_merlin_slave_translator.sv" -work altera_merlin_slave_translator_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/hdllib.cfg new file mode 100644 index 0000000000..ef9b259c5f --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_merlin_slave_translator_170 +hdl_library_clause_name = altera_merlin_slave_translator_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl new file mode 100644 index 0000000000..a2cfe1b1c1 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl @@ -0,0 +1,46 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# +vmap altera_mm_interconnect_170 ./work/ + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_3gbam2q.vhd" -work altera_mm_interconnect_170 + vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170 + vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_lcqbbfq.vhd" -work altera_mm_interconnect_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170 + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/hdllib.cfg new file mode 100644 index 0000000000..f08778a020 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_mm_interconnect_170 +hdl_library_clause_name = altera_mm_interconnect_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = ip_arria10_e1sg_altera_merlin_master_translator_170 ip_arria10_e1sg_altera_merlin_slave_translator_170 +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl new file mode 100644 index 0000000000..57ddfbe2f4 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl @@ -0,0 +1,37 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_remote_update_170 ./work/ + + vcom "$IP_DIR/../altera_remote_update_170/sim/ip_arria10_e1sg_remote_update_altera_remote_update_170_hsvaqga.vhd" -work altera_remote_update_170 + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/hdllib.cfg new file mode 100644 index 0000000000..fed8c35d6c --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/hdllib.cfg @@ -0,0 +1,15 @@ +hdl_lib_name = ip_arria10_e1sg_altera_remote_update_170 +hdl_library_clause_name = altera_remote_update_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = ip_arria10_e1sg_altera_remote_update_core_170 +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl new file mode 100644 index 0000000000..f9ee623401 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl @@ -0,0 +1,40 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + + +vmap altera_remote_update_core_170 ./work/ + + + vlog "$IP_DIR/../altera_remote_update_core_170/sim/mentor/altera_remote_update_core.sv" -work altera_remote_update_core_170 + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/hdllib.cfg new file mode 100644 index 0000000000..ef449921eb --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/hdllib.cfg @@ -0,0 +1,12 @@ +hdl_lib_name = ip_arria10_e1sg_altera_remote_update_core_170 +hdl_library_clause_name = altera_remote_update_core_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl new file mode 100644 index 0000000000..2ec6c18582 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl @@ -0,0 +1,37 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_reset_controller_170 ./work/ + + vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_170 + vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/hdllib.cfg new file mode 100644 index 0000000000..2bf3f30746 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_reset_controller_170 +hdl_library_clause_name = altera_reset_controller_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl new file mode 100644 index 0000000000..fca02130c3 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl @@ -0,0 +1,55 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_common_sv_packages ./work/ +vmap altera_xcvr_atx_pll_a10_170 ./work/ + + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/mentor/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/mentor/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/mentor/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/a10_avmm_h.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/alt_xcvr_atx_pll_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/a10_xcvr_atx_pll.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/alt_xcvr_pll_embedded_debug.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/alt_xcvr_pll_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/mentor/alt_xcvr_atx_pll_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/mentor/a10_xcvr_atx_pll.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/mentor/alt_xcvr_pll_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_170_3gt7q7a.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/alt_xcvr_atx_pll_rcfg_opt_logic_3gt7q7a.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/hdllib.cfg new file mode 100644 index 0000000000..db46806823 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altera_xcvr_atx_pll_a10_170 +hdl_library_clause_name = altera_xcvr_atx_pll_a10_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl new file mode 100644 index 0000000000..8ea648de46 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl @@ -0,0 +1,50 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_xcvr_fpll_a10_170 ./work/ + +#pll_xgmii_mac_clocks + vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/twentynm_xcvr_avmm.sv" -work altera_xcvr_fpll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/twentynm_xcvr_avmm.sv" -work altera_xcvr_fpll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_resync.sv" -work altera_xcvr_fpll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/alt_xcvr_resync.sv" -work altera_xcvr_fpll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/altera_xcvr_fpll_a10.sv" -work altera_xcvr_fpll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/altera_xcvr_fpll_a10.sv" -work altera_xcvr_fpll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/a10_avmm_h.sv" -work altera_xcvr_fpll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_native_avmm_nf.sv" -work altera_xcvr_fpll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_pll_embedded_debug.sv" -work altera_xcvr_fpll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_pll_avmm_csr.sv" -work altera_xcvr_fpll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -work altera_xcvr_fpll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/alt_xcvr_pll_avmm_csr.sv" -work altera_xcvr_fpll_a10_170 + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/hdllib.cfg new file mode 100644 index 0000000000..fbcddbb6b9 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altera_xcvr_fpll_a10_170 +hdl_library_clause_name = altera_xcvr_fpll_a10_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl new file mode 100644 index 0000000000..25fed105f6 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl @@ -0,0 +1,98 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +vmap altera_xcvr_native_a10_170 ./work/ +vmap altera_common_sv_packages ./work/ + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +# common dependencies + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/a10_avmm_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_pipe_retry.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_prbs_accum.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_odi_accel.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_pcie_dfe_params_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_commands_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_functions_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_program.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_cpu.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_master.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_pcie_dfe_ip.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/reconfig/altera_xcvr_native_a10_reconfig_parameters.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + +# phy_10gbase_r_48 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_170_otmjdta.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_otmjdta.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + +# phy_10gbase_r_24 +#set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generated/sim" + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_170_edf7tdy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_edf7tdy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + +# phy_10gbase_r_12 +#set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generated/sim" + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_170_uyp7wca.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_uyp7wca.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + +# phy_10gbase_r_4 +#set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generated/sim" + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_170_5bntvuq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_5bntvuq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + +# phy_10gbase_r_3 +#set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generated/sim" + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_170_exiqljq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_exiqljq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + +# phy_10gbase_r +#set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generated/sim" + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_170_s7t4kxy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_s7t4kxy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + +# tse_sgmii_gx +#set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim" + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_xcvr_native_a10_170_q6y47ey.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_q6y47ey.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/hdllib.cfg new file mode 100644 index 0000000000..96fde27cdf --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_xcvr_native_a10_170 +hdl_library_clause_name = altera_xcvr_native_a10_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl new file mode 100644 index 0000000000..d6ceb0f5c9 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl @@ -0,0 +1,44 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_xcvr_reset_control_170 ./work/ + + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/altera_xcvr_functions.sv" -work altera_xcvr_reset_control_170 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/altera_xcvr_functions.sv" -work altera_xcvr_reset_control_170 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/alt_xcvr_resync.sv" -work altera_xcvr_reset_control_170 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/alt_xcvr_resync.sv" -work altera_xcvr_reset_control_170 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/altera_xcvr_reset_control.sv" -work altera_xcvr_reset_control_170 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/alt_xcvr_reset_counter.sv" -work altera_xcvr_reset_control_170 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/altera_xcvr_reset_control.sv" -work altera_xcvr_reset_control_170 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/alt_xcvr_reset_counter.sv" -work altera_xcvr_reset_control_170 + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/hdllib.cfg new file mode 100644 index 0000000000..eedb9c51bd --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_xcvr_reset_control_170 +hdl_library_clause_name = altera_xcvr_reset_control_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl new file mode 100644 index 0000000000..c5e00ff4d4 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl @@ -0,0 +1,40 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap channel_adapter_170 ./work/ + + vlog -sv "$IP_DIR/../channel_adapter_170/sim/ip_arria10_e1sg_ddr4_8g_1600_channel_adapter_170_bsi6toa.sv" -work channel_adapter_170 + vlog -sv "$IP_DIR/../channel_adapter_170/sim/ip_arria10_e1sg_ddr4_8g_1600_channel_adapter_170_xbvi4ny.sv" -work channel_adapter_170 + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/hdllib.cfg new file mode 100644 index 0000000000..eebe788ab1 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_channel_adapter_170 +hdl_library_clause_name = channel_adapter_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl new file mode 100644 index 0000000000..c96a664efa --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl @@ -0,0 +1,39 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap timing_adapter_170 ./work/ + + vlog -sv "$IP_DIR/../timing_adapter_170/sim/ip_arria10_e1sg_ddr4_8g_1600_timing_adapter_170_osazali.sv" -work timing_adapter_170 + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/hdllib.cfg new file mode 100644 index 0000000000..4633fb177d --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_timing_adapter_170 +hdl_library_clause_name = timing_adapter_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl + + + -- GitLab