add altera_libraries

libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl

+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+vmap  altera_iopll_170           ./work/
+
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
+  vlog  "$IP_DIR/../altera_iopll_170/sim/ip_arria10_e1sg_pll_clk25_altera_iopll_170_7lq52ua.vo"  -work altera_iopll_170         
+
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
+  vlog  "$IP_DIR/../altera_iopll_170/sim/ip_arria10_e1sg_pll_clk125_altera_iopll_170_3a4ewza.vo" -work altera_iopll_170          
+
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
+  vlog  "$IP_DIR/../altera_iopll_170/sim/ip_arria10_e1sg_pll_clk200_altera_iopll_170_bqwoevq.vo" -work altera_iopll_170          
+                                         

libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/hdllib.cfg

+hdl_lib_name = ip_arria10_e1sg_altera_iopll_170
+hdl_library_clause_name = altera_iopll_170
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl
+
+
+

libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl

+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist      
+#
+
+
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
+
+vmap  altera_ip_col_if_170                  ./work/
+                                              
+  vlog      "$IP_DIR/../altera_ip_col_if_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_ip_col_if_170_bnb3mmy.v"                           -work altera_ip_col_if_170                 

libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/hdllib.cfg

+hdl_lib_name = ip_arria10_e1sg_altera_ip_col_if_170
+hdl_library_clause_name = altera_ip_col_if_170
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+    
+test_bench_files = 
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl
+
+
+

libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl

+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist      
+#
+
+
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
+
+vmap  altera_jtag_dc_streaming_170          ./work/
+  vlog      "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_jtag_interface.v"                                             -work altera_jtag_dc_streaming_170         
+  vlog      "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_jtag_dc_streaming.v"                                                    -work altera_jtag_dc_streaming_170         
+  vlog      "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_jtag_sld_node.v"                                                        -work altera_jtag_dc_streaming_170         
+  vlog      "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_jtag_streaming.v"                                                       -work altera_jtag_dc_streaming_170         
+  vlog      "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_clock_crosser.v"                                              -work altera_jtag_dc_streaming_170         
+  vlog      "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_std_synchronizer_nocut.v"                                               -work altera_jtag_dc_streaming_170         
+  vlog      "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_pipeline_base.v"                                              -work altera_jtag_dc_streaming_170         
+  vlog      "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_idle_remover.v"                                               -work altera_jtag_dc_streaming_170         
+  vlog      "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_idle_inserter.v"                                              -work altera_jtag_dc_streaming_170         
+  vlog -sv  "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_pipeline_stage.sv"                                            -work altera_jtag_dc_streaming_170                 

libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/hdllib.cfg

+hdl_lib_name = ip_arria10_e1sg_altera_jtag_dc_streaming_170
+hdl_library_clause_name = altera_jtag_dc_streaming_170
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+    
+test_bench_files = 
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl
+
+
+

libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl

+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
+vmap altera_lvds_170                 ./work/
+  vcom         "$IP_DIR/../altera_lvds_170/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_170_m5pqrlq.vhd"                -work altera_lvds_170  
+  vcom         "$IP_DIR/../altera_lvds_170/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_170_o42lhkq.vhd"                -work altera_lvds_170  
+

libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/hdllib.cfg

+hdl_lib_name = ip_arria10_e1sg_altera_lvds_170
+hdl_library_clause_name = altera_lvds_170
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_lvds_core20_170
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl
+
+
+

libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl

+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
+vmap  altera_lvds_core20_170                ./work/
+
+
+  vlog -sv  "$IP_DIR/../altera_lvds_core20_170/sim/mentor/altera_lvds_core20.sv"                                          -work altera_lvds_core20_170               
+  vlog      "$IP_DIR/../altera_lvds_core20_170/sim/mentor/altera_lvds_core20_pll.v"                                       -work altera_lvds_core20_170               
+  vcom         "$IP_DIR/../altera_lvds_core20_170/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_core20_170_qagiwoa.vhd"  -work altera_lvds_core20_170               
+  vlog -sv  "$IP_DIR/../altera_lvds_core20_170/sim/mentor/altera_lvds_core20.sv"                                          -work altera_lvds_core20_170               
+  vlog      "$IP_DIR/../altera_lvds_core20_170/sim/mentor/altera_lvds_core20_pll.v"                                       -work altera_lvds_core20_170               
+  vcom         "$IP_DIR/../altera_lvds_core20_170/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_core20_170_o4ldvbi.vhd"  -work altera_lvds_core20_170  

libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/hdllib.cfg

+hdl_lib_name = ip_arria10_e1sg_altera_lvds_core20_170
+hdl_library_clause_name = altera_lvds_core20_170
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl
+
+
+

libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl

+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist      
+#
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
+
+vmap  altera_merlin_master_translator_170 ./work/
+        
+  vlog -sv  "$IP_DIR/../altera_merlin_master_translator_170/sim/altera_merlin_master_translator.sv"                                     -work altera_merlin_master_translator_170
+                                                      

libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/hdllib.cfg

+hdl_lib_name = ip_arria10_e1sg_altera_merlin_master_translator_170
+hdl_library_clause_name = altera_merlin_master_translator_170
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+    
+test_bench_files = 
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl
+
+
+

libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl

+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist      
+#
+
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
+ 
+vmap  altera_merlin_slave_translator_170  ./work/
+                                                      
+  vlog -sv  "$IP_DIR/../altera_merlin_slave_translator_170/sim/mentor/altera_merlin_slave_translator.sv"                                -work altera_merlin_slave_translator_170 

libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/hdllib.cfg

+hdl_lib_name = ip_arria10_e1sg_altera_merlin_slave_translator_170
+hdl_library_clause_name = altera_merlin_slave_translator_170
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+    
+test_bench_files = 
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl
+
+
+

libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl

+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist      
+#
+vmap  altera_mm_interconnect_170          ./work/
+
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
+  vcom         "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_mm_interconnect_170_o2ys4ki.vhd"             -work altera_mm_interconnect_170         
+
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
+  vcom         "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_mm_interconnect_170_o2ys4ki.vhd"             -work altera_mm_interconnect_170         
+
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
+  vcom         "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_3gbam2q.vhd"             -work altera_mm_interconnect_170
+  vcom         "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_o2ys4ki.vhd"             -work altera_mm_interconnect_170
+  vcom         "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_lcqbbfq.vhd"             -work altera_mm_interconnect_170
+
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
+  vcom         "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_170_o2ys4ki.vhd"             -work altera_mm_interconnect_170         
+                                                      

libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/hdllib.cfg

+hdl_lib_name = ip_arria10_e1sg_altera_mm_interconnect_170
+hdl_library_clause_name = altera_mm_interconnect_170
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_merlin_master_translator_170 ip_arria10_e1sg_altera_merlin_slave_translator_170
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+    
+test_bench_files = 
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl
+
+
+

libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl

+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
+
+vmap  altera_remote_update_170      ./work/
+
+  vcom  "$IP_DIR/../altera_remote_update_170/sim/ip_arria10_e1sg_remote_update_altera_remote_update_170_hsvaqga.vhd" -work altera_remote_update_170     
+                                                            

libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/hdllib.cfg

+hdl_lib_name = ip_arria10_e1sg_altera_remote_update_170
+hdl_library_clause_name = altera_remote_update_170
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_remote_update_core_170
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl
+

libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl

+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
+
+
+vmap  altera_remote_update_core_170 ./work/
+
+
+  vlog  "$IP_DIR/../altera_remote_update_core_170/sim/mentor/altera_remote_update_core.sv"                           -work altera_remote_update_core_170
+  
+                                                            

libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/hdllib.cfg

+hdl_lib_name = ip_arria10_e1sg_altera_remote_update_core_170
+hdl_library_clause_name = altera_remote_update_core_170
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+    
+test_bench_files = 
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl