diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..ed9f1e35b618c48b70d4fde159949d9a2aba3592 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl @@ -0,0 +1,149 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap alt_em10g32_170 ./work/ + + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/alt_em10g32.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/alt_em10g32unit.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_clk_rst.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_clock_crosser.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_crc32.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_crc32_gf_mult32_kc.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_creg_map.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_creg_top.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_frm_decoder.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_rs_gmii_mii_layer.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_pipeline_base.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_reset_synchronizer.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rr_clock_crosser.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rst_cnt.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_fctl_filter_crcpad_rem.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_fctl_overflow.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_fctl_preamble.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_frm_control.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_pfc_flow_control.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_pfc_pause_conversion.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_pkt_backpressure_control.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_rs_gmii16b.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_rs_gmii16b_top.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_rs_gmii_mii.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_rs_layer.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_rs_xgmii.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_status_aligner.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_top.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_stat_mem.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_stat_reg.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_data_frm_gen.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_srcaddr_inserter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_err_aligner.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_flow_control.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_frm_arbiter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_frm_muxer.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_pause_beat_conversion.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_pause_frm_gen.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_pause_req.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_pfc_frm_gen.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rr_buffer.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_rs_gmii16b.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_rs_gmii16b_top.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_rs_layer.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_rs_xgmii_layer.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_sc_fifo.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_top.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_gmii_decoder.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_gmii_decoder_dfa.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii_encoder.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii_encoder_dfa.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_gmii_mii_decoder_if.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii_mii_encoder_if.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_mm_adapter/altera_eth_avalon_mm_adapter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_avalon_st_adapter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_rx.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_tx.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/alt_em10g32_vldpkt_rddly.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter_rx.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter_tx.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_sideband_crosser.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_sideband_crosser_sync.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_64_xgmii_conversion.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_to_64_xgmii_conversion.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_64_to_32_xgmii_conversion.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_dcfifo_32_to_64_xgmii_conversion.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_dcfifo_64_to_32_xgmii_conversion.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_32_to_64_adapter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_64_to_32_adapter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_data_format_adapter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_altsyncram_bundle.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_altsyncram.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_lat_calc.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_hecc.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_secc.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo_hecc.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo_secc.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_ecc_dec_18_12.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_ecc_dec_39_32.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_ecc_enc_12_18.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_ecc_enc_32_39.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_rs_xgmii_layer_ultra.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_rs_xgmii_ultra.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avst_to_gmii_if.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_gmii_to_avst_if.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_gmii_tsu.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_gmii16b_tsu.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_lpm_mult.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_ptp_aligner.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_ptp_detector.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_ptp_top.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii_crc_inserter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii16b_crc_inserter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii_ptp_inserter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii16b_ptp_inserter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii16b_ptp_inserter_1g2p5g10g.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_ptp_processor.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_ptp_top.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_xgmii_crc_inserter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_xgmii_ptp_inserter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_xgmii_tsu.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_crc328generator.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_crc32ctl8.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_crc32galois8.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_gmii_crc_inserter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_gmii16b_crc_inserter.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_gmii16b_crc32.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/alt_em10g32_avalon_dc_fifo.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/alt_em10g32_dcfifo_synchronizer_bundle.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/alt_em10g32_std_synchronizer.v" -work alt_em10g32_170 + vlog "$IP_DIR/../alt_em10g32_170/sim/altera_std_synchronizer_nocut.v" -work alt_em10g32_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..fecc7601f59eb50369a80014a5f7c22964f602d6 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/hdllib.cfg @@ -0,0 +1,20 @@ +hdl_lib_name = ip_arria10_e1sg_alt_em10g32_170 +hdl_library_clause_name = alt_em10g32_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + # The generated testbench is listed here to create a simulation configuration for it. However + # the tb is commented because it is not useful, see generate_ip.sh. + #$HDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..d35f46a0c17546c93d959dadbd9aa09b37029eaa --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl @@ -0,0 +1,38 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap alt_mem_if_jtag_master_170 ./work/ + + vcom "$IP_DIR/../alt_mem_if_jtag_master_170/sim/ip_arria10_e1sg_ddr4_8g_1600_alt_mem_if_jtag_master_170_biwt3uq.vhd" -work alt_mem_if_jtag_master_170 + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..189c63a2b6562c000a976d029ae6abb440f454ca --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_alt_mem_if_jtag_master_170 +hdl_library_clause_name = alt_mem_if_jtag_master_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = ip_arria10_e1sg_altera_jtag_dc_streaming_170 ip_arria10_e1sg_timing_adapter_170 ip_arria10_e1sg_altera_avalon_sc_fifo_170 ip_arria10_e1sg_altera_avalon_st_bytes_to_packets_170 ip_arria10_e1sg_altera_avalon_st_packets_to_bytes_170 ip_arria10_e1sg_altera_avalon_packets_to_master_170 ip_arria10_e1sg_channel_adapter_170 ip_arria10_e1sg_altera_reset_controller_170 + +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..e1cdadbeab388c772f7994c60c79f3f9702572b3 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl @@ -0,0 +1,35 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altclkctrl_170 ./work/ + vcom "$IP_DIR/../altclkctrl_170/sim/ip_arria10_e1sg_clkbuf_global_altclkctrl_170_7fwzyby.vhd" -work altclkctrl_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..150dab121407f6ea5247cfba2422b49a422808bc --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altclkctrl_170 +hdl_library_clause_name = altclkctrl_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..f344ad332c3d0c259217199ff912ab5cdfdba37e --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl @@ -0,0 +1,37 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +vlib ./work/ ;# Assume library work already exist + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_asmi_parallel_170 ./work/ + + + vcom "$IP_DIR/../altera_asmi_parallel_170/sim/ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_170_eou4tfa.vhd" -work altera_asmi_parallel_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..0e8e55c1e66a7cf84fb1832f5ed9cd4566232e5d --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/hdllib.cfg @@ -0,0 +1,15 @@ +hdl_lib_name = ip_arria10_e1sg_altera_asmi_parallel_170 +hdl_library_clause_name = altera_asmi_parallel_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..19c655935fc75dd20dfa6dfbefd11b447af83712 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl @@ -0,0 +1,35 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_avalon_mm_bridge_170 ./work/ + + vlog "$IP_DIR/../altera_avalon_mm_bridge_170/sim/altera_avalon_mm_bridge.v" -work altera_avalon_mm_bridge_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..1f0e8108fd2c3ac34bc3004d4cc4f1a5101237c4 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/hdllib.cfg @@ -0,0 +1,20 @@ +hdl_lib_name = ip_arria10_e1sg_altera_avalon_mm_bridge_170 +hdl_library_clause_name = altera_avalon_mm_bridge_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + # The generated testbench is listed here to create a simulation configuration for it. However + # the tb is commented because it is not useful, see generate_ip.sh. + #$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..3da14b9e74fa176ecc3c14f8b574196eb236210b --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl @@ -0,0 +1,46 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# +vmap altera_avalon_onchip_memory2_170 ./work/ + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170 + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..2edea37fa91875f04b9549e9bdebfc457efe2a71 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_avalon_onchip_memory2_170 +hdl_library_clause_name = altera_avalon_onchip_memory2_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..2936776afa142109e545ac1ad7d01e2d879b26f1 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl @@ -0,0 +1,37 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_avalon_packets_to_master_170 ./work/ + + vlog "$IP_DIR/../altera_avalon_packets_to_master_170/sim/altera_avalon_packets_to_master.v" -work altera_avalon_packets_to_master_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..0dc7501636e1a4dde423d7e9b1e7fe132b8681ae --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_avalon_packets_to_master_170 +hdl_library_clause_name = altera_avalon_packets_to_master_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..54dd8ac6a658c2cd69dca28c13ea4217b13ee966 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl @@ -0,0 +1,40 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_avalon_sc_fifo_170 ./work/ + vlog "$IP_DIR/../altera_avalon_sc_fifo_170/sim/altera_avalon_sc_fifo.v" -work altera_avalon_sc_fifo_170 + + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..f8ab200bc09097dba9bbd9fc92a2749814a9738d --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_avalon_sc_fifo_170 +hdl_library_clause_name = altera_avalon_sc_fifo_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..07d698207f4aebd212582129268a73a1e671ad42 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl @@ -0,0 +1,37 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_avalon_st_bytes_to_packets_170 ./work/ + + vlog "$IP_DIR/../altera_avalon_st_bytes_to_packets_170/sim/altera_avalon_st_bytes_to_packets.v" -work altera_avalon_st_bytes_to_packets_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..0662c5a3d2d3992f6c1c2fce438e9375b3f4a64d --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_avalon_st_bytes_to_packets_170 +hdl_library_clause_name = altera_avalon_st_bytes_to_packets_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..89f59ac908366d8720a9ccc7d65c029d6bb58199 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl @@ -0,0 +1,39 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" +vmap altera_avalon_st_packets_to_bytes_170 ./work/ + + vlog "$IP_DIR/../altera_avalon_st_packets_to_bytes_170/sim/altera_avalon_st_packets_to_bytes.v" -work altera_avalon_st_packets_to_bytes_170 + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..f8cf50573a24551facc73d506e8bb6501eac3bd7 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_avalon_st_packets_to_bytes_170 +hdl_library_clause_name = altera_avalon_st_packets_to_bytes_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..169d99bda6ec620ed01347494ee751413dc826e4 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl @@ -0,0 +1,162 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# +vmap altera_emif_170 ./work/ +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_emif_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_170_verwnda.v" -work altera_emif_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_emif_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_170_2hmjbxa.v" -work altera_emif_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_emif_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_170_7ixm4xa.v" -work altera_emif_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_emif_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_170_xxodvzi.v" -work altera_emif_170 + +vmap altera_emif_arch_nf_170 ./work/ +# ddr4_4g_1600 +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti_top.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti_io_aux.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti.sv" -work altera_emif_arch_nf_170 + +# ddr4_4g_2000 +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq_top.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq_io_aux.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq.sv" -work altera_emif_arch_nf_170 + +# ddr4_8g_1600 +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei_top.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei_io_aux.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei.sv" -work altera_emif_arch_nf_170 + +# ddr4_8g_2400 +set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim" + + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_170_as3yf3i_top.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_170_as3yf3i_io_aux.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_170_as3yf3i.sv" -work altera_emif_arch_nf_170 + +# common dependencies + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_bufs.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_se_i.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_se_o.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_df_i.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_df_o.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_cp_i.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_bdir_df.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_bdir_se.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_unused.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_cal_counter.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll_fast_sim.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll_extra_clks.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_oct.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_core_clks_rsts.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hps_clks_rsts.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles_wrap.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles_abphy.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_abphy_mux.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_avl_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_sideband_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_mmr_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_amm_data_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_ast_data_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_afi_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_seq_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_regs.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_oct.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_oct_um_fsm.sv" -work altera_emif_arch_nf_170 + vlog "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_std_synchronizer_nocut.v" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/mem_array_abphy.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_abphy.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_encrypted_abphy.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_nf5es_encrypted_abphy.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/io_12_lane_bcm__nf5es_abphy.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/io_12_lane__nf5es_abphy.sv" -work altera_emif_arch_nf_170 + +vmap altera_emif_cal_slave_nf_170 ./work/ +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170 + +vmap altera_reset_controller_170 ./work/ +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_170 + vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_170 + +vmap altera_mm_interconnect_170 ./work/ +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_3gbam2q.vhd" -work altera_mm_interconnect_170 + vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170 + vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_lcqbbfq.vhd" -work altera_mm_interconnect_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170 + +vmap altera_avalon_onchip_memory2_170 ./work/ +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170 + + +vmap altera_avalon_mm_bridge_170 ./work/ +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + + vlog "$IP_DIR/../altera_avalon_mm_bridge_170/sim/altera_avalon_mm_bridge.v" -work altera_avalon_mm_bridge_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..7e1017d4fddbf395af61b31df28c2e4428e91687 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_emif_170 +hdl_library_clause_name = altera_emif_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = ip_arria10_e1sg_altera_merlin_master_translator_170 ip_arria10_e1sg_altera_merlin_slave_translator_170 +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..b4f18e92ca198057921da394d14ff6cc9c558e6f --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl @@ -0,0 +1,98 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +vmap altera_emif_arch_nf_170 ./work/ + +# ddr4_4g_1600 +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti_top.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti_io_aux.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti.sv" -work altera_emif_arch_nf_170 + +# ddr4_4g_2000 +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq_top.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq_io_aux.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq.sv" -work altera_emif_arch_nf_170 + +# ddr4_8g_1600 +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei_top.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei_io_aux.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei.sv" -work altera_emif_arch_nf_170 + +# ddr4_8g_2400 +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_170_as3yf3i_top.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_170_as3yf3i_io_aux.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_170_as3yf3i.sv" -work altera_emif_arch_nf_170 + +# common dependencies + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_bufs.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_se_i.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_se_o.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_df_i.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_df_o.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_cp_i.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_bdir_df.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_bdir_se.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_unused.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_cal_counter.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll_fast_sim.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll_extra_clks.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_oct.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_core_clks_rsts.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hps_clks_rsts.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles_wrap.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles_abphy.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_abphy_mux.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_avl_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_sideband_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_mmr_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_amm_data_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_ast_data_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_afi_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_seq_if.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_regs.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_oct.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_oct_um_fsm.sv" -work altera_emif_arch_nf_170 + vlog "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_std_synchronizer_nocut.v" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/mem_array_abphy.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_abphy.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_encrypted_abphy.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_nf5es_encrypted_abphy.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/io_12_lane_bcm__nf5es_abphy.sv" -work altera_emif_arch_nf_170 + vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/io_12_lane__nf5es_abphy.sv" -work altera_emif_arch_nf_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..aa1549a76543830f29f84626cac1cdaab46c22f0 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/hdllib.cfg @@ -0,0 +1,20 @@ +hdl_lib_name = ip_arria10_e1sg_altera_emif_arch_nf_170 +hdl_library_clause_name = altera_emif_arch_nf_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + # The generated testbench is listed here to create a simulation configuration for it. However + # the tb is commented because it is not useful, see generate_ip.sh. + #$HDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..656287d795e744bd67177a67bca475b4e056cb1e --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl @@ -0,0 +1,47 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# + +vmap altera_emif_cal_slave_nf_170 ./work/ + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170 + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..c56bf53d57b495d9993c7d25ef95deac432d03b2 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_emif_cal_slave_nf_170 +hdl_library_clause_name = altera_emif_cal_slave_nf_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..1b531d9615535597ee921426a571a3878178fe01 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl @@ -0,0 +1,40 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +vmap altera_eth_tse_170 ./work/ + +# tse_sgmii_gx +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" +vcom "$IP_DIR/../altera_eth_tse_170/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_170_bs6nd6i.vhd" -work altera_eth_tse_170 + +# tse_sgmii_lvds +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" +vcom "$IP_DIR/../altera_eth_tse_170/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_170_kv2t7sq.vhd" -work altera_eth_tse_170 + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..a21ef74c59d0a5c854f86e48a0c557129baaf750 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/hdllib.cfg @@ -0,0 +1,27 @@ +hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_170 +hdl_library_clause_name = altera_eth_tse_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +ip_arria10_e1sg_altera_eth_tse_mac_170 +ip_arria10_e1sg_altera_eth_tse_avalon_arbiter_170 +ip_arria10_e1sg_altera_eth_tse_pcs_pma_nf_phyip_170 +ip_arria10_e1sg_altera_eth_tse_pcs_pma_nf_lvds_170 +ip_arria10_e1sg_altera_xcvr_native_a10_170 +ip_arria10_e1sg_altera_eth_tse_nf_phyip_terminator_170 +ip_arria10_e1sg_altera_eth_tse_nf_lvds_terminator_170 +ip_arria10_e1sg_altera_lvds_170 +ip_arria10_e1sg_altera_reset_controller_170 + +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..1e8b7658abe7beafb5da529a5e3d36d06bab2839 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl @@ -0,0 +1,33 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" +vmap altera_eth_tse_avalon_arbiter_170 ./work/ + vlog "$IP_DIR/../altera_eth_tse_avalon_arbiter_170/sim/mentor/altera_eth_tse_avalon_arbiter.v" -work altera_eth_tse_avalon_arbiter_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..71a9c4e0ccefa77ed0b2e5be5bbccf68222ccee4 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_avalon_arbiter_170 +hdl_library_clause_name = altera_eth_tse_avalon_arbiter_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..fb9293c0bcd841186b057d292a17a69ce8b1f9da --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl @@ -0,0 +1,148 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_eth_tse_mac_170 ./work/ + + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_eth_tse_mac.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_clk_cntl.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_crc328checker.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_crc328generator.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_crc32ctl8.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_crc32galois8.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_gmii_io.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_lb_read_cntl.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_lb_wrt_cntl.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_hashing.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_host_control.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_host_control_small.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mac_control.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_register_map.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_register_map_small.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_counter_cntl.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_shared_mac_control.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_shared_register_map.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_counter_cntl.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_lfsr_10.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_loopback_ff.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_altshifttaps.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_fifoless_mac_rx.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mac_rx.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_fifoless_mac_tx.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mac_tx.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_magic_detection.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mdio.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mdio_clk_gen.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mdio_cntl.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_mdio.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mii_rx_if.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mii_tx_if.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_pipeline_base.v" -work altera_eth_tse_mac_170 + vlog -sv "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_pipeline_stage.sv" -L altera_common_sv_packages -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_dpram_16x32.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_dpram_8x32.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_dpram_ecc_16x32.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_fifoless_retransmit_cntl.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_retransmit_cntl.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rgmii_in1.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rgmii_in4.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_nf_rgmii_module.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rgmii_module.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rgmii_out1.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rgmii_out4.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_ff.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_min_ff.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_ff_cntrl.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_ff_cntrl_32.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_ff_cntrl_32_shift16.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_ff_length.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_stat_extract.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_timing_adapter32.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_timing_adapter8.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_timing_adapter_fifo32.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_timing_adapter_fifo8.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_1geth.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_fifoless_1geth.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_w_fifo.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_w_fifo_10_100_1000.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_wo_fifo.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_wo_fifo_10_100_1000.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_gen_host.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_ff.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_min_ff.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_ff_cntrl.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_ff_cntrl_32.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_ff_cntrl_32_shift16.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_ff_length.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_ff_read_cntl.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_stat_extract.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_eth_tse_std_synchronizer_bundle.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_eth_tse_ptp_std_synchronizer.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_false_path_marker.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_clock_crosser.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_a_fifo_13.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_a_fifo_24.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_a_fifo_34.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_a_fifo_opt_1246.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_a_fifo_opt_14_44.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_a_fifo_opt_36_10.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_gray_cnt.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_sdpm_altsyncram.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_altsyncram_dpm_fifo.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_bin_cnt.v" -work altera_eth_tse_mac_170 + vlog -sv "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ph_calculator.sv" -L altera_common_sv_packages -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_sdpm_gen.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x10.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x10.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x10_wrapper.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x14.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x14.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x14_wrapper.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x2.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x2.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x2_wrapper.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x23.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x23.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x23_wrapper.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x36.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x36.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x36_wrapper.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x40.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x40.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x40_wrapper.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x30.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x30.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_status_crosser.v" -work altera_eth_tse_mac_170 + vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_mac_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..c8e2e0ffd18c89f4b602ba39e0c5e6d438af94d0 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_mac_170 +hdl_library_clause_name = altera_eth_tse_mac_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..55bf61fc4c7c965adec4d7e660909e3c0c608a13 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl @@ -0,0 +1,40 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" +vmap altera_eth_tse_nf_lvds_terminator_170 ./work/ + + + vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_170/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_nf_lvds_terminator_170 + vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_170/sim/mentor/altera_eth_tse_nf_lvds_terminator.v" -work altera_eth_tse_nf_lvds_terminator_170 + vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_170/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_nf_lvds_terminator_170 + vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_170/sim/mentor/altera_tse_nf_lvds_channel_reset_sequencer.v" -work altera_eth_tse_nf_lvds_terminator_170 + vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_170/sim/mentor/altera_tse_nf_lvds_common_reset_sequencer.v" -work altera_eth_tse_nf_lvds_terminator_170 + vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_170/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_nf_lvds_terminator_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..ad8113152b568e100f561238fa51a0f3119c220e --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_nf_lvds_terminator_170 +hdl_library_clause_name = altera_eth_tse_nf_lvds_terminator_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..8fdd7610c60cf88eb22060876a65bf57421d1253 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl @@ -0,0 +1,35 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_eth_tse_nf_phyip_terminator_170 ./work/ + + vlog "$IP_DIR/../altera_eth_tse_nf_phyip_terminator_170/sim/mentor/altera_eth_tse_nf_phyip_terminator.v" -work altera_eth_tse_nf_phyip_terminator_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..4a68c345a399bbe25d3de95fca7c004ef5ba7ee0 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_nf_phyip_terminator_170 +hdl_library_clause_name = altera_eth_tse_nf_phyip_terminator_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..227163ef15ee6f0ae9deae1366a87ab37859026d --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl @@ -0,0 +1,114 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_eth_tse_pcs_pma_nf_lvds_170 ./work/ + + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_eth_tse_pcs_pma_nf_lvds.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_align_sync.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_dec10b8b.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_dec_func.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_enc8b10b.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_autoneg.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_carrier_sense.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_clk_gen.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_sgmii_clk_div.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_sgmii_clk_enable.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_rx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_tx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_rx_encapsulation_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_pcs_control.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_pcs_host_control.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_mdio_reg.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_mii_rx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_mii_tx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_rx_sync.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_sgmii_clk_cntl.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_colision_detect.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_rx_fifo_rd.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_sgmii.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_sgmii_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_1000_base_x.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_1000_base_x_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_pcs.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_pcs_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_rx.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_tx.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_lvds_reset_sequencer.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_lvds_reverse_loopback.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_pma_lvds_rx_av.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_pma_lvds_rx.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_pma_lvds_tx.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_eth_tse_std_synchronizer_bundle.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_eth_tse_ptp_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_false_path_marker.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_clock_crosser.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_a_fifo_13.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_a_fifo_24.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_a_fifo_34.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_a_fifo_opt_1246.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_a_fifo_opt_14_44.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_a_fifo_opt_36_10.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_gray_cnt.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_sdpm_altsyncram.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_altsyncram_dpm_fifo.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_bin_cnt.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ph_calculator.sv" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_sdpm_gen.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_dec_x10.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x10.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x10_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_dec_x14.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x14.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x14_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_dec_x2.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x2.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x2_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_dec_x23.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x23.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x23_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_dec_x36.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x36.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x36_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_dec_x40.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x40.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x40_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_dec_x30.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x30.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_status_crosser.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_pcs_pma_nf_lvds_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..0bb69ecf007e80ef1de8b796ff5d88e0d27bf4bb --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_pcs_pma_nf_lvds_170 +hdl_library_clause_name = altera_eth_tse_pcs_pma_nf_lvds_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..93abb8da7fd7ed3e9b1b3ae1f1f9d1a78a37ba58 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl @@ -0,0 +1,116 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + + +vmap altera_eth_tse_pcs_pma_nf_phyip_170 ./work/ + + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages + + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_eth_tse_pcs_pma_nf_phyip.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_align_sync.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_dec10b8b.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_dec_func.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_enc8b10b.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_autoneg.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_carrier_sense.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_clk_gen.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_sgmii_clk_div.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_sgmii_clk_enable.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_rx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_tx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_rx_encapsulation_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_pcs_control.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_pcs_host_control.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_mdio_reg.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_mii_rx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_mii_tx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_rx_sync.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_sgmii_clk_cntl.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_colision_detect.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_rx_fifo_rd.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_sgmii.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_sgmii_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_1000_base_x.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_1000_base_x_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_pcs.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_pcs_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_rx.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_tx.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_reset_sequencer.sv" -L altera_common_sv_packages -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_reset_ctrl_lego.sv" -L altera_common_sv_packages -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_xcvr_resync.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_gxb_aligned_rxsync.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_eth_tse_std_synchronizer_bundle.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_eth_tse_ptp_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_false_path_marker.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_clock_crosser.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_a_fifo_13.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_a_fifo_24.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_a_fifo_34.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_a_fifo_opt_1246.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_a_fifo_opt_14_44.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_a_fifo_opt_36_10.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_gray_cnt.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_sdpm_altsyncram.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_altsyncram_dpm_fifo.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_bin_cnt.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ph_calculator.sv" -L altera_common_sv_packages -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_sdpm_gen.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_dec_x10.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x10.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x10_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_dec_x14.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x14.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x14_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_dec_x2.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x2.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x2_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_dec_x23.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x23.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x23_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_dec_x36.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x36.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x36_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_dec_x40.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x40.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x40_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_dec_x30.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x30.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_status_crosser.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 + vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_pcs_pma_nf_phyip_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..14e02053d5240acae9c43e5170e86f713fc0cd5c --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_pcs_pma_nf_phyip_170 +hdl_library_clause_name = altera_eth_tse_pcs_pma_nf_phyip_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..e6fc09b1ffd8249ec775a36c577905c9963d9067 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl @@ -0,0 +1,41 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +vmap altera_iopll_170 ./work/ + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_iopll_170/sim/ip_arria10_e1sg_pll_clk25_altera_iopll_170_7lq52ua.vo" -work altera_iopll_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_iopll_170/sim/ip_arria10_e1sg_pll_clk125_altera_iopll_170_3a4ewza.vo" -work altera_iopll_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vlog "$IP_DIR/../altera_iopll_170/sim/ip_arria10_e1sg_pll_clk200_altera_iopll_170_bqwoevq.vo" -work altera_iopll_170 + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..d75309def40467ad136aec37d367b6a3c33688eb --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altera_iopll_170 +hdl_library_clause_name = altera_iopll_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..4a89f0d42387b190ff75804bb93f3d4d8f1d906d --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl @@ -0,0 +1,37 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_ip_col_if_170 ./work/ + + vlog "$IP_DIR/../altera_ip_col_if_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_ip_col_if_170_bnb3mmy.v" -work altera_ip_col_if_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..540bef90d6fe2a9db186358879b1354089256691 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_ip_col_if_170 +hdl_library_clause_name = altera_ip_col_if_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..827770ab5410a4b9ce90c1685f98731eaf76311b --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl @@ -0,0 +1,45 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_jtag_dc_streaming_170 ./work/ + vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_jtag_interface.v" -work altera_jtag_dc_streaming_170 + vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_jtag_dc_streaming.v" -work altera_jtag_dc_streaming_170 + vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_jtag_sld_node.v" -work altera_jtag_dc_streaming_170 + vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_jtag_streaming.v" -work altera_jtag_dc_streaming_170 + vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_clock_crosser.v" -work altera_jtag_dc_streaming_170 + vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_std_synchronizer_nocut.v" -work altera_jtag_dc_streaming_170 + vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_pipeline_base.v" -work altera_jtag_dc_streaming_170 + vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_idle_remover.v" -work altera_jtag_dc_streaming_170 + vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_idle_inserter.v" -work altera_jtag_dc_streaming_170 + vlog -sv "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_pipeline_stage.sv" -work altera_jtag_dc_streaming_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..58633386cd5c011ca51c43a592fc2c92e01a7cbb --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_jtag_dc_streaming_170 +hdl_library_clause_name = altera_jtag_dc_streaming_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..9c08ddd0b0b8dc2753ce3e774680fda0f5b231d1 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl @@ -0,0 +1,34 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" +vmap altera_lvds_170 ./work/ + vcom "$IP_DIR/../altera_lvds_170/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_170_m5pqrlq.vhd" -work altera_lvds_170 + vcom "$IP_DIR/../altera_lvds_170/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_170_o42lhkq.vhd" -work altera_lvds_170 + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..5aafdf155e3fe629c525162641215ac1638449ad --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altera_lvds_170 +hdl_library_clause_name = altera_lvds_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = ip_arria10_e1sg_altera_lvds_core20_170 +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..d6fd3f2e14567879a72f9fe7bc969c1f0c239f16 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl @@ -0,0 +1,39 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" +vmap altera_lvds_core20_170 ./work/ + + + vlog -sv "$IP_DIR/../altera_lvds_core20_170/sim/mentor/altera_lvds_core20.sv" -work altera_lvds_core20_170 + vlog "$IP_DIR/../altera_lvds_core20_170/sim/mentor/altera_lvds_core20_pll.v" -work altera_lvds_core20_170 + vcom "$IP_DIR/../altera_lvds_core20_170/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_core20_170_qagiwoa.vhd" -work altera_lvds_core20_170 + vlog -sv "$IP_DIR/../altera_lvds_core20_170/sim/mentor/altera_lvds_core20.sv" -work altera_lvds_core20_170 + vlog "$IP_DIR/../altera_lvds_core20_170/sim/mentor/altera_lvds_core20_pll.v" -work altera_lvds_core20_170 + vcom "$IP_DIR/../altera_lvds_core20_170/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_core20_170_o4ldvbi.vhd" -work altera_lvds_core20_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..a72e4c297c86cd067dce135fa623c5eb45c8e1ba --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altera_lvds_core20_170 +hdl_library_clause_name = altera_lvds_core20_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..70d87057853e17c9886dbca92e4558b716acc0b6 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl @@ -0,0 +1,36 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_merlin_master_translator_170 ./work/ + + vlog -sv "$IP_DIR/../altera_merlin_master_translator_170/sim/altera_merlin_master_translator.sv" -work altera_merlin_master_translator_170 + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..1f2a23c00eaea07409b423479743715cd60d1ff1 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_merlin_master_translator_170 +hdl_library_clause_name = altera_merlin_master_translator_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..567760279868e9026fcf36f79a9c420434b47708 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl @@ -0,0 +1,36 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_merlin_slave_translator_170 ./work/ + + vlog -sv "$IP_DIR/../altera_merlin_slave_translator_170/sim/mentor/altera_merlin_slave_translator.sv" -work altera_merlin_slave_translator_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..ef9b259c5ff1a3aa044ac8c6b3e8eeb37fa88283 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_merlin_slave_translator_170 +hdl_library_clause_name = altera_merlin_slave_translator_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..a2cfe1b1c15db6e782ce50ffc26a97bdf61f6cce --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl @@ -0,0 +1,46 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# +vmap altera_mm_interconnect_170 ./work/ + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_3gbam2q.vhd" -work altera_mm_interconnect_170 + vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170 + vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_lcqbbfq.vhd" -work altera_mm_interconnect_170 + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170 + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..f08778a0208c0c258c17e2375d8699df74d3c166 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_mm_interconnect_170 +hdl_library_clause_name = altera_mm_interconnect_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = ip_arria10_e1sg_altera_merlin_master_translator_170 ip_arria10_e1sg_altera_merlin_slave_translator_170 +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..57ddfbe2f490dfa51e418e0228fbed40f18428d8 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl @@ -0,0 +1,37 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_remote_update_170 ./work/ + + vcom "$IP_DIR/../altera_remote_update_170/sim/ip_arria10_e1sg_remote_update_altera_remote_update_170_hsvaqga.vhd" -work altera_remote_update_170 + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..fed8c35d6ca2b458e6af524df5870e7bad3a81d3 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/hdllib.cfg @@ -0,0 +1,15 @@ +hdl_lib_name = ip_arria10_e1sg_altera_remote_update_170 +hdl_library_clause_name = altera_remote_update_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = ip_arria10_e1sg_altera_remote_update_core_170 +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..f9ee62340106fdf6b6f698c583a8115b773faa25 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl @@ -0,0 +1,40 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + + +vmap altera_remote_update_core_170 ./work/ + + + vlog "$IP_DIR/../altera_remote_update_core_170/sim/mentor/altera_remote_update_core.sv" -work altera_remote_update_core_170 + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..ef449921eb509296d6c7b5cda971164613d316fb --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/hdllib.cfg @@ -0,0 +1,12 @@ +hdl_lib_name = ip_arria10_e1sg_altera_remote_update_core_170 +hdl_library_clause_name = altera_remote_update_core_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..2ec6c185829409452174ebab6558eacc7aaef3a6 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl @@ -0,0 +1,37 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_reset_controller_170 ./work/ + + vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_170 + vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..2bf3f307467bf0b53b5663fe7a044f50a215b74b --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_reset_controller_170 +hdl_library_clause_name = altera_reset_controller_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..fca02130c30b522bc09f6eddaef10189c44efc90 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl @@ -0,0 +1,55 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_common_sv_packages ./work/ +vmap altera_xcvr_atx_pll_a10_170 ./work/ + + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/mentor/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/mentor/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/mentor/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/a10_avmm_h.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/alt_xcvr_atx_pll_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/a10_xcvr_atx_pll.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/alt_xcvr_pll_embedded_debug.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/alt_xcvr_pll_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/mentor/alt_xcvr_atx_pll_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/mentor/a10_xcvr_atx_pll.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/mentor/alt_xcvr_pll_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_170_3gt7q7a.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/alt_xcvr_atx_pll_rcfg_opt_logic_3gt7q7a.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170 + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..db46806823bd89d278e67d87196878b91c1c3dbc --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altera_xcvr_atx_pll_a10_170 +hdl_library_clause_name = altera_xcvr_atx_pll_a10_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..8ea648de469ed6c222dde0217e63fef541ea9c53 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl @@ -0,0 +1,50 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_xcvr_fpll_a10_170 ./work/ + +#pll_xgmii_mac_clocks + vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/twentynm_xcvr_avmm.sv" -work altera_xcvr_fpll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/twentynm_xcvr_avmm.sv" -work altera_xcvr_fpll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_resync.sv" -work altera_xcvr_fpll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/alt_xcvr_resync.sv" -work altera_xcvr_fpll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/altera_xcvr_fpll_a10.sv" -work altera_xcvr_fpll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/altera_xcvr_fpll_a10.sv" -work altera_xcvr_fpll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/a10_avmm_h.sv" -work altera_xcvr_fpll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_native_avmm_nf.sv" -work altera_xcvr_fpll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_pll_embedded_debug.sv" -work altera_xcvr_fpll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_pll_avmm_csr.sv" -work altera_xcvr_fpll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -work altera_xcvr_fpll_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/alt_xcvr_pll_avmm_csr.sv" -work altera_xcvr_fpll_a10_170 + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..fbcddbb6b9e60f55b5c5c9ec042ab2316c3e83de --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = ip_arria10_e1sg_altera_xcvr_fpll_a10_170 +hdl_library_clause_name = altera_xcvr_fpll_a10_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..25fed105f6248b36ddcdb4477b99c9deeb6832f0 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl @@ -0,0 +1,98 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + +vmap altera_xcvr_native_a10_170 ./work/ +vmap altera_common_sv_packages ./work/ + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +# common dependencies + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/a10_avmm_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_pipe_retry.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_prbs_accum.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_odi_accel.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_pcie_dfe_params_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_commands_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_functions_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_program.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_cpu.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_master.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_pcie_dfe_ip.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/reconfig/altera_xcvr_native_a10_reconfig_parameters.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + +# phy_10gbase_r_48 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_170_otmjdta.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_otmjdta.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + +# phy_10gbase_r_24 +#set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generated/sim" + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_170_edf7tdy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_edf7tdy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + +# phy_10gbase_r_12 +#set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generated/sim" + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_170_uyp7wca.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_uyp7wca.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + +# phy_10gbase_r_4 +#set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generated/sim" + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_170_5bntvuq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_5bntvuq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + +# phy_10gbase_r_3 +#set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generated/sim" + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_170_exiqljq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_exiqljq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + +# phy_10gbase_r +#set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generated/sim" + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_170_s7t4kxy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_s7t4kxy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + +# tse_sgmii_gx +#set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim" + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_xcvr_native_a10_170_q6y47ey.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 + vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_q6y47ey.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170 diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..96fde27cdff0dbd5fc1cca407adf30a44e89a767 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_xcvr_native_a10_170 +hdl_library_clause_name = altera_xcvr_native_a10_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..d6ceb0f5c9c6c05adee3d2488f2fae5cde015c18 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl @@ -0,0 +1,44 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap altera_xcvr_reset_control_170 ./work/ + + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/altera_xcvr_functions.sv" -work altera_xcvr_reset_control_170 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/altera_xcvr_functions.sv" -work altera_xcvr_reset_control_170 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/alt_xcvr_resync.sv" -work altera_xcvr_reset_control_170 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/alt_xcvr_resync.sv" -work altera_xcvr_reset_control_170 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/altera_xcvr_reset_control.sv" -work altera_xcvr_reset_control_170 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/alt_xcvr_reset_counter.sv" -work altera_xcvr_reset_control_170 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/altera_xcvr_reset_control.sv" -work altera_xcvr_reset_control_170 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/alt_xcvr_reset_counter.sv" -work altera_xcvr_reset_control_170 + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..eedb9c51bd0e8f966791754164558e028dcf1426 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_altera_xcvr_reset_control_170 +hdl_library_clause_name = altera_xcvr_reset_control_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..c5e00ff4d4048e4a6b374099d3da0405dbb3c1da --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl @@ -0,0 +1,40 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap channel_adapter_170 ./work/ + + vlog -sv "$IP_DIR/../channel_adapter_170/sim/ip_arria10_e1sg_ddr4_8g_1600_channel_adapter_170_bsi6toa.sv" -work channel_adapter_170 + vlog -sv "$IP_DIR/../channel_adapter_170/sim/ip_arria10_e1sg_ddr4_8g_1600_channel_adapter_170_xbvi4ny.sv" -work channel_adapter_170 + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..eebe788ab1ab82f06d0bb80dc1c65c2f1ed59caa --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_channel_adapter_170 +hdl_library_clause_name = channel_adapter_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl + + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..c96a664efa58ad5ccf52c66b95f87220b93d9a87 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl @@ -0,0 +1,39 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2017 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +#vlib ./work/ ;# Assume library work already exist +# + + +set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim" + +vmap timing_adapter_170 ./work/ + + vlog -sv "$IP_DIR/../timing_adapter_170/sim/ip_arria10_e1sg_ddr4_8g_1600_timing_adapter_170_osazali.sv" -work timing_adapter_170 + + diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..4633fb177d9ecea8e48d40cf06f04a3cb6aad243 --- /dev/null +++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e1sg_timing_adapter_170 +hdl_library_clause_name = timing_adapter_170 +hdl_lib_uses_synth = +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + +test_bench_files = + +[modelsim_project_file] +modelsim_compile_ip_files = + $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl + + +