edited hdllib.cfg and the vhd files of several technology libraries to

use the correct library names in the .../technology/ip_arria10_e1sg
folder

libraries/technology/pll/tech_pll_clk200.vhd

@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
 LIBRARY ip_stratixiv_pll_lib;
 LIBRARY ip_arria10_pll_clk200_altera_iopll_150;
 LIBRARY ip_arria10_e3sge3_pll_clk200_altera_iopll_151;
-LIBRARY ip_arria10_e1sg_pll_clk200_altera_iopll_151;
+LIBRARY ip_arria10_e1sg_pll_clk200_altera_iopll_170;
 
 ENTITY tech_pll_clk200 IS
   GENERIC (

libraries/technology/pll/tech_pll_clk25.vhd

@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
 LIBRARY ip_arria10_pll_clk25_altera_iopll_150;
 LIBRARY ip_stratixiv_pll_clk25_lib;
 LIBRARY ip_arria10_e3sge3_pll_clk25_altera_iopll_151;
-LIBRARY ip_arria10_e1sg_pll_clk25_altera_iopll_151;
+LIBRARY ip_arria10_e1sg_pll_clk25_altera_iopll_170;
 
 ENTITY tech_pll_clk25 IS
   GENERIC (

libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd

@@ -43,7 +43,7 @@ USE common_lib.common_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_150;
 LIBRARY ip_arria10_e3sge3_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151;
-LIBRARY ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151;
+LIBRARY ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_170;
 
 ENTITY tech_pll_xgmii_mac_clocks IS
   GENERIC (

libraries/technology/tse/hdllib.cfg

@@ -14,8 +14,8 @@ hdl_lib_disclose_library_clause_names =
     ip_arria10_tse_sgmii_gx           ip_arria10_tse_sgmii_gx_altera_eth_tse_150
     ip_arria10_e3sge3_tse_sgmii_lvds  ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_151
     ip_arria10_e3sge3_tse_sgmii_gx    ip_arria10_e3sge3_tse_sgmii_gx_altera_eth_tse_151
-    ip_arria10_e1sg_tse_sgmii_lvds    ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_151
-    ip_arria10_e1sg_tse_sgmii_gx      ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_151
+    ip_arria10_e1sg_tse_sgmii_lvds    ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_170
+    ip_arria10_e1sg_tse_sgmii_gx      ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_170
 
 synth_files =
     tech_tse_component_pkg.vhd

libraries/technology/tse/tech_tse.vhd

@@ -137,16 +137,16 @@ BEGIN
   END GENERATE;
 
   gen_sim_tse : IF c_use_sim_model=TRUE GENERATE
-    u_sim_tse : ENTITY work.sim_tse
-    GENERIC MAP (g_sim_tx, g_sim_rx)
-    PORT MAP (mm_rst, mm_clk, eth_clk, tx_snk_clk, rx_src_clk,
-              mm_sla_in, mm_sla_out,
-              tx_snk_in, tx_snk_out,
-              tx_mac_in, tx_mac_out,
-              rx_src_in, rx_src_out,
-              rx_mac_out,
-              eth_txp, eth_rxp,
-              tse_led);
+--    u_sim_tse : ENTITY work.sim_tse
+--    GENERIC MAP (g_sim_tx, g_sim_rx)
+--    PORT MAP (mm_rst, mm_clk, eth_clk, tx_snk_clk, rx_src_clk,
+--              mm_sla_in, mm_sla_out,
+--              tx_snk_in, tx_snk_out,
+--              tx_mac_in, tx_mac_out,
+--              rx_src_in, rx_src_out,
+--              rx_mac_out,
+--              eth_txp, eth_rxp,
+--              tse_led);
   END GENERATE;
   
 END ARCHITECTURE;

libraries/technology/tse/tech_tse_arria10_e1sg.vhd

@@ -28,8 +28,8 @@ USE common_lib.common_mem_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_151;
-LIBRARY ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_151;
+LIBRARY ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_170;
+LIBRARY ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_170;
 
 ENTITY tech_tse_arria10_e1sg IS
   GENERIC (