From dccde9ef535b89ff6e279f7122dd45c7a98745c3 Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Tue, 25 Jul 2017 09:25:29 +0000
Subject: [PATCH] edited hdllib.cfg and the vhd files of several technology
libraries to use the correct library names in the
.../technology/ip_arria10_e1sg folder
---
libraries/technology/10gbase_r/hdllib.cfg | 18 +++++++--------
.../10gbase_r/tech_10gbase_r_arria10_e1sg.vhd | 22 +++++++++----------
libraries/technology/clkbuf/hdllib.cfg | 2 +-
libraries/technology/clkbuf/tech_clkbuf.vhd | 2 +-
libraries/technology/ddr/hdllib.cfg | 8 +++----
.../technology/ddr/tech_ddr_arria10_e1sg.vhd | 8 +++----
libraries/technology/flash/hdllib.cfg | 4 ++--
.../flash/tech_flash_asmi_parallel.vhd | 2 +-
.../flash/tech_flash_remote_update.vhd | 2 +-
.../technology/fpga_temp_sens/hdllib.cfg | 2 +-
.../fpga_temp_sens/tech_fpga_temp_sens.vhd | 2 +-
.../technology/fpga_voltage_sens/hdllib.cfg | 2 +-
.../tech_fpga_voltage_sens.vhd | 2 +-
.../technology/fractional_pll/hdllib.cfg | 4 ++--
.../tech_fractional_pll_clk125.vhd | 2 +-
.../tech_fractional_pll_clk200.vhd | 2 +-
libraries/technology/mac_10g/hdllib.cfg | 2 +-
.../mac_10g/tech_mac_10g_arria10_e1sg.vhd | 2 +-
libraries/technology/pll/hdllib.cfg | 8 +++----
libraries/technology/pll/tech_pll_clk125.vhd | 2 +-
libraries/technology/pll/tech_pll_clk200.vhd | 2 +-
libraries/technology/pll/tech_pll_clk25.vhd | 2 +-
.../pll/tech_pll_xgmii_mac_clocks.vhd | 2 +-
libraries/technology/tse/hdllib.cfg | 4 ++--
libraries/technology/tse/tech_tse.vhd | 20 ++++++++---------
.../technology/tse/tech_tse_arria10_e1sg.vhd | 4 ++--
26 files changed, 66 insertions(+), 66 deletions(-)
diff --git a/libraries/technology/10gbase_r/hdllib.cfg b/libraries/technology/10gbase_r/hdllib.cfg
index df262a14c6..be50155fb5 100644
--- a/libraries/technology/10gbase_r/hdllib.cfg
+++ b/libraries/technology/10gbase_r/hdllib.cfg
@@ -38,15 +38,15 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e3sge3_transceiver_reset_controller_24 ip_arria10_e3sge3_transceiver_reset_controller_24_altera_xcvr_reset_control_151
ip_arria10_e3sge3_transceiver_reset_controller_48 ip_arria10_e3sge3_transceiver_reset_controller_48_altera_xcvr_reset_control_151
ip_arria10_e1sg_phy_10gbase_r ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_151
- ip_arria10_e1sg_phy_10gbase_r_4 ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_151
- ip_arria10_e1sg_phy_10gbase_r_12 ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_151
- ip_arria10_e1sg_phy_10gbase_r_24 ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_151
- ip_arria10_e1sg_phy_10gbase_r_48 ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_151
- ip_arria10_e1sg_transceiver_pll_10g ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151
- ip_arria10_e1sg_transceiver_reset_controller_1 ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_151
- ip_arria10_e1sg_transceiver_reset_controller_4 ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_151
- ip_arria10_e1sg_transceiver_reset_controller_12 ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_151
- ip_arria10_e1sg_transceiver_reset_controller_24 ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_151
+ ip_arria10_e1sg_phy_10gbase_r_4 ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_170
+ ip_arria10_e1sg_phy_10gbase_r_12 ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_170
+ ip_arria10_e1sg_phy_10gbase_r_24 ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_170
+ ip_arria10_e1sg_phy_10gbase_r_48 ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_170
+ ip_arria10_e1sg_transceiver_pll_10g ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_170
+ ip_arria10_e1sg_transceiver_reset_controller_1 ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_170
+ ip_arria10_e1sg_transceiver_reset_controller_4 ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_170
+ ip_arria10_e1sg_transceiver_reset_controller_12 ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_170
+ ip_arria10_e1sg_transceiver_reset_controller_24 ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_170
synth_files =
sim_10gbase_r.vhd
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
index 32171c4708..4e61f6475d 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
@@ -21,17 +21,17 @@
--------------------------------------------------------------------------------
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_151;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_151;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_151;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_151;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_151;
-LIBRARY ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_151;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_151;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_151;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_151;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_48_altera_xcvr_reset_control_151;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_170;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_170;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_170;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_170;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_170;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_48_altera_xcvr_reset_control_170;
LIBRARY IEEE, tech_pll_lib, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
diff --git a/libraries/technology/clkbuf/hdllib.cfg b/libraries/technology/clkbuf/hdllib.cfg
index ea613dc680..64d48639a1 100644
--- a/libraries/technology/clkbuf/hdllib.cfg
+++ b/libraries/technology/clkbuf/hdllib.cfg
@@ -7,7 +7,7 @@ hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_arria10_clkbuf_global ip_arria10_clkbuf_global_altclkctrl_150
ip_arria10_e3sge3_clkbuf_global ip_arria10_e3sge3_clkbuf_global_altclkctrl_151
- ip_arria10_e1sg_clkbuf_global ip_arria10_e1sg_clkbuf_global_altclkctrl_151
+ ip_arria10_e1sg_clkbuf_global ip_arria10_e1sg_clkbuf_global_altclkctrl_170
synth_files =
tech_clkbuf_component_pkg.vhd
diff --git a/libraries/technology/clkbuf/tech_clkbuf.vhd b/libraries/technology/clkbuf/tech_clkbuf.vhd
index ef2500794b..b55e51bdde 100644
--- a/libraries/technology/clkbuf/tech_clkbuf.vhd
+++ b/libraries/technology/clkbuf/tech_clkbuf.vhd
@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_clkbuf_global_altclkctrl_150;
LIBRARY ip_arria10_e3sge3_clkbuf_global_altclkctrl_151;
-LIBRARY ip_arria10_e1sg_clkbuf_global_altclkctrl_151;
+LIBRARY ip_arria10_e1sg_clkbuf_global_altclkctrl_170;
ENTITY tech_clkbuf IS
GENERIC (
diff --git a/libraries/technology/ddr/hdllib.cfg b/libraries/technology/ddr/hdllib.cfg
index 08c18b3366..f26d433199 100644
--- a/libraries/technology/ddr/hdllib.cfg
+++ b/libraries/technology/ddr/hdllib.cfg
@@ -33,10 +33,10 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e3sge3_ddr4_8g_1600 ip_arria10_e3sge3_ddr4_8g_1600_altera_emif_151
ip_arria10_e3sge3_ddr4_4g_2000 ip_arria10_e3sge3_ddr4_4g_2000_altera_emif_151
ip_arria10_e3sge3_ddr4_8g_2400 ip_arria10_e3sge3_ddr4_8g_2400_altera_emif_151
- ip_arria10_e1sg_ddr4_4g_1600 ip_arria10_e1sg_ddr4_4g_1600_altera_emif_151
- ip_arria10_e1sg_ddr4_8g_1600 ip_arria10_e1sg_ddr4_8g_1600_altera_emif_151
- ip_arria10_e1sg_ddr4_4g_2000 ip_arria10_e1sg_ddr4_4g_2000_altera_emif_151
- ip_arria10_e1sg_ddr4_8g_2400 ip_arria10_e1sg_ddr4_8g_2400_altera_emif_151
+ ip_arria10_e1sg_ddr4_4g_1600 ip_arria10_e1sg_ddr4_4g_1600_altera_emif_170
+ ip_arria10_e1sg_ddr4_8g_1600 ip_arria10_e1sg_ddr4_8g_1600_altera_emif_170
+ ip_arria10_e1sg_ddr4_4g_2000 ip_arria10_e1sg_ddr4_4g_2000_altera_emif_170
+ ip_arria10_e1sg_ddr4_8g_2400 ip_arria10_e1sg_ddr4_8g_2400_altera_emif_170
ip_stratixiv_ddr3_mem_model ip_stratixiv_ddr3_mem_model_lib
ip_arria10_ddr4_mem_model_141 ip_arria10_ddr4_mem_model_141
diff --git a/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd b/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd
index 49f45f3b2e..6564425f2d 100644
--- a/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd
+++ b/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd
@@ -34,10 +34,10 @@
-- DDR interface monitoring purposes.
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_ddr4_4g_1600_altera_emif_151;
-LIBRARY ip_arria10_e1sg_ddr4_8g_1600_altera_emif_151;
-LIBRARY ip_arria10_e1sg_ddr4_4g_2000_altera_emif_151;
-LIBRARY ip_arria10_e1sg_ddr4_8g_2400_altera_emif_151;
+LIBRARY ip_arria10_e1sg_ddr4_4g_1600_altera_emif_170;
+LIBRARY ip_arria10_e1sg_ddr4_8g_1600_altera_emif_170;
+LIBRARY ip_arria10_e1sg_ddr4_4g_2000_altera_emif_170;
+LIBRARY ip_arria10_e1sg_ddr4_8g_2400_altera_emif_170;
LIBRARY IEEE, technology_lib, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
diff --git a/libraries/technology/flash/hdllib.cfg b/libraries/technology/flash/hdllib.cfg
index 4424eaa642..e62927b991 100644
--- a/libraries/technology/flash/hdllib.cfg
+++ b/libraries/technology/flash/hdllib.cfg
@@ -16,8 +16,8 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_remote_update ip_arria10_remote_update_altera_remote_update_150
ip_arria10_e3sge3_asmi_parallel ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151
ip_arria10_e3sge3_remote_update ip_arria10_e3sge3_remote_update_altera_remote_update_151
- ip_arria10_e1sg_asmi_parallel ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_151
- ip_arria10_e1sg_remote_update ip_arria10_e1sg_remote_update_altera_remote_update_151
+ ip_arria10_e1sg_asmi_parallel ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_170
+ ip_arria10_e1sg_remote_update ip_arria10_e1sg_remote_update_altera_remote_update_170
synth_files =
tech_flash_component_pkg.vhd
diff --git a/libraries/technology/flash/tech_flash_asmi_parallel.vhd b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
index e6bb150696..37d20af1f2 100644
--- a/libraries/technology/flash/tech_flash_asmi_parallel.vhd
+++ b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
@@ -31,7 +31,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_flash_lib;
LIBRARY ip_arria10_asmi_parallel_altera_asmi_parallel_150;
LIBRARY ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151;
-LIBRARY ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_151;
+LIBRARY ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_170;
ENTITY tech_flash_asmi_parallel IS
GENERIC (
diff --git a/libraries/technology/flash/tech_flash_remote_update.vhd b/libraries/technology/flash/tech_flash_remote_update.vhd
index 3d387c1e54..f0949faec2 100644
--- a/libraries/technology/flash/tech_flash_remote_update.vhd
+++ b/libraries/technology/flash/tech_flash_remote_update.vhd
@@ -31,7 +31,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_flash_lib;
LIBRARY ip_arria10_remote_update_altera_remote_update_150;
LIBRARY ip_arria10_e3sge3_remote_update_altera_remote_update_151;
-LIBRARY ip_arria10_e1sg_remote_update_altera_remote_update_151;
+LIBRARY ip_arria10_e1sg_remote_update_altera_remote_update_170;
ENTITY tech_flash_remote_update IS
GENERIC (
diff --git a/libraries/technology/fpga_temp_sens/hdllib.cfg b/libraries/technology/fpga_temp_sens/hdllib.cfg
index 22f6125780..2e5124c781 100644
--- a/libraries/technology/fpga_temp_sens/hdllib.cfg
+++ b/libraries/technology/fpga_temp_sens/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_arria10_temp_sense ip_arria10_temp_sense_altera_temp_sense_150
ip_arria10_e3sge3_temp_sense ip_arria10_e3sge3_temp_sense_altera_temp_sense_151
- ip_arria10_e1sg_temp_sense ip_arria10_e1sg_temp_sense_altera_temp_sense_151
+ ip_arria10_e1sg_temp_sense ip_arria10_e1sg_temp_sense_altera_temp_sense_170
synth_files =
tech_fpga_temp_sens_component_pkg.vhd
diff --git a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
index ea06ed0820..65a773084a 100644
--- a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
+++ b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_temp_sense_altera_temp_sense_150;
LIBRARY ip_arria10_e3sge3_temp_sense_altera_temp_sense_151;
-LIBRARY ip_arria10_e1sg_temp_sense_altera_temp_sense_151;
+LIBRARY ip_arria10_e1sg_temp_sense_altera_temp_sense_170;
ENTITY tech_fpga_temp_sens IS
diff --git a/libraries/technology/fpga_voltage_sens/hdllib.cfg b/libraries/technology/fpga_voltage_sens/hdllib.cfg
index 46c474c6d3..03aaf853ed 100644
--- a/libraries/technology/fpga_voltage_sens/hdllib.cfg
+++ b/libraries/technology/fpga_voltage_sens/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_arria10_voltage_sense ip_arria10_voltage_sense_altera_voltage_sense_150
ip_arria10_e3sge3_voltage_sense ip_arria10_e3sge3_voltage_sense_altera_voltage_sense_151
- ip_arria10_e1sg_voltage_sense ip_arria10_e1sg_voltage_sense_altera_voltage_sense_151
+ ip_arria10_e1sg_voltage_sense ip_arria10_e1sg_voltage_sense_altera_voltage_sense_170
synth_files =
tech_fpga_voltage_sens_component_pkg.vhd
diff --git a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
index 8ddaaff0b2..bc66f172fd 100644
--- a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
+++ b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_voltage_sense_altera_voltage_sense_150;
LIBRARY ip_arria10_e3sge3_voltage_sense_altera_voltage_sense_151;
-LIBRARY ip_arria10_e1sg_voltage_sense_altera_voltage_sense_151;
+LIBRARY ip_arria10_e1sg_voltage_sense_altera_voltage_sense_170;
ENTITY tech_fpga_voltage_sens IS
diff --git a/libraries/technology/fractional_pll/hdllib.cfg b/libraries/technology/fractional_pll/hdllib.cfg
index aa107e1a63..3c2cf1abd6 100644
--- a/libraries/technology/fractional_pll/hdllib.cfg
+++ b/libraries/technology/fractional_pll/hdllib.cfg
@@ -10,8 +10,8 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_fractional_pll_clk125 ip_arria10_fractional_pll_clk125_altera_xcvr_fpll_a10_150
ip_arria10_e3sge3_fractional_pll_clk200 ip_arria10_e3sge3_fractional_pll_clk200_altera_xcvr_fpll_a10_151
ip_arria10_e3sge3_fractional_pll_clk125 ip_arria10_e3sge3_fractional_pll_clk125_altera_xcvr_fpll_a10_151
- ip_arria10_e1sg_fractional_pll_clk200 ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_151
- ip_arria10_e1sg_fractional_pll_clk125 ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_151
+ ip_arria10_e1sg_fractional_pll_clk200 ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_170
+ ip_arria10_e1sg_fractional_pll_clk125 ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_170
synth_files =
tech_fractional_pll_component_pkg.vhd
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
index db1911d583..cc8f297c07 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_fractional_pll_clk125_altera_xcvr_fpll_a10_150;
LIBRARY ip_arria10_e3sge3_fractional_pll_clk125_altera_xcvr_fpll_a10_151;
-LIBRARY ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_151;
+LIBRARY ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_170;
ENTITY tech_fractional_pll_clk125 IS
GENERIC (
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
index 5114716224..f30733508e 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_fractional_pll_clk200_altera_xcvr_fpll_a10_150;
LIBRARY ip_arria10_e3sge3_fractional_pll_clk200_altera_xcvr_fpll_a10_151;
-LIBRARY ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_151;
+LIBRARY ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_170;
ENTITY tech_fractional_pll_clk200 IS
GENERIC (
diff --git a/libraries/technology/mac_10g/hdllib.cfg b/libraries/technology/mac_10g/hdllib.cfg
index c81aa3c753..c73c25d07a 100644
--- a/libraries/technology/mac_10g/hdllib.cfg
+++ b/libraries/technology/mac_10g/hdllib.cfg
@@ -8,7 +8,7 @@ hdl_lib_disclose_library_clause_names =
ip_stratixiv_mac_10g ip_stratixiv_mac_10g_lib
ip_arria10_mac_10g ip_arria10_mac_10g_alt_em10g32_150
ip_arria10_e3sge3_mac_10g ip_arria10_e3sge3_mac_10g_alt_em10g32_151
- ip_arria10_e1sg_mac_10g ip_arria10_e1sg_mac_10g_alt_em10g32_151
+ ip_arria10_e1sg_mac_10g ip_arria10_e1sg_mac_10g_alt_em10g32_170
synth_files =
tech_mac_10g_component_pkg.vhd
diff --git a/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd b/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd
index e01af57e01..c41aa27748 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd
@@ -21,7 +21,7 @@
--------------------------------------------------------------------------------
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_mac_10g_alt_em10g32_151;
+LIBRARY ip_arria10_e1sg_mac_10g_alt_em10g32_170;
LIBRARY IEEE, technology_lib, common_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
diff --git a/libraries/technology/pll/hdllib.cfg b/libraries/technology/pll/hdllib.cfg
index 7b5ef9392e..4b047fa7c0 100644
--- a/libraries/technology/pll/hdllib.cfg
+++ b/libraries/technology/pll/hdllib.cfg
@@ -18,10 +18,10 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e3sge3_pll_clk25 ip_arria10_e3sge3_pll_clk25_altera_iopll_151
ip_arria10_e3sge3_pll_clk125 ip_arria10_e3sge3_pll_clk125_altera_iopll_151
ip_arria10_e3sge3_pll_xgmii_mac_clocks ip_arria10_e3sge3_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151
- ip_arria10_e1sg_pll_clk200 ip_arria10_e1sg_pll_clk200_altera_iopll_151
- ip_arria10_e1sg_pll_clk25 ip_arria10_e1sg_pll_clk25_altera_iopll_151
- ip_arria10_e1sg_pll_clk125 ip_arria10_e1sg_pll_clk125_altera_iopll_151
- ip_arria10_e1sg_pll_xgmii_mac_clocks ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151
+ ip_arria10_e1sg_pll_clk200 ip_arria10_e1sg_pll_clk200_altera_iopll_170
+ ip_arria10_e1sg_pll_clk25 ip_arria10_e1sg_pll_clk25_altera_iopll_170
+ ip_arria10_e1sg_pll_clk125 ip_arria10_e1sg_pll_clk125_altera_iopll_170
+ ip_arria10_e1sg_pll_xgmii_mac_clocks ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_170
synth_files =
tech_pll_component_pkg.vhd
diff --git a/libraries/technology/pll/tech_pll_clk125.vhd b/libraries/technology/pll/tech_pll_clk125.vhd
index dc5cd91e9f..5cdbbb6be1 100644
--- a/libraries/technology/pll/tech_pll_clk125.vhd
+++ b/libraries/technology/pll/tech_pll_clk125.vhd
@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_pll_clk125_altera_iopll_150;
LIBRARY ip_arria10_e3sge3_pll_clk125_altera_iopll_151;
-LIBRARY ip_arria10_e1sg_pll_clk125_altera_iopll_151;
+LIBRARY ip_arria10_e1sg_pll_clk125_altera_iopll_170;
ENTITY tech_pll_clk125 IS
GENERIC (
diff --git a/libraries/technology/pll/tech_pll_clk200.vhd b/libraries/technology/pll/tech_pll_clk200.vhd
index 2e9f9ed5e7..4eefc35b6d 100644
--- a/libraries/technology/pll/tech_pll_clk200.vhd
+++ b/libraries/technology/pll/tech_pll_clk200.vhd
@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_pll_lib;
LIBRARY ip_arria10_pll_clk200_altera_iopll_150;
LIBRARY ip_arria10_e3sge3_pll_clk200_altera_iopll_151;
-LIBRARY ip_arria10_e1sg_pll_clk200_altera_iopll_151;
+LIBRARY ip_arria10_e1sg_pll_clk200_altera_iopll_170;
ENTITY tech_pll_clk200 IS
GENERIC (
diff --git a/libraries/technology/pll/tech_pll_clk25.vhd b/libraries/technology/pll/tech_pll_clk25.vhd
index e02409a04d..2521432735 100644
--- a/libraries/technology/pll/tech_pll_clk25.vhd
+++ b/libraries/technology/pll/tech_pll_clk25.vhd
@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_pll_clk25_altera_iopll_150;
LIBRARY ip_stratixiv_pll_clk25_lib;
LIBRARY ip_arria10_e3sge3_pll_clk25_altera_iopll_151;
-LIBRARY ip_arria10_e1sg_pll_clk25_altera_iopll_151;
+LIBRARY ip_arria10_e1sg_pll_clk25_altera_iopll_170;
ENTITY tech_pll_clk25 IS
GENERIC (
diff --git a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
index 731530e585..28f1fa3a1e 100644
--- a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
+++ b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
@@ -43,7 +43,7 @@ USE common_lib.common_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_150;
LIBRARY ip_arria10_e3sge3_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151;
-LIBRARY ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151;
+LIBRARY ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_170;
ENTITY tech_pll_xgmii_mac_clocks IS
GENERIC (
diff --git a/libraries/technology/tse/hdllib.cfg b/libraries/technology/tse/hdllib.cfg
index e9dc7a5dab..2198a8e398 100644
--- a/libraries/technology/tse/hdllib.cfg
+++ b/libraries/technology/tse/hdllib.cfg
@@ -14,8 +14,8 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_tse_sgmii_gx ip_arria10_tse_sgmii_gx_altera_eth_tse_150
ip_arria10_e3sge3_tse_sgmii_lvds ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_151
ip_arria10_e3sge3_tse_sgmii_gx ip_arria10_e3sge3_tse_sgmii_gx_altera_eth_tse_151
- ip_arria10_e1sg_tse_sgmii_lvds ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_151
- ip_arria10_e1sg_tse_sgmii_gx ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_151
+ ip_arria10_e1sg_tse_sgmii_lvds ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_170
+ ip_arria10_e1sg_tse_sgmii_gx ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_170
synth_files =
tech_tse_component_pkg.vhd
diff --git a/libraries/technology/tse/tech_tse.vhd b/libraries/technology/tse/tech_tse.vhd
index 0fdc5bb4c4..967b83e54b 100644
--- a/libraries/technology/tse/tech_tse.vhd
+++ b/libraries/technology/tse/tech_tse.vhd
@@ -137,16 +137,16 @@ BEGIN
END GENERATE;
gen_sim_tse : IF c_use_sim_model=TRUE GENERATE
- u_sim_tse : ENTITY work.sim_tse
- GENERIC MAP (g_sim_tx, g_sim_rx)
- PORT MAP (mm_rst, mm_clk, eth_clk, tx_snk_clk, rx_src_clk,
- mm_sla_in, mm_sla_out,
- tx_snk_in, tx_snk_out,
- tx_mac_in, tx_mac_out,
- rx_src_in, rx_src_out,
- rx_mac_out,
- eth_txp, eth_rxp,
- tse_led);
+-- u_sim_tse : ENTITY work.sim_tse
+-- GENERIC MAP (g_sim_tx, g_sim_rx)
+-- PORT MAP (mm_rst, mm_clk, eth_clk, tx_snk_clk, rx_src_clk,
+-- mm_sla_in, mm_sla_out,
+-- tx_snk_in, tx_snk_out,
+-- tx_mac_in, tx_mac_out,
+-- rx_src_in, rx_src_out,
+-- rx_mac_out,
+-- eth_txp, eth_rxp,
+-- tse_led);
END GENERATE;
END ARCHITECTURE;
diff --git a/libraries/technology/tse/tech_tse_arria10_e1sg.vhd b/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
index 7ff63e2531..4512fe7d9e 100644
--- a/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
+++ b/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
@@ -28,8 +28,8 @@ USE common_lib.common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_151;
-LIBRARY ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_151;
+LIBRARY ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_170;
+LIBRARY ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_170;
ENTITY tech_tse_arria10_e1sg IS
GENERIC (
--
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