diff --git a/libraries/technology/10gbase_r/hdllib.cfg b/libraries/technology/10gbase_r/hdllib.cfg
index df262a14c69d73f9a68b25efaeafa2e15272864c..be50155fb52b399554142de77656b2a3bc663633 100644
--- a/libraries/technology/10gbase_r/hdllib.cfg
+++ b/libraries/technology/10gbase_r/hdllib.cfg
@@ -38,15 +38,15 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e3sge3_transceiver_reset_controller_24 ip_arria10_e3sge3_transceiver_reset_controller_24_altera_xcvr_reset_control_151
ip_arria10_e3sge3_transceiver_reset_controller_48 ip_arria10_e3sge3_transceiver_reset_controller_48_altera_xcvr_reset_control_151
ip_arria10_e1sg_phy_10gbase_r ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_151
- ip_arria10_e1sg_phy_10gbase_r_4 ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_151
- ip_arria10_e1sg_phy_10gbase_r_12 ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_151
- ip_arria10_e1sg_phy_10gbase_r_24 ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_151
- ip_arria10_e1sg_phy_10gbase_r_48 ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_151
- ip_arria10_e1sg_transceiver_pll_10g ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151
- ip_arria10_e1sg_transceiver_reset_controller_1 ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_151
- ip_arria10_e1sg_transceiver_reset_controller_4 ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_151
- ip_arria10_e1sg_transceiver_reset_controller_12 ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_151
- ip_arria10_e1sg_transceiver_reset_controller_24 ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_151
+ ip_arria10_e1sg_phy_10gbase_r_4 ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_170
+ ip_arria10_e1sg_phy_10gbase_r_12 ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_170
+ ip_arria10_e1sg_phy_10gbase_r_24 ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_170
+ ip_arria10_e1sg_phy_10gbase_r_48 ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_170
+ ip_arria10_e1sg_transceiver_pll_10g ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_170
+ ip_arria10_e1sg_transceiver_reset_controller_1 ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_170
+ ip_arria10_e1sg_transceiver_reset_controller_4 ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_170
+ ip_arria10_e1sg_transceiver_reset_controller_12 ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_170
+ ip_arria10_e1sg_transceiver_reset_controller_24 ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_170
synth_files =
sim_10gbase_r.vhd
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
index 32171c4708aed405b13c8cc1194423997b0244c0..4e61f6475d0678e538015f886bafe4e82a5ff2ac 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
@@ -21,17 +21,17 @@
--------------------------------------------------------------------------------
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_151;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_151;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_151;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_151;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_151;
-LIBRARY ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_151;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_151;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_151;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_151;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_48_altera_xcvr_reset_control_151;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_170;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_170;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_170;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_170;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_170;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_48_altera_xcvr_reset_control_170;
LIBRARY IEEE, tech_pll_lib, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
diff --git a/libraries/technology/clkbuf/hdllib.cfg b/libraries/technology/clkbuf/hdllib.cfg
index ea613dc68013e5a93d162879a0777f50bfa5a0b2..64d48639a170c7325736e7ee63735b07bb0a3016 100644
--- a/libraries/technology/clkbuf/hdllib.cfg
+++ b/libraries/technology/clkbuf/hdllib.cfg
@@ -7,7 +7,7 @@ hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_arria10_clkbuf_global ip_arria10_clkbuf_global_altclkctrl_150
ip_arria10_e3sge3_clkbuf_global ip_arria10_e3sge3_clkbuf_global_altclkctrl_151
- ip_arria10_e1sg_clkbuf_global ip_arria10_e1sg_clkbuf_global_altclkctrl_151
+ ip_arria10_e1sg_clkbuf_global ip_arria10_e1sg_clkbuf_global_altclkctrl_170
synth_files =
tech_clkbuf_component_pkg.vhd
diff --git a/libraries/technology/clkbuf/tech_clkbuf.vhd b/libraries/technology/clkbuf/tech_clkbuf.vhd
index ef2500794bd06d8eb3e92e11d1cd7785811c1f8a..b55e51bdde3ac19be82aeaed23ccc28841919859 100644
--- a/libraries/technology/clkbuf/tech_clkbuf.vhd
+++ b/libraries/technology/clkbuf/tech_clkbuf.vhd
@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_clkbuf_global_altclkctrl_150;
LIBRARY ip_arria10_e3sge3_clkbuf_global_altclkctrl_151;
-LIBRARY ip_arria10_e1sg_clkbuf_global_altclkctrl_151;
+LIBRARY ip_arria10_e1sg_clkbuf_global_altclkctrl_170;
ENTITY tech_clkbuf IS
GENERIC (
diff --git a/libraries/technology/ddr/hdllib.cfg b/libraries/technology/ddr/hdllib.cfg
index 08c18b33665908f8ee4fe28a396cadc1f6cf04ab..f26d4331997d5f4f4ff6c68f24ffa719f605c5f5 100644
--- a/libraries/technology/ddr/hdllib.cfg
+++ b/libraries/technology/ddr/hdllib.cfg
@@ -33,10 +33,10 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e3sge3_ddr4_8g_1600 ip_arria10_e3sge3_ddr4_8g_1600_altera_emif_151
ip_arria10_e3sge3_ddr4_4g_2000 ip_arria10_e3sge3_ddr4_4g_2000_altera_emif_151
ip_arria10_e3sge3_ddr4_8g_2400 ip_arria10_e3sge3_ddr4_8g_2400_altera_emif_151
- ip_arria10_e1sg_ddr4_4g_1600 ip_arria10_e1sg_ddr4_4g_1600_altera_emif_151
- ip_arria10_e1sg_ddr4_8g_1600 ip_arria10_e1sg_ddr4_8g_1600_altera_emif_151
- ip_arria10_e1sg_ddr4_4g_2000 ip_arria10_e1sg_ddr4_4g_2000_altera_emif_151
- ip_arria10_e1sg_ddr4_8g_2400 ip_arria10_e1sg_ddr4_8g_2400_altera_emif_151
+ ip_arria10_e1sg_ddr4_4g_1600 ip_arria10_e1sg_ddr4_4g_1600_altera_emif_170
+ ip_arria10_e1sg_ddr4_8g_1600 ip_arria10_e1sg_ddr4_8g_1600_altera_emif_170
+ ip_arria10_e1sg_ddr4_4g_2000 ip_arria10_e1sg_ddr4_4g_2000_altera_emif_170
+ ip_arria10_e1sg_ddr4_8g_2400 ip_arria10_e1sg_ddr4_8g_2400_altera_emif_170
ip_stratixiv_ddr3_mem_model ip_stratixiv_ddr3_mem_model_lib
ip_arria10_ddr4_mem_model_141 ip_arria10_ddr4_mem_model_141
diff --git a/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd b/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd
index 49f45f3b2e0068b1c2b1b6ee64dd1e57a6f4a097..6564425f2d010587da68966283742e348998e239 100644
--- a/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd
+++ b/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd
@@ -34,10 +34,10 @@
-- DDR interface monitoring purposes.
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_ddr4_4g_1600_altera_emif_151;
-LIBRARY ip_arria10_e1sg_ddr4_8g_1600_altera_emif_151;
-LIBRARY ip_arria10_e1sg_ddr4_4g_2000_altera_emif_151;
-LIBRARY ip_arria10_e1sg_ddr4_8g_2400_altera_emif_151;
+LIBRARY ip_arria10_e1sg_ddr4_4g_1600_altera_emif_170;
+LIBRARY ip_arria10_e1sg_ddr4_8g_1600_altera_emif_170;
+LIBRARY ip_arria10_e1sg_ddr4_4g_2000_altera_emif_170;
+LIBRARY ip_arria10_e1sg_ddr4_8g_2400_altera_emif_170;
LIBRARY IEEE, technology_lib, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
diff --git a/libraries/technology/flash/hdllib.cfg b/libraries/technology/flash/hdllib.cfg
index 4424eaa64222f65cd73b9bda704b406159f7b701..e62927b9914d802cac14a587144065d2198281da 100644
--- a/libraries/technology/flash/hdllib.cfg
+++ b/libraries/technology/flash/hdllib.cfg
@@ -16,8 +16,8 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_remote_update ip_arria10_remote_update_altera_remote_update_150
ip_arria10_e3sge3_asmi_parallel ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151
ip_arria10_e3sge3_remote_update ip_arria10_e3sge3_remote_update_altera_remote_update_151
- ip_arria10_e1sg_asmi_parallel ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_151
- ip_arria10_e1sg_remote_update ip_arria10_e1sg_remote_update_altera_remote_update_151
+ ip_arria10_e1sg_asmi_parallel ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_170
+ ip_arria10_e1sg_remote_update ip_arria10_e1sg_remote_update_altera_remote_update_170
synth_files =
tech_flash_component_pkg.vhd
diff --git a/libraries/technology/flash/tech_flash_asmi_parallel.vhd b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
index e6bb150696df57ba1a8fcb4ff394f796ea5b21c1..37d20af1f263bed0fcc2c887f818788533aad23d 100644
--- a/libraries/technology/flash/tech_flash_asmi_parallel.vhd
+++ b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
@@ -31,7 +31,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_flash_lib;
LIBRARY ip_arria10_asmi_parallel_altera_asmi_parallel_150;
LIBRARY ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151;
-LIBRARY ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_151;
+LIBRARY ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_170;
ENTITY tech_flash_asmi_parallel IS
GENERIC (
diff --git a/libraries/technology/flash/tech_flash_remote_update.vhd b/libraries/technology/flash/tech_flash_remote_update.vhd
index 3d387c1e549ec928cd438ecdf816aa992073a3c7..f0949faec28f99afecb7931899a7d0a00c90d2af 100644
--- a/libraries/technology/flash/tech_flash_remote_update.vhd
+++ b/libraries/technology/flash/tech_flash_remote_update.vhd
@@ -31,7 +31,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_flash_lib;
LIBRARY ip_arria10_remote_update_altera_remote_update_150;
LIBRARY ip_arria10_e3sge3_remote_update_altera_remote_update_151;
-LIBRARY ip_arria10_e1sg_remote_update_altera_remote_update_151;
+LIBRARY ip_arria10_e1sg_remote_update_altera_remote_update_170;
ENTITY tech_flash_remote_update IS
GENERIC (
diff --git a/libraries/technology/fpga_temp_sens/hdllib.cfg b/libraries/technology/fpga_temp_sens/hdllib.cfg
index 22f6125780c98b328b44f81f935c58203f661108..2e5124c781c28e9edeb3eab47a56835202a094f6 100644
--- a/libraries/technology/fpga_temp_sens/hdllib.cfg
+++ b/libraries/technology/fpga_temp_sens/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_arria10_temp_sense ip_arria10_temp_sense_altera_temp_sense_150
ip_arria10_e3sge3_temp_sense ip_arria10_e3sge3_temp_sense_altera_temp_sense_151
- ip_arria10_e1sg_temp_sense ip_arria10_e1sg_temp_sense_altera_temp_sense_151
+ ip_arria10_e1sg_temp_sense ip_arria10_e1sg_temp_sense_altera_temp_sense_170
synth_files =
tech_fpga_temp_sens_component_pkg.vhd
diff --git a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
index ea06ed0820edeaf1a6990c5672b8178cf65e6b7b..65a773084abd2ad7ec2b9e97d690833afc61257b 100644
--- a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
+++ b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_temp_sense_altera_temp_sense_150;
LIBRARY ip_arria10_e3sge3_temp_sense_altera_temp_sense_151;
-LIBRARY ip_arria10_e1sg_temp_sense_altera_temp_sense_151;
+LIBRARY ip_arria10_e1sg_temp_sense_altera_temp_sense_170;
ENTITY tech_fpga_temp_sens IS
diff --git a/libraries/technology/fpga_voltage_sens/hdllib.cfg b/libraries/technology/fpga_voltage_sens/hdllib.cfg
index 46c474c6d38e42c5ca9726777fcf2860707ec731..03aaf853eda51a0d2cd3708ad0529fd869942e9b 100644
--- a/libraries/technology/fpga_voltage_sens/hdllib.cfg
+++ b/libraries/technology/fpga_voltage_sens/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_arria10_voltage_sense ip_arria10_voltage_sense_altera_voltage_sense_150
ip_arria10_e3sge3_voltage_sense ip_arria10_e3sge3_voltage_sense_altera_voltage_sense_151
- ip_arria10_e1sg_voltage_sense ip_arria10_e1sg_voltage_sense_altera_voltage_sense_151
+ ip_arria10_e1sg_voltage_sense ip_arria10_e1sg_voltage_sense_altera_voltage_sense_170
synth_files =
tech_fpga_voltage_sens_component_pkg.vhd
diff --git a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
index 8ddaaff0b2a47a3229ef0733ebcc95bdaa3b4c66..bc66f172fd61c55364e1fe5cd3afb81c71fdfb9c 100644
--- a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
+++ b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_voltage_sense_altera_voltage_sense_150;
LIBRARY ip_arria10_e3sge3_voltage_sense_altera_voltage_sense_151;
-LIBRARY ip_arria10_e1sg_voltage_sense_altera_voltage_sense_151;
+LIBRARY ip_arria10_e1sg_voltage_sense_altera_voltage_sense_170;
ENTITY tech_fpga_voltage_sens IS
diff --git a/libraries/technology/fractional_pll/hdllib.cfg b/libraries/technology/fractional_pll/hdllib.cfg
index aa107e1a63d99a87b952cfa1641f7b743c5a5fac..3c2cf1abd6a0a60053c1236255ee1723c7dcaf05 100644
--- a/libraries/technology/fractional_pll/hdllib.cfg
+++ b/libraries/technology/fractional_pll/hdllib.cfg
@@ -10,8 +10,8 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_fractional_pll_clk125 ip_arria10_fractional_pll_clk125_altera_xcvr_fpll_a10_150
ip_arria10_e3sge3_fractional_pll_clk200 ip_arria10_e3sge3_fractional_pll_clk200_altera_xcvr_fpll_a10_151
ip_arria10_e3sge3_fractional_pll_clk125 ip_arria10_e3sge3_fractional_pll_clk125_altera_xcvr_fpll_a10_151
- ip_arria10_e1sg_fractional_pll_clk200 ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_151
- ip_arria10_e1sg_fractional_pll_clk125 ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_151
+ ip_arria10_e1sg_fractional_pll_clk200 ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_170
+ ip_arria10_e1sg_fractional_pll_clk125 ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_170
synth_files =
tech_fractional_pll_component_pkg.vhd
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
index db1911d5832aa222eb1f167a5cda8ca94672afa4..cc8f297c07540396431186aace896b4dfc7b2e3f 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_fractional_pll_clk125_altera_xcvr_fpll_a10_150;
LIBRARY ip_arria10_e3sge3_fractional_pll_clk125_altera_xcvr_fpll_a10_151;
-LIBRARY ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_151;
+LIBRARY ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_170;
ENTITY tech_fractional_pll_clk125 IS
GENERIC (
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
index 51147162242f50ae7508c38c7b253e166c204578..f30733508e9b2efd2d487f614532c410eb9f9dc4 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_fractional_pll_clk200_altera_xcvr_fpll_a10_150;
LIBRARY ip_arria10_e3sge3_fractional_pll_clk200_altera_xcvr_fpll_a10_151;
-LIBRARY ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_151;
+LIBRARY ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_170;
ENTITY tech_fractional_pll_clk200 IS
GENERIC (
diff --git a/libraries/technology/mac_10g/hdllib.cfg b/libraries/technology/mac_10g/hdllib.cfg
index c81aa3c75320a8beab2a967bb5ee9c3b3e53efcc..c73c25d07ace159e1cdc134df74059710a78010e 100644
--- a/libraries/technology/mac_10g/hdllib.cfg
+++ b/libraries/technology/mac_10g/hdllib.cfg
@@ -8,7 +8,7 @@ hdl_lib_disclose_library_clause_names =
ip_stratixiv_mac_10g ip_stratixiv_mac_10g_lib
ip_arria10_mac_10g ip_arria10_mac_10g_alt_em10g32_150
ip_arria10_e3sge3_mac_10g ip_arria10_e3sge3_mac_10g_alt_em10g32_151
- ip_arria10_e1sg_mac_10g ip_arria10_e1sg_mac_10g_alt_em10g32_151
+ ip_arria10_e1sg_mac_10g ip_arria10_e1sg_mac_10g_alt_em10g32_170
synth_files =
tech_mac_10g_component_pkg.vhd
diff --git a/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd b/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd
index e01af57e0112c0c32b74a9dcf6cb51073250971a..c41aa2774891bb77962b62ea95583f0aadd33648 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd
@@ -21,7 +21,7 @@
--------------------------------------------------------------------------------
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_mac_10g_alt_em10g32_151;
+LIBRARY ip_arria10_e1sg_mac_10g_alt_em10g32_170;
LIBRARY IEEE, technology_lib, common_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
diff --git a/libraries/technology/pll/hdllib.cfg b/libraries/technology/pll/hdllib.cfg
index 7b5ef9392e2caf521355012f7dbb6dd262cbcc49..4b047fa7c0eb0237004172d7426940ffe6f5ba8d 100644
--- a/libraries/technology/pll/hdllib.cfg
+++ b/libraries/technology/pll/hdllib.cfg
@@ -18,10 +18,10 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e3sge3_pll_clk25 ip_arria10_e3sge3_pll_clk25_altera_iopll_151
ip_arria10_e3sge3_pll_clk125 ip_arria10_e3sge3_pll_clk125_altera_iopll_151
ip_arria10_e3sge3_pll_xgmii_mac_clocks ip_arria10_e3sge3_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151
- ip_arria10_e1sg_pll_clk200 ip_arria10_e1sg_pll_clk200_altera_iopll_151
- ip_arria10_e1sg_pll_clk25 ip_arria10_e1sg_pll_clk25_altera_iopll_151
- ip_arria10_e1sg_pll_clk125 ip_arria10_e1sg_pll_clk125_altera_iopll_151
- ip_arria10_e1sg_pll_xgmii_mac_clocks ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151
+ ip_arria10_e1sg_pll_clk200 ip_arria10_e1sg_pll_clk200_altera_iopll_170
+ ip_arria10_e1sg_pll_clk25 ip_arria10_e1sg_pll_clk25_altera_iopll_170
+ ip_arria10_e1sg_pll_clk125 ip_arria10_e1sg_pll_clk125_altera_iopll_170
+ ip_arria10_e1sg_pll_xgmii_mac_clocks ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_170
synth_files =
tech_pll_component_pkg.vhd
diff --git a/libraries/technology/pll/tech_pll_clk125.vhd b/libraries/technology/pll/tech_pll_clk125.vhd
index dc5cd91e9fb2148dcc373b72023525161ffc12e3..5cdbbb6be1a4d276d0f2d45e3f701d4ca56c5bb4 100644
--- a/libraries/technology/pll/tech_pll_clk125.vhd
+++ b/libraries/technology/pll/tech_pll_clk125.vhd
@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_pll_clk125_altera_iopll_150;
LIBRARY ip_arria10_e3sge3_pll_clk125_altera_iopll_151;
-LIBRARY ip_arria10_e1sg_pll_clk125_altera_iopll_151;
+LIBRARY ip_arria10_e1sg_pll_clk125_altera_iopll_170;
ENTITY tech_pll_clk125 IS
GENERIC (
diff --git a/libraries/technology/pll/tech_pll_clk200.vhd b/libraries/technology/pll/tech_pll_clk200.vhd
index 2e9f9ed5e7468f4e234a73de21985002eeee45e7..4eefc35b6de5375616b1f9bc585a4cc750ba1771 100644
--- a/libraries/technology/pll/tech_pll_clk200.vhd
+++ b/libraries/technology/pll/tech_pll_clk200.vhd
@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_pll_lib;
LIBRARY ip_arria10_pll_clk200_altera_iopll_150;
LIBRARY ip_arria10_e3sge3_pll_clk200_altera_iopll_151;
-LIBRARY ip_arria10_e1sg_pll_clk200_altera_iopll_151;
+LIBRARY ip_arria10_e1sg_pll_clk200_altera_iopll_170;
ENTITY tech_pll_clk200 IS
GENERIC (
diff --git a/libraries/technology/pll/tech_pll_clk25.vhd b/libraries/technology/pll/tech_pll_clk25.vhd
index e02409a04d6877a723cc9b202ec63328d749a8af..2521432735ce688387a6fa211a847973d1ef7845 100644
--- a/libraries/technology/pll/tech_pll_clk25.vhd
+++ b/libraries/technology/pll/tech_pll_clk25.vhd
@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_pll_clk25_altera_iopll_150;
LIBRARY ip_stratixiv_pll_clk25_lib;
LIBRARY ip_arria10_e3sge3_pll_clk25_altera_iopll_151;
-LIBRARY ip_arria10_e1sg_pll_clk25_altera_iopll_151;
+LIBRARY ip_arria10_e1sg_pll_clk25_altera_iopll_170;
ENTITY tech_pll_clk25 IS
GENERIC (
diff --git a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
index 731530e5850d8768fc3a009824593aa661374164..28f1fa3a1ed8ac9a886605359bd397afc11640ca 100644
--- a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
+++ b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
@@ -43,7 +43,7 @@ USE common_lib.common_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_150;
LIBRARY ip_arria10_e3sge3_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151;
-LIBRARY ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151;
+LIBRARY ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_170;
ENTITY tech_pll_xgmii_mac_clocks IS
GENERIC (
diff --git a/libraries/technology/tse/hdllib.cfg b/libraries/technology/tse/hdllib.cfg
index e9dc7a5dab961b053d1065ccd826f431305b9ba0..2198a8e3981778c0c5b6809471e644a39af00f6d 100644
--- a/libraries/technology/tse/hdllib.cfg
+++ b/libraries/technology/tse/hdllib.cfg
@@ -14,8 +14,8 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_tse_sgmii_gx ip_arria10_tse_sgmii_gx_altera_eth_tse_150
ip_arria10_e3sge3_tse_sgmii_lvds ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_151
ip_arria10_e3sge3_tse_sgmii_gx ip_arria10_e3sge3_tse_sgmii_gx_altera_eth_tse_151
- ip_arria10_e1sg_tse_sgmii_lvds ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_151
- ip_arria10_e1sg_tse_sgmii_gx ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_151
+ ip_arria10_e1sg_tse_sgmii_lvds ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_170
+ ip_arria10_e1sg_tse_sgmii_gx ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_170
synth_files =
tech_tse_component_pkg.vhd
diff --git a/libraries/technology/tse/tech_tse.vhd b/libraries/technology/tse/tech_tse.vhd
index 0fdc5bb4c43913b57f8a3d9c2139787501a5f4c2..967b83e54b3b2c37b1bfa5d439169e5028b9fd30 100644
--- a/libraries/technology/tse/tech_tse.vhd
+++ b/libraries/technology/tse/tech_tse.vhd
@@ -137,16 +137,16 @@ BEGIN
END GENERATE;
gen_sim_tse : IF c_use_sim_model=TRUE GENERATE
- u_sim_tse : ENTITY work.sim_tse
- GENERIC MAP (g_sim_tx, g_sim_rx)
- PORT MAP (mm_rst, mm_clk, eth_clk, tx_snk_clk, rx_src_clk,
- mm_sla_in, mm_sla_out,
- tx_snk_in, tx_snk_out,
- tx_mac_in, tx_mac_out,
- rx_src_in, rx_src_out,
- rx_mac_out,
- eth_txp, eth_rxp,
- tse_led);
+-- u_sim_tse : ENTITY work.sim_tse
+-- GENERIC MAP (g_sim_tx, g_sim_rx)
+-- PORT MAP (mm_rst, mm_clk, eth_clk, tx_snk_clk, rx_src_clk,
+-- mm_sla_in, mm_sla_out,
+-- tx_snk_in, tx_snk_out,
+-- tx_mac_in, tx_mac_out,
+-- rx_src_in, rx_src_out,
+-- rx_mac_out,
+-- eth_txp, eth_rxp,
+-- tse_led);
END GENERATE;
END ARCHITECTURE;
diff --git a/libraries/technology/tse/tech_tse_arria10_e1sg.vhd b/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
index 7ff63e253131d54959fd77e87fc080ed097ffdf2..4512fe7d9e9a08487caa41b6376ce774ee07ef82 100644
--- a/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
+++ b/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
@@ -28,8 +28,8 @@ USE common_lib.common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_151;
-LIBRARY ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_151;
+LIBRARY ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_170;
+LIBRARY ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_170;
ENTITY tech_tse_arria10_e1sg IS
GENERIC (