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Commit dace1a94 authored by Reinier van der Walle's avatar Reinier van der Walle
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added compile_ip.tcl files and edited hdllib.cfg to change the quartus 

version number from 151 to 170
parent 70fae082
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with 696 additions and 18 deletions
libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl 0 → 100644
+ 39
− 0
View file @ dace1a94
#------------------------------------------------------------------------------
#
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on generated file mentor/msim_setup.tcl.
# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/clkbuf_global/generated/sim"
vmap altclkctrl_170 ./work/
vmap ip_arria10_e1sg_clkbuf_global ./work/
vcom "$IP_DIR/../altclkctrl_170/sim/ip_arria10_e1sg_clkbuf_global_altclkctrl_170_7fwzyby.vhd" -work altclkctrl_170
vcom "$IP_DIR/ip_arria10_e1sg_clkbuf_global.vhd" -work ip_arria10_e1sg_clkbuf_global
libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
+ 1
− 1
View file @ dace1a94
hdl_lib_name = ip_arria10_e1sg_clkbuf_global
hdl_library_clause_name = ip_arria10_e1sg_clkbuf_global_altclkctrl_151
hdl_library_clause_name = ip_arria10_e1sg_clkbuf_global_altclkctrl_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
......
libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl 0 → 100644
+ 39
− 0
View file @ dace1a94
#------------------------------------------------------------------------------
#
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on generated file mentor/msim_setup.tcl.
# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/complex_mult/generated/sim"
vmap ip_arria10_e1sg_complex_mult ./work/
vmap altmult_complex_170 ./work/
vcom "$IP_DIR/../altmult_complex_170/sim/ip_arria10_e1sg_complex_mult_altmult_complex_170_myrk3hi.vhd" -work altmult_complex_170
vcom "$IP_DIR/ip_arria10_e1sg_complex_mult.vhd" -work ip_arria10_e1sg_complex_mult
libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl 0 → 100644
+ 41
− 0
View file @ dace1a94
#------------------------------------------------------------------------------
#
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on generated file mentor/msim_setup.tcl.
# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddio/generated/sim"
vmap altera_gpio_core20_170 ./work/
vmap altera_gpio_170 ./work/
vmap ip_arria10_e1sg_ddio_out_1 ./work/
vlog -sv "$IP_DIR/../altera_gpio_core20_170/sim/mentor/altera_gpio.sv" -work altera_gpio_core20_170
vcom "$IP_DIR/../altera_gpio_170/sim/ip_arria10_e1sg_ddio_out_1_altera_gpio_170_pqckuoi.vhd" -work altera_gpio_170
vcom "$IP_DIR/ip_arria10_e1sg_ddio_out_1.vhd" -work ip_arria10_e1sg_ddio_out_1
libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl 0 → 100644
+ 95
− 0
View file @ dace1a94
#------------------------------------------------------------------------------
#
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on generated file mentor/msim_setup.tcl.
# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
vmap altera_merlin_master_translator_170 ./work/
vmap altera_emif_cal_slave_nf_170 ./work/
vmap altera_avalon_onchip_memory2_170 ./work/
vmap altera_mm_interconnect_170 ./work/
vmap altera_reset_controller_170 ./work/
vmap ip_arria10_e1sg_ddr4_4g_1600 ./work/
vmap altera_emif_arch_nf_170 ./work/
vmap altera_emif_170 ./work/
vmap altera_avalon_mm_bridge_170 ./work/
vmap altera_merlin_slave_translator_170 ./work/
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti_top.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti_io_aux.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_bufs.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_se_i.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_se_o.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_df_i.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_df_o.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_cp_i.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_bdir_df.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_bdir_se.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_unused.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_cal_counter.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll_fast_sim.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll_extra_clks.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_oct.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_core_clks_rsts.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hps_clks_rsts.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles_wrap.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles_abphy.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_abphy_mux.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_avl_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_sideband_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_mmr_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_amm_data_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_ast_data_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_afi_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_seq_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_regs.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_oct.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_oct_um_fsm.sv" -work altera_emif_arch_nf_170
vlog "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_std_synchronizer_nocut.v" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/mem_array_abphy.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_abphy.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_encrypted_abphy.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_nf5es_encrypted_abphy.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/io_12_lane_bcm__nf5es_abphy.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/io_12_lane__nf5es_abphy.sv" -work altera_emif_arch_nf_170
vlog "$IP_DIR/../altera_avalon_mm_bridge_170/sim/altera_avalon_mm_bridge.v" -work altera_avalon_mm_bridge_170
vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
vlog -sv "$IP_DIR/../altera_merlin_master_translator_170/sim/altera_merlin_master_translator.sv" -work altera_merlin_master_translator_170
vlog -sv "$IP_DIR/../altera_merlin_slave_translator_170/sim/mentor/altera_merlin_slave_translator.sv" -work altera_merlin_slave_translator_170
vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170
vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_170
vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_170
vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170
vlog "$IP_DIR/../altera_emif_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_170_fpxzpei.v" -work altera_emif_170
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_4g_1600.vhd" -work ip_arria10_e1sg_ddr4_4g_1600
libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
+ 1
− 1
View file @ dace1a94
hdl_lib_name = ip_arria10_e1sg_ddr4_4g_1600
hdl_library_clause_name = ip_arria10_e1sg_ddr4_4g_1600_altera_emif_151
hdl_library_clause_name = ip_arria10_e1sg_ddr4_4g_1600_altera_emif_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
......
libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl 0 → 100644
+ 95
− 0
View file @ dace1a94
#------------------------------------------------------------------------------
#
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on generated file mentor/msim_setup.tcl.
# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
vmap altera_merlin_master_translator_170 ./work/
vmap altera_emif_cal_slave_nf_170 ./work/
vmap altera_avalon_onchip_memory2_170 ./work/
vmap ip_arria10_e1sg_ddr4_4g_2000 ./work/
vmap altera_mm_interconnect_170 ./work/
vmap altera_reset_controller_170 ./work/
vmap altera_emif_arch_nf_170 ./work/
vmap altera_emif_170 ./work/
vmap altera_avalon_mm_bridge_170 ./work/
vmap altera_merlin_slave_translator_170 ./work/
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq_top.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq_io_aux.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_bufs.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_se_i.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_se_o.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_df_i.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_df_o.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_cp_i.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_bdir_df.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_bdir_se.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_unused.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_cal_counter.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll_fast_sim.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll_extra_clks.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_oct.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_core_clks_rsts.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hps_clks_rsts.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles_wrap.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles_abphy.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_abphy_mux.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_avl_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_sideband_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_mmr_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_amm_data_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_ast_data_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_afi_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_seq_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_regs.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_oct.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_oct_um_fsm.sv" -work altera_emif_arch_nf_170
vlog "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_std_synchronizer_nocut.v" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/mem_array_abphy.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_abphy.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_encrypted_abphy.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_nf5es_encrypted_abphy.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/io_12_lane_bcm__nf5es_abphy.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/io_12_lane__nf5es_abphy.sv" -work altera_emif_arch_nf_170
vlog "$IP_DIR/../altera_avalon_mm_bridge_170/sim/altera_avalon_mm_bridge.v" -work altera_avalon_mm_bridge_170
vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
vlog -sv "$IP_DIR/../altera_merlin_master_translator_170/sim/altera_merlin_master_translator.sv" -work altera_merlin_master_translator_170
vlog -sv "$IP_DIR/../altera_merlin_slave_translator_170/sim/mentor/altera_merlin_slave_translator.sv" -work altera_merlin_slave_translator_170
vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170
vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_170
vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_170
vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170
vlog "$IP_DIR/../altera_emif_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_170_e7aaa3y.v" -work altera_emif_170
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_4g_2000.vhd" -work ip_arria10_e1sg_ddr4_4g_2000
libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
+ 1
− 1
View file @ dace1a94
hdl_lib_name = ip_arria10_e1sg_ddr4_4g_2000
hdl_library_clause_name = ip_arria10_e1sg_ddr4_4g_2000_altera_emif_151
hdl_library_clause_name = ip_arria10_e1sg_ddr4_4g_2000_altera_emif_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
......
libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl 0 → 100644
+ 125
− 0
View file @ dace1a94
#------------------------------------------------------------------------------
#
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on generated file mentor/msim_setup.tcl.
# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
vmap ip_arria10_e1sg_ddr4_8g_1600 ./work/
vmap altera_reset_controller_170 ./work/
vmap altera_avalon_sc_fifo_170 ./work/
vmap altera_avalon_st_packets_to_bytes_170 ./work/
vmap altera_emif_cal_slave_nf_170 ./work/
vmap altera_merlin_slave_translator_170 ./work/
vmap altera_emif_170 ./work/
vmap altera_ip_col_if_170 ./work/
vmap altera_avalon_onchip_memory2_170 ./work/
vmap altera_jtag_dc_streaming_170 ./work/
vmap altera_merlin_master_translator_170 ./work/
vmap altera_avalon_mm_bridge_170 ./work/
vmap alt_mem_if_jtag_master_170 ./work/
vmap altera_emif_arch_nf_170 ./work/
vmap altera_avalon_st_bytes_to_packets_170 ./work/
vmap altera_mm_interconnect_170 ./work/
vmap altera_avalon_packets_to_master_170 ./work/
vmap channel_adapter_170 ./work/
vmap timing_adapter_170 ./work/
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei_top.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei_io_aux.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_bufs.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_se_i.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_se_o.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_df_i.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_df_o.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_cp_i.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_bdir_df.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_bdir_se.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_unused.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_cal_counter.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll_fast_sim.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll_extra_clks.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_oct.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_core_clks_rsts.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hps_clks_rsts.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles_wrap.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles_abphy.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_abphy_mux.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_avl_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_sideband_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_mmr_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_amm_data_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_ast_data_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_afi_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_seq_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_regs.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_oct.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_oct_um_fsm.sv" -work altera_emif_arch_nf_170
vlog "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_std_synchronizer_nocut.v" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/mem_array_abphy.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_abphy.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_encrypted_abphy.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_nf5es_encrypted_abphy.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/io_12_lane_bcm__nf5es_abphy.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/io_12_lane__nf5es_abphy.sv" -work altera_emif_arch_nf_170
vlog "$IP_DIR/../altera_avalon_mm_bridge_170/sim/altera_avalon_mm_bridge.v" -work altera_avalon_mm_bridge_170
vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_jtag_interface.v" -work altera_jtag_dc_streaming_170
vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_jtag_dc_streaming.v" -work altera_jtag_dc_streaming_170
vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_jtag_sld_node.v" -work altera_jtag_dc_streaming_170
vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_jtag_streaming.v" -work altera_jtag_dc_streaming_170
vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_clock_crosser.v" -work altera_jtag_dc_streaming_170
vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_std_synchronizer_nocut.v" -work altera_jtag_dc_streaming_170
vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_pipeline_base.v" -work altera_jtag_dc_streaming_170
vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_idle_remover.v" -work altera_jtag_dc_streaming_170
vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_idle_inserter.v" -work altera_jtag_dc_streaming_170
vlog -sv "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_pipeline_stage.sv" -work altera_jtag_dc_streaming_170
vlog -sv "$IP_DIR/../timing_adapter_170/sim/ip_arria10_e1sg_ddr4_8g_1600_timing_adapter_170_osazali.sv" -work timing_adapter_170
vlog "$IP_DIR/../altera_avalon_sc_fifo_170/sim/altera_avalon_sc_fifo.v" -work altera_avalon_sc_fifo_170
vlog "$IP_DIR/../altera_avalon_st_bytes_to_packets_170/sim/altera_avalon_st_bytes_to_packets.v" -work altera_avalon_st_bytes_to_packets_170
vlog "$IP_DIR/../altera_avalon_st_packets_to_bytes_170/sim/altera_avalon_st_packets_to_bytes.v" -work altera_avalon_st_packets_to_bytes_170
vlog "$IP_DIR/../altera_avalon_packets_to_master_170/sim/altera_avalon_packets_to_master.v" -work altera_avalon_packets_to_master_170
vlog -sv "$IP_DIR/../channel_adapter_170/sim/ip_arria10_e1sg_ddr4_8g_1600_channel_adapter_170_bsi6toa.sv" -work channel_adapter_170
vlog -sv "$IP_DIR/../channel_adapter_170/sim/ip_arria10_e1sg_ddr4_8g_1600_channel_adapter_170_xbvi4ny.sv" -work channel_adapter_170
vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_170
vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_170
vcom "$IP_DIR/../alt_mem_if_jtag_master_170/sim/ip_arria10_e1sg_ddr4_8g_1600_alt_mem_if_jtag_master_170_biwt3uq.vhd" -work alt_mem_if_jtag_master_170
vlog -sv "$IP_DIR/../altera_merlin_master_translator_170/sim/altera_merlin_master_translator.sv" -work altera_merlin_master_translator_170
vlog -sv "$IP_DIR/../altera_merlin_slave_translator_170/sim/mentor/altera_merlin_slave_translator.sv" -work altera_merlin_slave_translator_170
vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_3gbam2q.vhd" -work altera_mm_interconnect_170
vlog "$IP_DIR/../altera_ip_col_if_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_ip_col_if_170_bnb3mmy.v" -work altera_ip_col_if_170
vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170
vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170
vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_lcqbbfq.vhd" -work altera_mm_interconnect_170
vlog "$IP_DIR/../altera_emif_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_170_zmrgaza.v" -work altera_emif_170
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_8g_1600.vhd" -work ip_arria10_e1sg_ddr4_8g_1600
libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
+ 1
− 1
View file @ dace1a94
hdl_lib_name = ip_arria10_e1sg_ddr4_8g_1600
hdl_library_clause_name = ip_arria10_e1sg_ddr4_8g_1600_altera_emif_151
hdl_library_clause_name = ip_arria10_e1sg_ddr4_8g_1600_altera_emif_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
......
libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl 0 → 100644
+ 95
− 0
View file @ dace1a94
#------------------------------------------------------------------------------
#
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on generated file mentor/msim_setup.tcl.
# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
vmap altera_merlin_master_translator_170 ./work/
vmap altera_emif_cal_slave_nf_170 ./work/
vmap altera_avalon_onchip_memory2_170 ./work/
vmap ip_arria10_e1sg_ddr4_8g_2400 ./work/
vmap altera_mm_interconnect_170 ./work/
vmap altera_reset_controller_170 ./work/
vmap altera_emif_arch_nf_170 ./work/
vmap altera_emif_170 ./work/
vmap altera_avalon_mm_bridge_170 ./work/
vmap altera_merlin_slave_translator_170 ./work/
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_170_as3yf3i_top.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_170_as3yf3i_io_aux.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_170_as3yf3i.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_bufs.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_se_i.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_se_o.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_df_i.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_df_o.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_cp_i.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_bdir_df.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_bdir_se.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_unused.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_cal_counter.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll_fast_sim.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll_extra_clks.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_oct.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_core_clks_rsts.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hps_clks_rsts.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles_wrap.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles_abphy.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_abphy_mux.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_avl_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_sideband_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_mmr_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_amm_data_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_ast_data_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_afi_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_seq_if.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_regs.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_oct.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_oct_um_fsm.sv" -work altera_emif_arch_nf_170
vlog "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_std_synchronizer_nocut.v" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/mem_array_abphy.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_abphy.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_encrypted_abphy.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_nf5es_encrypted_abphy.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/io_12_lane_bcm__nf5es_abphy.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/io_12_lane__nf5es_abphy.sv" -work altera_emif_arch_nf_170
vlog "$IP_DIR/../altera_avalon_mm_bridge_170/sim/altera_avalon_mm_bridge.v" -work altera_avalon_mm_bridge_170
vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
vlog -sv "$IP_DIR/../altera_merlin_master_translator_170/sim/altera_merlin_master_translator.sv" -work altera_merlin_master_translator_170
vlog -sv "$IP_DIR/../altera_merlin_slave_translator_170/sim/mentor/altera_merlin_slave_translator.sv" -work altera_merlin_slave_translator_170
vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170
vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_170
vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_170
vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170
vlog "$IP_DIR/../altera_emif_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_170_xxodvzi.v" -work altera_emif_170
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_8g_2400.vhd" -work ip_arria10_e1sg_ddr4_8g_2400
libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
+ 1
− 1
View file @ dace1a94
hdl_lib_name = ip_arria10_e1sg_ddr4_8g_2400
hdl_library_clause_name = ip_arria10_e1sg_ddr4_8g_2400_altera_emif_151
hdl_library_clause_name = ip_arria10_e1sg_ddr4_8g_2400_altera_emif_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
......
libraries/technology/ip_arria10_e1sg/fifo/compile_ip.tcl 0 → 100644
+ 39
− 0
View file @ dace1a94
#------------------------------------------------------------------------------
#
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on generated file mentor/msim_setup.tcl.
# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/fifo/generated/sim"
vmap ip_arria10_e1sg_fifo_dc_mixed_widths ./work/
vmap fifo_170 ./work/
vcom "$IP_DIR/../fifo_170/sim/ip_arria10_e1sg_fifo_dc_mixed_widths_fifo_170_kpo7qdy.vhd" -work fifo_170
vcom "$IP_DIR/ip_arria10_e1sg_fifo_dc_mixed_widths.vhd" -work ip_arria10_e1sg_fifo_dc_mixed_widths
libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
+ 9
− 4
View file @ dace1a94
#------------------------------------------------------------------------------
#
# Copyright (C) 2014
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
......@@ -26,9 +26,14 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generated/sim"
vmap ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_151 ./work/
vmap altera_asmi_parallel_170 ./work/
vmap ip_arria10_e1sg_asmi_parallel ./work/
vlog "$IP_DIR/../altera_asmi_parallel_151/sim/ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_151_27ndfba.v" -work ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_151
vcom "$IP_DIR/ip_arria10_e1sg_asmi_parallel.vhd"
vcom "$IP_DIR/../altera_asmi_parallel_170/sim/ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_170_eou4tfa.vhd" -work altera_asmi_parallel_170
vcom "$IP_DIR/ip_arria10_e1sg_asmi_parallel.vhd" -work ip_arria10_e1sg_asmi_parallel
libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
+ 1
− 1
View file @ dace1a94
hdl_lib_name = ip_arria10_e1sg_asmi_parallel
hdl_library_clause_name = ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_151
hdl_library_clause_name = ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
......
libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
+ 11
− 6
View file @ dace1a94
#------------------------------------------------------------------------------
#
# Copyright (C) 2014
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
......@@ -26,11 +26,16 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/flash/remote_update/generated/sim"
vmap ip_arria10_e1sg_remote_update_altera_remote_update_core_151 ./work/
vmap ip_arria10_e1sg_remote_update_altera_remote_update_151 ./work/
vmap ip_arria10_e1sg_remote_update ./work/
vmap altera_remote_update_170 ./work/
vmap altera_remote_update_core_170 ./work/
vlog "$IP_DIR/../altera_remote_update_core_151/sim/altera_remote_update_core.sv" -work ip_arria10_e1sg_remote_update_altera_remote_update_core_151
vlog "$IP_DIR/../altera_remote_update_151/sim/ip_arria10_e1sg_remote_update_altera_remote_update_151_fdzfjma.v" -work ip_arria10_e1sg_remote_update_altera_remote_update_151
vcom "$IP_DIR/ip_arria10_e1sg_remote_update.vhd"
vlog -sv "$IP_DIR/../altera_remote_update_core_170/sim/mentor/altera_remote_update_core.sv" -work altera_remote_update_core_170
vcom "$IP_DIR/../altera_remote_update_170/sim/ip_arria10_e1sg_remote_update_altera_remote_update_170_hsvaqga.vhd" -work altera_remote_update_170
vcom "$IP_DIR/ip_arria10_e1sg_remote_update.vhd" -work ip_arria10_e1sg_remote_update
libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
+ 1
− 1
View file @ dace1a94
hdl_lib_name = ip_arria10_e1sg_remote_update
hdl_library_clause_name = ip_arria10_e1sg_remote_update_altera_remote_update_151
hdl_library_clause_name = ip_arria10_e1sg_remote_update_altera_remote_update_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
......
libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl 0 → 100644
+ 50
− 0
View file @ dace1a94
#------------------------------------------------------------------------------
#
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on generated file mentor/msim_setup.tcl.
# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/generated/sim"
vmap altera_xcvr_fpll_a10_170 ./work/
vmap ip_arria10_e1sg_fractional_pll_clk125 ./work/
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/twentynm_xcvr_avmm.sv" -work altera_xcvr_fpll_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/twentynm_xcvr_avmm.sv" -work altera_xcvr_fpll_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_resync.sv" -work altera_xcvr_fpll_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/alt_xcvr_resync.sv" -work altera_xcvr_fpll_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/altera_xcvr_fpll_a10.sv" -work altera_xcvr_fpll_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/altera_xcvr_fpll_a10.sv" -work altera_xcvr_fpll_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/a10_avmm_h.sv" -work altera_xcvr_fpll_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_native_avmm_nf.sv" -work altera_xcvr_fpll_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_pll_embedded_debug.sv" -work altera_xcvr_fpll_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_pll_avmm_csr.sv" -work altera_xcvr_fpll_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -work altera_xcvr_fpll_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/alt_xcvr_pll_avmm_csr.sv" -work altera_xcvr_fpll_a10_170
vcom "$IP_DIR/ip_arria10_e1sg_fractional_pll_clk125.vhd" -work ip_arria10_e1sg_fractional_pll_clk125
libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
+ 1
− 1
View file @ dace1a94
hdl_lib_name = ip_arria10_e1sg_fractional_pll_clk125
hdl_library_clause_name = ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_151
hdl_library_clause_name = ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
......
libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl 0 → 100644
+ 50
− 0
View file @ dace1a94
#------------------------------------------------------------------------------
#
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on generated file mentor/msim_setup.tcl.
# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/generated/sim"
vmap altera_xcvr_fpll_a10_170 ./work/
vmap ip_arria10_e1sg_fractional_pll_clk200 ./work/
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/twentynm_xcvr_avmm.sv" -work altera_xcvr_fpll_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/twentynm_xcvr_avmm.sv" -work altera_xcvr_fpll_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_resync.sv" -work altera_xcvr_fpll_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/alt_xcvr_resync.sv" -work altera_xcvr_fpll_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/altera_xcvr_fpll_a10.sv" -work altera_xcvr_fpll_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/altera_xcvr_fpll_a10.sv" -work altera_xcvr_fpll_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/a10_avmm_h.sv" -work altera_xcvr_fpll_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_native_avmm_nf.sv" -work altera_xcvr_fpll_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_pll_embedded_debug.sv" -work altera_xcvr_fpll_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_pll_avmm_csr.sv" -work altera_xcvr_fpll_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -work altera_xcvr_fpll_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/alt_xcvr_pll_avmm_csr.sv" -work altera_xcvr_fpll_a10_170
vcom "$IP_DIR/ip_arria10_e1sg_fractional_pll_clk200.vhd" -work ip_arria10_e1sg_fractional_pll_clk200
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