backup last changes, build for unb2b not working

boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/quartus/unb1_test_ddr_16g_MB_I_II_pins.tcl

@@ -25,6 +25,6 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
 
 # -- include ddr3 pins
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
 

boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg

@@ -17,7 +17,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
 
 
 [quartus_project_file]
@@ -28,10 +28,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 quartus_tcl_files =
     quartus/unb1_test_ddr_MB_I_pins.tcl
@@ -41,5 +41,5 @@ quartus_vhdl_files =
 
 quartus_qip_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
 

boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg

@@ -17,7 +17,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
 
 
 [quartus_project_file]
@@ -28,10 +28,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 quartus_tcl_files =
     quartus/unb1_test_ddr_MB_I_pins.tcl
@@ -41,5 +41,5 @@ quartus_vhdl_files =
 
 quartus_qip_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
 

boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg

@@ -16,7 +16,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
 
 
 [quartus_project_file]
@@ -27,10 +27,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 quartus_tcl_files =
     quartus/unb1_test_ddr_MB_I_II_pins.tcl
@@ -40,5 +40,5 @@ quartus_vhdl_files =
 
 quartus_qip_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
 

boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/quartus/unb1_test_ddr_pins.tcl

@@ -25,6 +25,6 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
 
 # -- include ddr3 pins
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
 

boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg

@@ -26,7 +26,7 @@ quartus_copy_files =
 #    src/hex/ hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_tcl_files =
     quartus/unb1_tr_10GbE_pins.tcl
@@ -37,4 +37,4 @@ quartus_qip_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_tr_10GbE/qsys_unb1_tr_10GbE/synthesis/qsys_unb1_tr_10GbE.qip
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc    
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc    

boards/uniboard1/libraries/unb1_board/hdllib.cfg

@@ -43,9 +43,9 @@ synth_files =
     
     src/vhdl/unb1_board_peripherals_pkg.vhd
 
-    # For BN the $RADIOHDL/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd is 
+    # For BN the $RADIOHDL_WORK/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd is 
     # referred to directly in the apertif_unb1_bn_filterbank library.
-    # For FN a copy of $RADIOHDL/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
+    # For FN a copy of $RADIOHDL_WORK/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
     # is taken via this unb1_board library:
     src/vhdl/node_unb1_fn_terminal_db.vhd    
     

boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_allpins.tcl

@@ -23,7 +23,7 @@
 # Pin assignments
 
 # -- Common
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
 
 # -- Back Node specific
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_pins.tcl

boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_pins.tcl

@@ -23,10 +23,10 @@
 # Back node specific pin assignments
 
 # -- Backplane Interface
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_tr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_tr_pins.tcl
 
 # -- FN to BN Interface added 08-01-2010
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_mesh_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_mesh_pins.tcl
 
 # -- ADC Interface
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_adc_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_adc_pins.tcl

boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl

@@ -23,22 +23,22 @@
 # Common pin assignments for front_node and back_node
 
 # -- General: clk, pps, wdi, inta, intb
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
 
 # -- FPGA Interconnects Front-Node Back-Node
 #    Clocks only as transceiver pins are now different (08-01-2010)
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_tr_clk_pins.tcl
-#source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_tr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_tr_clk_pins.tcl
+#source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_tr_pins.tcl
 
 # -- 1GbE Control Interface
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
 
 # -- SO-DIMM Memory Banks I and II
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_ddr_I_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_ddr_II_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_ddr_I_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_ddr_II_pins.tcl
 
 # -- I2C Interface to Sensors
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
 
 # -- Other: version[1:0], id[7:0], testio[7:0]
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl

boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_allpins.tcl

@@ -23,7 +23,7 @@
 # Pin assignments
 
 # -- Common
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
 
 # -- Front Node specific
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_pins.tcl

boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_pins.tcl

@@ -23,9 +23,9 @@
 # Front node specific pin assignments
 
 # -- Front Interface (10GbE)
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_cntrl_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_cntrl_pins.tcl
 
 # -- FN to BN Mesh Interface added 08-01-2010
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_mesh_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_mesh_pins.tcl
 

boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_back_pcs.tcl

@@ -20,6 +20,6 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tx_back_pcs.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_rx_back_pcs.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tx_back_pcs.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_rx_back_pcs.tcl
 

boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs.tcl

@@ -20,7 +20,7 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_clk.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_0.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_1.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_2.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_clk.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_0.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_1.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_2.tcl

boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_clk.tcl

@@ -20,7 +20,7 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_cntrl_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_cntrl_pins.tcl
 
 set_location_assignment PIN_AA2 -to SA_CLK
 set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SA_CLK

boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_mesh_pcs.tcl

@@ -20,5 +20,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tx_mesh_pcs.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_rx_mesh_pcs.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tx_mesh_pcs.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_rx_mesh_pcs.tcl

boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf

@@ -22,7 +22,7 @@
 # This QSF is sourced by other design QSF files.
 # ==============================================
 # Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
 
 # Device:
 set_global_assignment -name FAMILY "Stratix IV"
@@ -49,7 +49,7 @@ set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCS128
 if { [info exists ::env(UNB_COMPILE_STAMPS) ] } {
   set_parameter -name g_stamp_date [clock format [clock seconds] -format {%Y%m%d}]
   set_parameter -name g_stamp_time [clock format [clock seconds] -format {%H%M%S}]
-  post_message -type info "RADIOHDL: using SVN revision $::env(RADIOHDL_SVN_REVISION)"
-  set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_SVN_REVISION)] ""]
+  post_message -type info "RADIOHDL: using SVN revision $::env(RADIOHDL_GIT_REVISION)"
+  set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_GIT_REVISION)] ""]
 }
 

boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf

@@ -22,7 +22,7 @@
 # This QSF is sourced by other design QSF files.
 # ==============================================
 # Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
 
 # This file contains includes that should be added to another project QSF before 
 # user contraints and/or QIPs are added.
@@ -48,13 +48,13 @@ set_global_assignment -name USE_CONFIGURATION_DEVICE ON
 set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCS128
 
 # Timing constraints
-set_global_assignment -name SDC_FILE $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.sdc
+set_global_assignment -name SDC_FILE $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.sdc
 
 # Pass compile stamps as generics (passed to top-level when $UNB_COMPILE_STAMPS is set)
 if { [info exists ::env(UNB_COMPILE_STAMPS) ] } {
   set_parameter -name g_stamp_date [clock format [clock seconds] -format {%Y%m%d}]
   set_parameter -name g_stamp_time [clock format [clock seconds] -format {%H%M%S}]
-  post_message -type info "RADIOHDL: using SVN revision $::env(RADIOHDL_SVN_REVISION)"
-  set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_SVN_REVISION)] ""]
+  post_message -type info "RADIOHDL: using SVN revision $::env(RADIOHDL_GIT_REVISION)"
+  set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_GIT_REVISION)] ""]
 }
 

boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.qsf

@@ -22,12 +22,12 @@
 # This QSF is sourced by other design QSF files.
 # ==============================================
 # Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
 #
 # This file contains includes that should be added to another project QSF after certain
 # user contraints (DDR3 timing constraints for instance) have been included. 
 
 # Post Timing constraints
-set_global_assignment -name SDC_FILE $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.sdc
+set_global_assignment -name SDC_FILE $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.sdc
 
 

boards/uniboard2/designs/unb2_led/hdllib.cfg

@@ -20,10 +20,10 @@ synth_top_level_entity =
 quartus_copy_files =
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
 
 quartus_tcl_files =
     quartus/unb2_minimal_pins.tcl