diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000000000000000000000000000000000000..b1619157a91e71413a62edfb2c12bd1f8c617024
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,4 @@
+*log
+build*
+*generated
+*pyc
diff --git a/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg b/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
index 68229b7b18e63113f4702ba39013d30d00698049..e970f796712cf4d51ca47324d90d92a833b1f3cd 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
@@ -1,6 +1,7 @@
 hdl_lib_name = unb1_bn_capture
 hdl_library_clause_name = unb1_bn_capture_lib
 hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag aduh 
+hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
@@ -22,19 +23,19 @@ regression_test_vhdl =
     tb/vhdl/tb_node_unb1_bn_capture.vhd
 
 [modelsim_project_file]
-modelsim_copy_files = $RADIOHDL/libraries/io/i2c/tb/data data   
-                      $RADIOHDL/libraries/base/diag/src/data data
+modelsim_copy_files = $RADIOHDL_WORK/libraries/io/i2c/tb/data data   
+                      $RADIOHDL_WORK/libraries/base/diag/src/data data
 
 
 [quartus_project_file]
 synth_top_level_entity =
 
 quartus_copy_files = quartus/sopc_unb1_bn_capture.sopc .
-                     $RADIOHDL/libraries/io/i2c/tb/data data
-                     $RADIOHDL/libraries/base/diag/src/data data
+                     $RADIOHDL_WORK/libraries/io/i2c/tb/data data
+                     $RADIOHDL_WORK/libraries/base/diag/src/data data
 
 quartus_qsf_files = 
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_tcl_files =
     quartus/unb1_bn_capture_pins.tcl
@@ -42,7 +43,7 @@ quartus_tcl_files =
 quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.qip
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
 
 
 
diff --git a/boards/uniboard1/designs/unb1_bn_capture/quartus/unb1_bn_capture_pins.tcl b/boards/uniboard1/designs/unb1_bn_capture/quartus/unb1_bn_capture_pins.tcl
index 56d0bc7bacfbace8c02be8a96ec5110b396cdb50..f2cfef868fd2e9047e152cf979dd87185a7828fb 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/quartus/unb1_bn_capture_pins.tcl
+++ b/boards/uniboard1/designs/unb1_bn_capture/quartus/unb1_bn_capture_pins.tcl
@@ -1,13 +1,13 @@
 # Pin assignments
 # -- GENERAL: clk, pps, wdi, inta, intb
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
 # -- 1GbE Control Interface
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
 # -- I2C Interface to Sensors
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
 # -- Other: version[1:0], id[7:0], testio[7:0]
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
 # -- BN_BI ADC pins
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_adc_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_adc_pins.tcl
 
 
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg b/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
index 327cfda99ab7d337308e07d095629bd4696a73e0..e927886e07bc19dbeb12725fc3d420b243537bf5 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
@@ -1,6 +1,7 @@
 hdl_lib_name = unb1_bn_terminal_bg
 hdl_library_clause_name = unb1_bn_terminal_bg_lib
 hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag bf  
+hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
@@ -14,17 +15,17 @@ test_bench_files =
 
 
 [modelsim_project_file]
-modelsim_copy_files = $RADIOHDL/libraries/base/diag/src/data data
+modelsim_copy_files = $RADIOHDL_WORK/libraries/base/diag/src/data data
 
 
 [quartus_project_file]
 synth_top_level_entity =
 
 quartus_copy_files = quartus/sopc_unb1_bn_terminal_bg.sopc .
-                     $RADIOHDL/libraries/base/diag/src/data data 
+                     $RADIOHDL_WORK/libraries/base/diag/src/data data 
 
 quartus_qsf_files = 
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_tcl_files =
     quartus/unb1_bn_terminal_bg_pins.tcl
@@ -32,4 +33,4 @@ quartus_tcl_files =
 quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.qip
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/quartus/unb1_bn_terminal_bg_pins.tcl b/boards/uniboard1/designs/unb1_bn_terminal_bg/quartus/unb1_bn_terminal_bg_pins.tcl
index 41f447693a0ce09dc172e70cf48bdddb39b69f0a..0a38a91c5bde1dc5bcca249cfc476fd6cef064ad 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/quartus/unb1_bn_terminal_bg_pins.tcl
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/quartus/unb1_bn_terminal_bg_pins.tcl
@@ -1,14 +1,14 @@
 # Pin assignments
 # -- GENERAL: clk, pps, wdi, inta, intb
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
 # -- 1GbE Control Interface
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
 # -- I2C Interface to Sensors
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
 # -- Other: version[1:0], id[7:0], testio[7:0]
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
 # -- Mesh pins. 
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_mesh_tr_clk_pin.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_mesh_nocmu_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_mesh_tr_clk_pin.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_mesh_nocmu_pins.tcl
 
 
diff --git a/boards/uniboard1/designs/unb1_ddr3/doc/README b/boards/uniboard1/designs/unb1_ddr3/doc/README
index a6b8f853c324952f82d50f84eccbf7e8541e665d..4134e5df3170b97aa95b4ef5b8a1f7e3d89180b9 100644
--- a/boards/uniboard1/designs/unb1_ddr3/doc/README
+++ b/boards/uniboard1/designs/unb1_ddr3/doc/README
@@ -2,8 +2,8 @@ Quick steps to compile and use design [unb1_ddr3] in RadionHDL
 --------------------------------------------------------------
 
 Start with the Oneclick Commands:
-    python $RADIOHDL/tools/oneclick/base/modelsim_config.py
-    python $RADIOHDL/tools/oneclick/base/quartus_config.py
+    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py
+    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py
 
 Generate MMM for SOPC:
     run_sopc unb1 unb1_ddr3
diff --git a/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
index b24fe5c0be88b413b816bef23046129c18351227..d3453f987cb6922b2f80a72590a119b9db314085 100644
--- a/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
@@ -16,7 +16,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
     
 
 [quartus_project_file]
@@ -26,7 +26,7 @@ quartus_copy_files =
     quartus/sopc_unb1_ddr3.sopc .
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_qip_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.qip
@@ -36,5 +36,5 @@ quartus_tcl_files =
     quartus/unb1_ddr3_pins_constraints.tcl
     
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
diff --git a/boards/uniboard1/designs/unb1_ddr3/quartus/unb1_ddr3_pins.tcl b/boards/uniboard1/designs/unb1_ddr3/quartus/unb1_ddr3_pins.tcl
index 8c1eadf575d20076473ca8e238381bec057e73ca..caedfb746e613f2dc41d1ef37343d7a35ee4c56f 100644
--- a/boards/uniboard1/designs/unb1_ddr3/quartus/unb1_ddr3_pins.tcl
+++ b/boards/uniboard1/designs/unb1_ddr3/quartus/unb1_ddr3_pins.tcl
@@ -20,8 +20,8 @@
 ###############################################################################
 
 # -- include ddr3 pins
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
-#source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+#source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
 
 # -- include the clock pin
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/doc/README b/boards/uniboard1/designs/unb1_ddr3_reorder/doc/README
index f52ac9c7e5872268d8e0a48bf836668d9935e1fd..489688ec457794329f95d5d2c59c6efadd7f370e 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/doc/README
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/doc/README
@@ -2,8 +2,8 @@ Quick steps to compile and use design [unb1_ddr3_reorder] in RadioHDL
 --------------------------------------------------------------
 
 Start with the Oneclick Commands:
-    python $RADIOHDL/tools/oneclick/base/modelsim_config.py
-    python $RADIOHDL/tools/oneclick/base/quartus_config.py
+    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py
+    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py
 
 Generate MMM for SOPC:
     run_sopc unb1 unb1_ddr3_reorder
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/quartus/unb1_ddr3_reorder_pins.tcl b/boards/uniboard1/designs/unb1_ddr3_reorder/quartus/unb1_ddr3_reorder_pins.tcl
index 66c2161ff4af594b961a0aa90dbabd022697354c..9834de8f9a11bb8e1edd44377744c81eec020bf8 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/quartus/unb1_ddr3_reorder_pins.tcl
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/quartus/unb1_ddr3_reorder_pins.tcl
@@ -20,7 +20,7 @@
 ###############################################################################
 
 # -- include ddr3 pins
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
 
 # -- include the clock pin
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
index 8be0a5b4fb90c86b342091e5454803b6feb16053..4bded51236d67df60ccce7cc8bc964421e7517f6 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
@@ -22,7 +22,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
     
 
 [quartus_project_file]
@@ -33,7 +33,7 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_tcl_files =
     ../../quartus/unb1_ddr3_reorder_pins.tcl
@@ -42,6 +42,6 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
-    $RADIOHDL/build/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.qip
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+    $RADIOHDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.qip
     
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
index 104d038b62b71f7be03522443c9e637290e17ba3..d9e3a8cd86f62f5cea4ca23502f9b604f27d3c60 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
@@ -22,7 +22,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
     
 
 [quartus_project_file]
@@ -33,7 +33,7 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_tcl_files =
     ../../quartus/unb1_ddr3_reorder_pins.tcl
@@ -42,6 +42,6 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
-    $RADIOHDL/build/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.qip
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+    $RADIOHDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.qip
     
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/doc/README b/boards/uniboard1/designs/unb1_ddr3_transpose/doc/README
index b3475d0f6bb250cb8c7ce3bafade2d846f77cb78..d2fd86f43c99b07f84b4cc3deba00f64d7de6437 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/doc/README
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/doc/README
@@ -4,8 +4,8 @@ Quick steps to compile and use design [unb1_ddr3_transpose] in RadionHDL
 
 
 Start with the Oneclick Commands:
-    python $RADIOHDL/tools/oneclick/base/modelsim_config.py
-    python $RADIOHDL/tools/oneclick/base/quartus_config.py
+    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py
+    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py
 
 Generate MMM for SOPC and QSYS:
     run_sopc unb1 unb1_ddr3_transpose
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
index 97059fae5345f036cb41815eab7139b7b0a3809a..6c541b4951a465feb5e44f46a76f92aa81b64a66 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
@@ -16,7 +16,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
 
 
 [quartus_project_file]
@@ -26,7 +26,7 @@ quartus_copy_files =
     quartus/sopc_unb_ddr3_transpose.sopc .
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_tcl_files =
     quartus/unb1_ddr3_transpose_pins.tcl
@@ -36,5 +36,5 @@ quartus_vhdl_files =
 
 quartus_qip_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.qip
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
 
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb1_ddr3_transpose_pins.tcl b/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb1_ddr3_transpose_pins.tcl
index 644fc9a105d1a66032d68809db5f86c1d18cdc9b..1f162d6353dd4b10881cb3cf1c732fcd1e3a58a4 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb1_ddr3_transpose_pins.tcl
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb1_ddr3_transpose_pins.tcl
@@ -3,5 +3,5 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tc
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
 
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
 
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg b/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
index fb01a093b4dbd40fb89d9e0697df7daa480788a0..d956258b51215f3823a2536e2c3759685ac28fdd 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
@@ -1,6 +1,7 @@
 hdl_lib_name = unb1_fn_terminal_db
 hdl_library_clause_name = unb1_fn_terminal_db_lib
 hdl_lib_uses_synth = common technology mm i2c unb1_board diag 
+hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
 
 synth_files =   
@@ -22,7 +23,7 @@ synth_top_level_entity =
 quartus_copy_files = quartus/sopc_unb1_fn_terminal_db.sopc .
 
 quartus_qsf_files =                                                       
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_tcl_files =
     quartus/unb1_fn_terminal_db_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_heater/doc/README b/boards/uniboard1/designs/unb1_heater/doc/README
index 4919dd1d76e604f46c65ff2a11d0a476ad1c7d5f..a907cf2b91ffcb459d93f9ef3954d44bc0757e43 100644
--- a/boards/uniboard1/designs/unb1_heater/doc/README
+++ b/boards/uniboard1/designs/unb1_heater/doc/README
@@ -4,8 +4,8 @@ Quick steps to compile and use design [unb1_heater] in RadionHDL
 
 
 Start with the Oneclick Commands:
-    python $RADIOHDL/tools/oneclick/base/modelsim_config.py
-    python $RADIOHDL/tools/oneclick/base/quartus_config.py
+    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py
+    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py
 
 Generate MMM for SOPC and QSYS:
     run_qsys unb1 unb1_heater
diff --git a/boards/uniboard1/designs/unb1_heater/hdllib.cfg b/boards/uniboard1/designs/unb1_heater/hdllib.cfg
index 19c04e7f3c101dcbe173261b0b67862c49d6fb12..84640d28b1f24371368fcc37615c0e667423865e 100644
--- a/boards/uniboard1/designs/unb1_heater/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_heater/hdllib.cfg
@@ -23,10 +23,10 @@ quartus_copy_files =
     quartus/qsys_unb1_heater.qsys .
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
 
 quartus_tcl_files =
     quartus/unb1_heater_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_heater/quartus/unb1_heater_pins.tcl b/boards/uniboard1/designs/unb1_heater/quartus/unb1_heater_pins.tcl
index dfd44294b3c22eea1f164a02aae917a1f9492446..ff0099460334af052cfc829b7180226b563353f8 100644
--- a/boards/uniboard1/designs/unb1_heater/quartus/unb1_heater_pins.tcl
+++ b/boards/uniboard1/designs/unb1_heater/quartus/unb1_heater_pins.tcl
@@ -19,8 +19,8 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
 
diff --git a/boards/uniboard1/designs/unb1_minimal/doc/README b/boards/uniboard1/designs/unb1_minimal/doc/README
index ec32e31ac2d5a66cbbbfcfb305041784df53173e..d85df74cd153f712b2dcd7dabac0ac6106ced633 100644
--- a/boards/uniboard1/designs/unb1_minimal/doc/README
+++ b/boards/uniboard1/designs/unb1_minimal/doc/README
@@ -4,8 +4,8 @@ Quick steps to compile and use design [unb1_minimal] in RadionHDL
 
 
 Start with the Oneclick Commands:
-    python $RADIOHDL/tools/oneclick/base/modelsim_config.py
-    python $RADIOHDL/tools/oneclick/base/quartus_config.py
+    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py
+    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py
 
 Generate MMM for SOPC and QSYS:
     run_sopc unb1 unb1_minimal_sopc
@@ -58,12 +58,12 @@ Convert .sof to .rbf:
 
 
 Send to LCU capture5:
-    scp $RADIOHDL/build/quartus/unb1_minimal_qsys/unb1_minimal_qsys.rbf capture5:~/rbf/  # QSYS
+    scp $RADIOHDL_WORK/build/quartus/unb1_minimal_qsys/unb1_minimal_qsys.rbf capture5:~/rbf/  # QSYS
     or:
-    scp $RADIOHDL/build/quartus/unb1_minimal_qsys/unb1_minimal_sopc.rbf capture5:~/rbf/  # SOPC
+    scp $RADIOHDL_WORK/build/quartus/unb1_minimal_qsys/unb1_minimal_sopc.rbf capture5:~/rbf/  # SOPC
 
     # Now login on capture5 and use pythonscript to program flash:
-    cd $RADIOHDL/boards/uniboard1/designs/unb1_minimal/tb/python
+    cd $RADIOHDL_WORK/boards/uniboard1/designs/unb1_minimal/tb/python
 
     # for example use frontnode 0 on uniboard 0:
     python tc_unb1_minimal.py --gn 0 --seq REGMAP,FLASH -s ~/rbf/unb1_minimal_qsys.rbf   # QSYS
diff --git a/boards/uniboard1/designs/unb1_minimal/quartus/unb1_minimal_pins.tcl b/boards/uniboard1/designs/unb1_minimal/quartus/unb1_minimal_pins.tcl
index dfd44294b3c22eea1f164a02aae917a1f9492446..ff0099460334af052cfc829b7180226b563353f8 100644
--- a/boards/uniboard1/designs/unb1_minimal/quartus/unb1_minimal_pins.tcl
+++ b/boards/uniboard1/designs/unb1_minimal/quartus/unb1_minimal_pins.tcl
@@ -19,8 +19,8 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
 
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg
index 573fbd31dea7767c20f4375c1c4e4f7f70b68718..46135b978828b79f203bfaec21fdbcb86d7ee280 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg
@@ -21,10 +21,10 @@ quartus_copy_files =
     qsys_unb1_minimal_mm_arbiter.qsys .
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 quartus_tcl_files =
     ../../quartus/unb1_minimal_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg
index 2909ebe510cb12940277d5be92fc03c3522c0b89..30e64fde99c4f6fb2dd6017ffdf47ddaf690fcc7 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
     ../../quartus/qsys_unb1_minimal.qsys .
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 quartus_tcl_files =
     ../../quartus/unb1_minimal_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg
index 47ab642c8394e1eb706502d7f2c6863ccf585d51..8feddd68dcf48c586db3b8a2306966a2cf3d96b7 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg
@@ -23,10 +23,10 @@ quartus_copy_files =
     ../../quartus/qsys_wo_pll_unb1_minimal.qsys .
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
 
 quartus_tcl_files =
     ../../quartus/unb1_minimal_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg
index b533e42f3610a06f7be124169a844cdb0b0d44f1..2724f918e6875d03654ef80ddaa0c8bb8cfcc16b 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg
@@ -21,10 +21,10 @@ quartus_copy_files =
     ../../quartus/sopc_unb1_minimal.sopc .
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 quartus_tcl_files =
     ../../quartus/unb1_minimal_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
index f687fcbc733d138a4bc19915cb7a3377ae417679..f34d0b341d4591c8fc614498aecc2b4c347bd0ba 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
@@ -1,6 +1,7 @@
 hdl_lib_name = unb1_terminal_bg_mesh_db
 hdl_library_clause_name = unb1_terminal_bg_mesh_db_lib
 hdl_lib_uses_synth = common technology mm i2c unb1_board diag eth tech_tse
+hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
 
 synth_files =   
@@ -23,7 +24,7 @@ synth_top_level_entity =
 quartus_copy_files = quartus/qsys_unb1_terminal_bg_mesh_db.qsys .
                      src/hex hex                                                   
 quartus_qsf_files = 
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_tcl_files =
     quartus/unb1_terminal_bg_mesh_db_pins.tcl
@@ -32,4 +33,4 @@ quartus_qip_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.qip
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
diff --git a/boards/uniboard1/designs/unb1_test/doc/README b/boards/uniboard1/designs/unb1_test/doc/README
index 6aca7ca007cd8e23fc5b0b51528a21df7d79ee37..bb6725a13e98bf9fdbede3945c84006410068d93 100644
--- a/boards/uniboard1/designs/unb1_test/doc/README
+++ b/boards/uniboard1/designs/unb1_test/doc/README
@@ -16,16 +16,16 @@ The following revisions are available for unb1_test (see the directories in ../r
 
 
 -> In case of a new installation, the IP's have to be generated for Stratix IV. 
-   In the: $RADIOHDL/libraries/technology/ip_stratixiv 
+   In the: $RADIOHDL_WORK/libraries/technology/ip_stratixiv 
    directory; run the bash script: ./generate-all-ip.sh
 
 -> For compilation it might be necessary to check the .vhd file:
-   $RADIOHDL/libraries/technology/technology_select_pkg.vhd
+   $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
 
 
 1. Start with the Oneclick Commands:
-    python $RADIOHDL/tools/oneclick/base/modelsim_config.py -t unb1
-    python $RADIOHDL/tools/oneclick/base/quartus_config.py -t unb1
+    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb1
+    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb1
 
 
 2. Generate MMM for QSYS (select one of these revisions):
@@ -91,7 +91,7 @@ Convert .sof to .rbf:
 
 Send to LCU (capture5):
     # for example the unb1_test_10GbE revision:
-    scp $RADIOHDL/build/quartus/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.rbf capture5:~/rbf/
+    scp $RADIOHDL_WORK/build/quartus/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.rbf capture5:~/rbf/
 
     # Now login on capture5 and use pythonscript to program flash:
     cd unb1_test/tb/python
@@ -118,10 +118,10 @@ defining the pinning:
 2. unb1_test_ddr_MB_I_II_pins_constraints.tcl (pin attributes like termination etc..)
 
 The 2nd tcl file can be created with Quartus. Here are the steps:
-- generate the IP's by running: $RADIOHDL/libraries/technology/ip_stratixiv/generate-all-ip.sh
+- generate the IP's by running: $RADIOHDL_WORK/libraries/technology/ip_stratixiv/generate-all-ip.sh
 - Start synthesis in the Quartus GUI. Only the Analysis step!!
 - Then in Quartus click: Tools/TclScripts. 
-  Open the Tcl file: $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0_pin_assignments.tcl
+  Open the Tcl file: $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0_pin_assignments.tcl
   Click Run.
 - Then Continue synthesis with Fitter, or restart with Analysis.
 - Copy the generated build/unb1_test_ddr_MB_I_II.qsf file to ./designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/quartus/unb1_test_ddr_MB_I_II_pins_constraints.tcl
diff --git a/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins.tcl b/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins.tcl
index 06974891a2a2847dcc6a4fb509d9cca4dc005a93..27ecdf6551de137050de835fe1ae7336449ccc64 100644
--- a/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins.tcl
+++ b/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins.tcl
@@ -85,6 +85,6 @@ set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_RX[3]
 
 
 # -- include ddr3 pins
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
index c608a07b3776ab38b8310f29ac2f1b4088905be9..790c2fcb41f9e800bb1d4dc7df836e02006dc136 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
 
 quartus_tcl_files =
     quartus/unb1_test_10GbE_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg
index 27587a6b03abbc2efcb207c4136429d99297c5b1..fc2febb4543d8b3d8438bc6bb9f23b2eecde60a8 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
 
 quartus_tcl_files =
     quartus/unb1_test_10GbE_tx_only_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg
index 68110374db943acd84fee23b7ebb1acec157347b..78f41d558fcee7eb46f599697fb9c8361e68d57f 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 quartus_tcl_files =
     quartus/unb1_test_1GbE_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/quartus/unb1_test_1GbE_pins.tcl b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/quartus/unb1_test_1GbE_pins.tcl
index 06974891a2a2847dcc6a4fb509d9cca4dc005a93..27ecdf6551de137050de835fe1ae7336449ccc64 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/quartus/unb1_test_1GbE_pins.tcl
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/quartus/unb1_test_1GbE_pins.tcl
@@ -85,6 +85,6 @@ set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_RX[3]
 
 
 # -- include ddr3 pins
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
index 18894362a59ade0a1cdce01e052adb67e182cc38..f5dcccf80cfa68ebea0b8c3ea7b83b37ed9705b0 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
 
 
 [quartus_project_file]
@@ -28,10 +28,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 quartus_tcl_files =
     ../../quartus/unb1_test_pins.tcl
@@ -41,6 +41,6 @@ quartus_vhdl_files =
 
 quartus_qip_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_test_all/qsys_unb1_test/synthesis/qsys_unb1_test.qip
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
-    #$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+    #$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
index f37c913aa1c0ba22af45a8efe9e44768554f9cb2..8363cba5b7eff9e0815743b5626aed11aec9bf4d 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_copy_files =
     ../../src/hex hex
     
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
 
 
 [quartus_project_file]
@@ -28,10 +28,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 quartus_tcl_files =
     quartus/unb1_test_ddr_pins.tcl
@@ -41,6 +41,6 @@ quartus_vhdl_files =
 
 quartus_qip_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr/qsys_unb1_test/synthesis/qsys_unb1_test.qip
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
-    #$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+    #$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/quartus/unb1_test_ddr_pins.tcl b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/quartus/unb1_test_ddr_pins.tcl
index 65282d0ba6f1068b6f7bf80ab17e5454f7d194e2..bac6c86884452254d942b599d9730840d5c5c71f 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/quartus/unb1_test_ddr_pins.tcl
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/quartus/unb1_test_ddr_pins.tcl
@@ -25,6 +25,6 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
 
 # -- include ddr3 pins
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
index 1454028e66a05317b854a3b6b4c2e9124119d723..f768ee780f309b1a3a57ac3aa8739dbc2583fae6 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
@@ -18,7 +18,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
 
 
 [quartus_project_file]
@@ -29,10 +29,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 quartus_tcl_files =
     quartus/unb1_test_ddr_16g_MB_I_pins.tcl
@@ -42,5 +42,5 @@ quartus_vhdl_files =
 
 quartus_qip_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/quartus/unb1_test_ddr_16g_MB_I_pins.tcl b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/quartus/unb1_test_ddr_16g_MB_I_pins.tcl
index 850f27204a65741e777978b035de45f51a9834cc..e6c6cd90d5f2e13c726c577f6cd1867edf780740 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/quartus/unb1_test_ddr_16g_MB_I_pins.tcl
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/quartus/unb1_test_ddr_16g_MB_I_pins.tcl
@@ -25,5 +25,5 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
 
 # -- include ddr3 pins
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
index 0976da6a26aac4db8d8f8bdd6a9b3442d8bd129f..131abe1162f57a1b16704f75aeebb6663329cd07 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
 
 
 [quartus_project_file]
@@ -28,10 +28,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 quartus_tcl_files =
     quartus/unb1_test_ddr_pins_16g_MB_II.tcl
@@ -41,5 +41,5 @@ quartus_vhdl_files =
 
 quartus_qip_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/quartus/unb1_test_ddr_pins_16g_MB_II.tcl b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/quartus/unb1_test_ddr_pins_16g_MB_II.tcl
index e6d56bb52235271c951e6ad24dee00083315d502..f4fac0a19d69e96830c45895f14a46f9121e43b7 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/quartus/unb1_test_ddr_pins_16g_MB_II.tcl
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/quartus/unb1_test_ddr_pins_16g_MB_II.tcl
@@ -25,5 +25,5 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
 
 # -- include ddr3 pins
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
index 02b71ffe2750f79ea8799771c18e70c57665308c..3c9364d69e79fcac863e1974cc4aaf7e828abfbe 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
 
 
 [quartus_project_file]
@@ -28,10 +28,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 quartus_tcl_files =
     quartus/unb1_test_ddr_16g_MB_I_II_pins.tcl
@@ -41,5 +41,5 @@ quartus_vhdl_files =
 
 quartus_qip_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/quartus/unb1_test_ddr_16g_MB_I_II_pins.tcl b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/quartus/unb1_test_ddr_16g_MB_I_II_pins.tcl
index 65282d0ba6f1068b6f7bf80ab17e5454f7d194e2..bac6c86884452254d942b599d9730840d5c5c71f 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/quartus/unb1_test_ddr_16g_MB_I_II_pins.tcl
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/quartus/unb1_test_ddr_16g_MB_I_II_pins.tcl
@@ -25,6 +25,6 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
 
 # -- include ddr3 pins
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
index d6d700acefbd2c353eedff143a86eb0df48daf9d..2f10f4fbe89f05c8023c5aaa6017ce74f9251a09 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
 
 
 [quartus_project_file]
@@ -28,10 +28,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 quartus_tcl_files =
     quartus/unb1_test_ddr_MB_I_pins.tcl
@@ -41,5 +41,5 @@ quartus_vhdl_files =
 
 quartus_qip_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
index b1569dd161ede6e0016c80b6fbd25529ed08d300..7fe0acbd0a30d419763b330aa9d154af6bfb0a6d 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
 
 
 [quartus_project_file]
@@ -28,10 +28,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 quartus_tcl_files =
     quartus/unb1_test_ddr_MB_I_pins.tcl
@@ -41,5 +41,5 @@ quartus_vhdl_files =
 
 quartus_qip_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
index 69d6bb04c8552516134dd5a81a3a96bc32cfa79c..b0b65d13271097e25c698ac2345c25d41b288075 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
 
 
 [quartus_project_file]
@@ -27,10 +27,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 quartus_tcl_files =
     quartus/unb1_test_ddr_MB_I_II_pins.tcl
@@ -40,5 +40,5 @@ quartus_vhdl_files =
 
 quartus_qip_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/quartus/unb1_test_ddr_pins.tcl b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/quartus/unb1_test_ddr_pins.tcl
index 65282d0ba6f1068b6f7bf80ab17e5454f7d194e2..bac6c86884452254d942b599d9730840d5c5c71f 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/quartus/unb1_test_ddr_pins.tcl
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/quartus/unb1_test_ddr_pins.tcl
@@ -25,6 +25,6 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
 
 # -- include ddr3 pins
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
 
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
index 3ef8d196d4e38ef189c34edcc39585eff7151142..0e0b26f797deda2dc27141fdfa88b63ae5d707b4 100644
--- a/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
@@ -26,7 +26,7 @@ quartus_copy_files =
 #    src/hex/ hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_tcl_files =
     quartus/unb1_tr_10GbE_pins.tcl
@@ -37,4 +37,4 @@ quartus_qip_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_tr_10GbE/qsys_unb1_tr_10GbE/synthesis/qsys_unb1_tr_10GbE.qip
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc    
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc    
diff --git a/boards/uniboard1/libraries/unb1_board/hdllib.cfg b/boards/uniboard1/libraries/unb1_board/hdllib.cfg
index 3c0c0332a003d4204b90867e389caf19f8fa96ed..f9b219ceaa9478a2fb8206f4cfdcc6e9800a8ae1 100644
--- a/boards/uniboard1/libraries/unb1_board/hdllib.cfg
+++ b/boards/uniboard1/libraries/unb1_board/hdllib.cfg
@@ -43,9 +43,9 @@ synth_files =
     
     src/vhdl/unb1_board_peripherals_pkg.vhd
 
-    # For BN the $RADIOHDL/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd is 
+    # For BN the $RADIOHDL_WORK/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd is 
     # referred to directly in the apertif_unb1_bn_filterbank library.
-    # For FN a copy of $RADIOHDL/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
+    # For FN a copy of $RADIOHDL_WORK/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
     # is taken via this unb1_board library:
     src/vhdl/node_unb1_fn_terminal_db.vhd    
     
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_allpins.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_allpins.tcl
index e9a0020ecabcbcfe435232afa424f1957f95d06a..b18c31a46b325b5df7376ddc0a94f8d11c94b1c8 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_allpins.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_allpins.tcl
@@ -23,7 +23,7 @@
 # Pin assignments
 
 # -- Common
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
 
 # -- Back Node specific
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_pins.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_pins.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_pins.tcl
index 01b6b0ee2d19c7328c4a0fdee10aa91382c19702..c023237cd682a1c2125245d25499b8de0ab1d40a 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_pins.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_pins.tcl
@@ -23,10 +23,10 @@
 # Back node specific pin assignments
 
 # -- Backplane Interface
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_tr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_tr_pins.tcl
 
 # -- FN to BN Interface added 08-01-2010
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_mesh_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_mesh_pins.tcl
 
 # -- ADC Interface
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_adc_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_adc_pins.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
index 07a96e303982b1e5ffff2f2018e4a6fc59b3cc4b..fa264372aaeff6c369645f37a3d8d9bcbcd6f400 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
@@ -23,22 +23,22 @@
 # Common pin assignments for front_node and back_node
 
 # -- General: clk, pps, wdi, inta, intb
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
 
 # -- FPGA Interconnects Front-Node Back-Node
 #    Clocks only as transceiver pins are now different (08-01-2010)
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_tr_clk_pins.tcl
-#source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_tr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_tr_clk_pins.tcl
+#source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_tr_pins.tcl
 
 # -- 1GbE Control Interface
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
 
 # -- SO-DIMM Memory Banks I and II
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_ddr_I_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_ddr_II_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_ddr_I_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_ddr_II_pins.tcl
 
 # -- I2C Interface to Sensors
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
 
 # -- Other: version[1:0], id[7:0], testio[7:0]
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_allpins.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_allpins.tcl
index f2bc1b735dbb66c9ce40409744dc854d0ab6b8d3..ba55f0e9e57578902902fe4ed35b10ed48fe5cbb 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_allpins.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_allpins.tcl
@@ -23,7 +23,7 @@
 # Pin assignments
 
 # -- Common
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
 
 # -- Front Node specific
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_pins.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_pins.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_pins.tcl
index 47b4a220ec3e92ff32036fd9e019f2dadcf1dff8..afbd717cd6e5cfbc14a7e13090d8cb109923f7b1 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_pins.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_pins.tcl
@@ -23,9 +23,9 @@
 # Front node specific pin assignments
 
 # -- Front Interface (10GbE)
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_cntrl_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_cntrl_pins.tcl
 
 # -- FN to BN Mesh Interface added 08-01-2010
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_mesh_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_mesh_pins.tcl
 
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_back_pcs.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_back_pcs.tcl
index 0f53630b3a3e9e38ebe29b5c7d4310207196d882..d2a233a4719c1fe0d84182feb09bc5a0a4de2510 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_back_pcs.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_back_pcs.tcl
@@ -20,6 +20,6 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tx_back_pcs.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_rx_back_pcs.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tx_back_pcs.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_rx_back_pcs.tcl
 
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs.tcl
index 994c29136220058441fd5a12ff5b6c1625515fc8..856ec42e60f16f6d36698eddb61ff6f80d23e28a 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs.tcl
@@ -20,7 +20,7 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_clk.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_0.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_1.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_2.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_clk.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_0.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_1.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_2.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_clk.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_clk.tcl
index 4bd32910641819a9782b76843b1ff83c11053038..22f4d234b233f608187821f11f772e71fc37d591 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_clk.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_clk.tcl
@@ -20,7 +20,7 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_cntrl_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_cntrl_pins.tcl
 
 set_location_assignment PIN_AA2 -to SA_CLK
 set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SA_CLK
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_mesh_pcs.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_mesh_pcs.tcl
index ab9c957cf804e9e6867f7fb126b3a278592c0a6d..926e243c89da0a81643c08371dd4731e6727cb25 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_mesh_pcs.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_mesh_pcs.tcl
@@ -20,5 +20,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tx_mesh_pcs.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_rx_mesh_pcs.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tx_mesh_pcs.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_rx_mesh_pcs.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
index 4e2396ba38fcbc79523e9e1198763e271f1b2475..35e67d8844d3cff06efea90b10f54344be0b861d 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+++ b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
@@ -22,7 +22,7 @@
 # This QSF is sourced by other design QSF files.
 # ==============================================
 # Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
 
 # Device:
 set_global_assignment -name FAMILY "Stratix IV"
@@ -49,7 +49,7 @@ set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCS128
 if { [info exists ::env(UNB_COMPILE_STAMPS) ] } {
   set_parameter -name g_stamp_date [clock format [clock seconds] -format {%Y%m%d}]
   set_parameter -name g_stamp_time [clock format [clock seconds] -format {%H%M%S}]
-  post_message -type info "RADIOHDL: using SVN revision $::env(RADIOHDL_SVN_REVISION)"
-  set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_SVN_REVISION)] ""]
+  post_message -type info "RADIOHDL: using SVN revision $::env(RADIOHDL_GIT_REVISION)"
+  set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_GIT_REVISION)] ""]
 }
 
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf
index 47fbc4afdca37879f8c0837c462ce222430196cb..4d46b5409c278f7781b6bc82c813b022e32cd960 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf
+++ b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf
@@ -22,7 +22,7 @@
 # This QSF is sourced by other design QSF files.
 # ==============================================
 # Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
 
 # This file contains includes that should be added to another project QSF before 
 # user contraints and/or QIPs are added.
@@ -48,13 +48,13 @@ set_global_assignment -name USE_CONFIGURATION_DEVICE ON
 set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCS128
 
 # Timing constraints
-set_global_assignment -name SDC_FILE $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.sdc
+set_global_assignment -name SDC_FILE $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.sdc
 
 # Pass compile stamps as generics (passed to top-level when $UNB_COMPILE_STAMPS is set)
 if { [info exists ::env(UNB_COMPILE_STAMPS) ] } {
   set_parameter -name g_stamp_date [clock format [clock seconds] -format {%Y%m%d}]
   set_parameter -name g_stamp_time [clock format [clock seconds] -format {%H%M%S}]
-  post_message -type info "RADIOHDL: using SVN revision $::env(RADIOHDL_SVN_REVISION)"
-  set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_SVN_REVISION)] ""]
+  post_message -type info "RADIOHDL: using SVN revision $::env(RADIOHDL_GIT_REVISION)"
+  set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_GIT_REVISION)] ""]
 }
 
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.qsf b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.qsf
index 55045186351f1dd967908a36f2cb8c0d118e7cf9..821a28fa2deba7dca47d3701f1833fe25f2969f2 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.qsf
+++ b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.qsf
@@ -22,12 +22,12 @@
 # This QSF is sourced by other design QSF files.
 # ==============================================
 # Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
 #
 # This file contains includes that should be added to another project QSF after certain
 # user contraints (DDR3 timing constraints for instance) have been included. 
 
 # Post Timing constraints
-set_global_assignment -name SDC_FILE $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.sdc
+set_global_assignment -name SDC_FILE $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.sdc
 
 
diff --git a/boards/uniboard2/designs/unb2_led/hdllib.cfg b/boards/uniboard2/designs/unb2_led/hdllib.cfg
index b827bc6b809c0afd8cb8cd88e474a3fb45aee3b4..31c102a23c0eef5d75482debc578759a3d2955ce 100644
--- a/boards/uniboard2/designs/unb2_led/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_led/hdllib.cfg
@@ -20,10 +20,10 @@ synth_top_level_entity =
 quartus_copy_files =
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
 
 quartus_tcl_files =
     quartus/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_led/quartus/unb2_minimal_pins.tcl b/boards/uniboard2/designs/unb2_led/quartus/unb2_minimal_pins.tcl
index ac10dfbc4ce169310ce4468b18a12c973f03f23a..23bcf027b1639fd7876c128c82f3bd7f83f8ac87 100644
--- a/boards/uniboard2/designs/unb2_led/quartus/unb2_minimal_pins.tcl
+++ b/boards/uniboard2/designs/unb2_led/quartus/unb2_minimal_pins.tcl
@@ -19,4 +19,4 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_minimal/doc/README b/boards/uniboard2/designs/unb2_minimal/doc/README
index 215cf4e673f8029dec2c08a38f044707624ebe84..d4c4b3ef19935eaddc50b6dd1d38bcd328db7e9c 100644
--- a/boards/uniboard2/designs/unb2_minimal/doc/README
+++ b/boards/uniboard2/designs/unb2_minimal/doc/README
@@ -2,17 +2,17 @@ Quick steps to compile and use design [unb2_minimal] in RadionHDL
 -----------------------------------------------------------------
 
 -> In case of a new installation, the IP's have to be generated for Arria10.
-   In the: $RADIOHDL/libraries/technology/ip_arria10
+   In the: $RADIOHDL_WORK/libraries/technology/ip_arria10
    directory; run the bash script: ./generate-all-ip.sh
 
 -> For compilation it might be necessary to check the .vhd file:
-   $RADIOHDL/libraries/technology/technology_select_pkg.vhd
+   $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
 
 
 
 1. Start with the Oneclick Commands:
-    python $RADIOHDL/tools/oneclick/base/modelsim_config.py -t unb2
-    python $RADIOHDL/tools/oneclick/base/quartus_config.py -t unb2
+    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2
+    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2
 
 
 2. Generate MMM for QSYS:
@@ -105,7 +105,7 @@ Then program the .JIC file (output_file.jic) to EPCS flash:
 - make sure the 4 fpga icons have the device 10AX115U4F45ES
 - right-click each fpga icon and attach flash device EPCQL1024
 - right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
-  (in $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus)
+  (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus)
 - right-click each EPCQL1024 and change file from <none> to output_file.jic
 - select click each Program/Configure radiobutton
 - click start and wait for 'Successful'
diff --git a/boards/uniboard2/designs/unb2_minimal/hdllib.cfg b/boards/uniboard2/designs/unb2_minimal/hdllib.cfg
index 438f691f82a9fe0874661f988705ea080db1bd3e..3c8171266d0b37a55e93d812322c11ee8eda347e 100644
--- a/boards/uniboard2/designs/unb2_minimal/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_minimal/hdllib.cfg
@@ -23,10 +23,10 @@ quartus_copy_files =
     quartus/qsys_unb2_minimal.qsys .
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
 
 quartus_tcl_files =
     quartus/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_minimal/quartus/unb2_minimal_pins.tcl b/boards/uniboard2/designs/unb2_minimal/quartus/unb2_minimal_pins.tcl
index ac10dfbc4ce169310ce4468b18a12c973f03f23a..23bcf027b1639fd7876c128c82f3bd7f83f8ac87 100644
--- a/boards/uniboard2/designs/unb2_minimal/quartus/unb2_minimal_pins.tcl
+++ b/boards/uniboard2/designs/unb2_minimal/quartus/unb2_minimal_pins.tcl
@@ -19,4 +19,4 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/doc/README b/boards/uniboard2/designs/unb2_test/doc/README
index 2b843fa4516f086599f9cfcc47f6eb9cd52cd735..5c311198c8fb13862603499e0706edad56f58ab6 100644
--- a/boards/uniboard2/designs/unb2_test/doc/README
+++ b/boards/uniboard2/designs/unb2_test/doc/README
@@ -25,18 +25,18 @@ The following revisions are available for unb2_test (see the directories in ../r
 
 
 -> In case of a new installation, the IP's have to be generated for Arria10. 
-   In the: $RADIOHDL/libraries/technology/ip_arria10 
+   In the: $RADIOHDL_WORK/libraries/technology/ip_arria10 
    directory; run the bash script: ./generate-all-ip.sh
 
 -> For compilation it might be necessary to check the .vhd file:
-   $RADIOHDL/libraries/technology/technology_select_pkg.vhd
+   $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
 
 
 
 
 1. Start with the Oneclick Commands:
-    python $RADIOHDL/tools/oneclick/base/modelsim_config.py -t unb2
-    python $RADIOHDL/tools/oneclick/base/quartus_config.py -t unb2
+    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2
+    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2
 
 
 2. Generate MMM for QSYS (select one of these revisions):
@@ -117,7 +117,7 @@ Then program the .JIC file (output_file.jic) to EPCS flash:
 - make sure the 4 fpga icons have the device 10AX115U4F45ES
 - right-click each fpga icon and attach flash device EPCQL1024
 - right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
-  (in $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus)
+  (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus)
 - right-click each EPCQL1024 and change file from <none> to output_file.jic
 - select click each Program/Configure radiobutton
 - click start and wait for 'Successful'
diff --git a/boards/uniboard2/designs/unb2_test/quartus/unb2_test_pins.tcl b/boards/uniboard2/designs/unb2_test/quartus/unb2_test_pins.tcl
index a28b05005ce0c22f46b9d6a62667ddc4624baf29..7df88096be123780f90fb3b696632aa8be80402c 100644
--- a/boards/uniboard2/designs/unb2_test/quartus/unb2_test_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/quartus/unb2_test_pins.tcl
@@ -19,7 +19,7 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_10GbE_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
 
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
index 593d274985331f1c519881cc820d1f8bd1e0d380..2835bf9b43aa738805850d4feb48a00db9208ebd 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
@@ -44,11 +44,11 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
 
 quartus_sdc_files =
     quartus/unb2_test_10GbE.sdc
-    $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
 
 quartus_tcl_files =
     quartus/unb2_test_10GbE_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/quartus/unb2_test_10GbE_pins.tcl b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/quartus/unb2_test_10GbE_pins.tcl
index 1e0d2cdc832690f03e1cb714092a9306a5539635..e14bd851bb3d3458c1a4d10dfb7bdc0f3a7b3fe7 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/quartus/unb2_test_10GbE_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/quartus/unb2_test_10GbE_pins.tcl
@@ -19,5 +19,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_10GbE_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
index b8c824fe2630e5ed035cdebd2cc67710d4fa82b8..a5ce4f51a9f44e307e3541811430fdce8d8bca12 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
 
 quartus_tcl_files =
     quartus/unb2_test_1GbE_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/quartus/unb2_test_1GbE_pins.tcl b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/quartus/unb2_test_1GbE_pins.tcl
index ac10dfbc4ce169310ce4468b18a12c973f03f23a..23bcf027b1639fd7876c128c82f3bd7f83f8ac87 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/quartus/unb2_test_1GbE_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/quartus/unb2_test_1GbE_pins.tcl
@@ -19,4 +19,4 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
index ac49ea9924975b298f8dde67bcbba84a6bc19828..00625f07ebe1be9b0d076d305d830d99107f4d98 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
@@ -49,11 +49,11 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
 
 quartus_sdc_files =
     quartus/unb2_test_10GbE.sdc
-    $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
 
 quartus_tcl_files =
     quartus/unb2_test_all_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/quartus/unb2_test_all_pins.tcl b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/quartus/unb2_test_all_pins.tcl
index e2c6e6d7aecc692f84093e0e92da7e53747b2b71..f979adc2ee27b8dc6aca7f6e739fa141e5005e2f 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/quartus/unb2_test_all_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/quartus/unb2_test_all_pins.tcl
@@ -19,6 +19,6 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_10GbE_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
index 1dfd4626829c3a064c5f3dec4280f4c2d1ffa7b6..67f20d9e4fcb9fc1243fc6df6d57e79e3695f520 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
@@ -22,7 +22,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl    
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl    
 
 
 [quartus_project_file]
@@ -33,7 +33,7 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
 
 quartus_qip_files =
     $HDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_I/qsys_unb2_test/synthesis/qsys_unb2_test.qip
@@ -42,5 +42,5 @@ quartus_tcl_files =
     quartus/unb2_test_ddr_MB_I_pins.tcl
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
 
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/quartus/unb2_test_ddr_MB_I_pins.tcl b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/quartus/unb2_test_ddr_MB_I_pins.tcl
index 83eeedee0b6b9e9797b11764a286b93f6182fbd4..1830b7b880bf62e41a8118175db3260dbe2407f9 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/quartus/unb2_test_ddr_MB_I_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/quartus/unb2_test_ddr_MB_I_pins.tcl
@@ -19,5 +19,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
index 328ae2de92264f63a33798f7d228f8c808e17536..34036c3461684a30fa3f61fed6045a143ccf7bfd 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
@@ -22,7 +22,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
     
 
 [quartus_project_file]
@@ -33,7 +33,7 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
 
 quartus_qip_files =
     $HDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_II/qsys_unb2_test/synthesis/qsys_unb2_test.qip
@@ -42,5 +42,5 @@ quartus_tcl_files =
     quartus/unb2_test_ddr_MB_II_pins.tcl
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
 
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/quartus/unb2_test_ddr_MB_II_pins.tcl b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/quartus/unb2_test_ddr_MB_II_pins.tcl
index 83eeedee0b6b9e9797b11764a286b93f6182fbd4..1830b7b880bf62e41a8118175db3260dbe2407f9 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/quartus/unb2_test_ddr_MB_II_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/quartus/unb2_test_ddr_MB_II_pins.tcl
@@ -19,5 +19,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
index 302047e4f4b88f550b660e40fc404da2f9cee3ad..a42629b841592f4cf3dd34787b94e05486033c1a 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
@@ -22,7 +22,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
     
 
 [quartus_project_file]
@@ -33,7 +33,7 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
 
 quartus_qip_files =
     $HDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_I_II/qsys_unb2_test/synthesis/qsys_unb2_test.qip
@@ -42,5 +42,5 @@ quartus_tcl_files =
     quartus/unb2_test_ddr_MB_I_II_pins.tcl
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
 
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/quartus/unb2_test_ddr_MB_I_II_pins.tcl b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/quartus/unb2_test_ddr_MB_I_II_pins.tcl
index 83eeedee0b6b9e9797b11764a286b93f6182fbd4..1830b7b880bf62e41a8118175db3260dbe2407f9 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/quartus/unb2_test_ddr_MB_I_II_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/quartus/unb2_test_ddr_MB_I_II_pins.tcl
@@ -19,5 +19,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
index 0af0858dce16e6ad21a9d049d5825bd313b254e3..94e14c4340bb227b0f9498d0fe4f79d587cd5a69 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
@@ -26,7 +26,7 @@ PACKAGE qsys_unb2_test_pkg IS
 
   -----------------------------------------------------------------------------
   -- this component declaration is copy-pasted from Quartus QSYS builder generated file:
-  -- $RADIOHDL/build/unb2/quartus/unb2_test_ddr/qsys_unb2_test/sim/qsys_unb2_test.vhd
+  -- $RADIOHDL_WORK/build/unb2/quartus/unb2_test_ddr/qsys_unb2_test/sim/qsys_unb2_test.vhd
   -----------------------------------------------------------------------------
   
     component qsys_unb2_test is
diff --git a/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf b/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
index 577051cd04ca496483104ac833348cdca94c10c4..072fd6fb681994a3c4256ebd8cf33ccb3c56dde2 100644
--- a/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+++ b/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
@@ -22,7 +22,7 @@
 # This QSF is sourced by other design QSF files.
 # ==============================================
 # Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
 
 # Device:
 set_global_assignment -name FAMILY "Arria 10"
@@ -107,7 +107,7 @@ set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_1
 if { [info exists ::env(UNB_COMPILE_STAMPS) ] } {
   set_parameter -name g_stamp_date [clock format [clock seconds] -format {%Y%m%d}]
   set_parameter -name g_stamp_time [clock format [clock seconds] -format {%H%M%S}]
-  post_message -type info "RADIOHDL: using SVN $::env(RADIOHDL_SVN_REVISION)"
-  set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_SVN_REVISION)] ""] 
+  post_message -type info "RADIOHDL: using SVN $::env(RADIOHDL_GIT_REVISION)"
+  set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_GIT_REVISION)] ""] 
 }
 
diff --git a/boards/uniboard2a/designs/altera_ref_designs/ddr4/doc/README_ddr4.txt b/boards/uniboard2a/designs/altera_ref_designs/ddr4/doc/README_ddr4.txt
index 4a32ab051e4d8f7a034b8ff8bdd4177ee8060e41..7fd2f086e5b92f6d8a6b3579d0045608126d316a 100644
--- a/boards/uniboard2a/designs/altera_ref_designs/ddr4/doc/README_ddr4.txt
+++ b/boards/uniboard2a/designs/altera_ref_designs/ddr4/doc/README_ddr4.txt
@@ -143,7 +143,7 @@ Quartus IP catalog "Arria10 External Memory Interface" fill in:
 
   run:
   cd emif_0_example_design
-  . ${RADIOHDL}/tools/quartus/set_quartus unb2 && quartus_sh -t make_qii_design.tcl
+  . ${RADIOHDL_GEAR}/quartus/set_quartus unb2 && quartus_sh -t make_qii_design.tcl
 
   add to qii/ed_synth.qsf:
   source ../../unb2_pins_ed_synth.tcl
diff --git a/boards/uniboard2a/designs/unb2a_heater/doc/README.txt b/boards/uniboard2a/designs/unb2a_heater/doc/README.txt
index 99553f4ac7a77fd324cfd13ef0dd778db0690c02..45d88bd21b9f2bd7d296df1929051fe45efe5a7b 100644
--- a/boards/uniboard2a/designs/unb2a_heater/doc/README.txt
+++ b/boards/uniboard2a/designs/unb2a_heater/doc/README.txt
@@ -2,17 +2,17 @@ Quick steps to compile and use design [unb2a_heater] in RadionHDL
 ------------------------------------------------------------------
 
 -> In case of a new installation, the IP's have to be generated for Arria10.
-   In the: $RADIOHDL/libraries/technology/ip_arria10_e3sge3
+   In the: $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3
    directory; run the bash script: ./generate-all-ip.sh
 
 -> For compilation it might be necessary to check the .vhd file:
-   $RADIOHDL/libraries/technology/technology_select_pkg.vhd
+   $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
 
 
 
 1. Start with the Oneclick Commands:
-    python $RADIOHDL/tools/oneclick/base/modelsim_config.py -t unb2a
-    python $RADIOHDL/tools/oneclick/base/quartus_config.py -t unb2a
+    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2a
+    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2a
 
 
 2. Generate MMM for QSYS:
@@ -107,7 +107,7 @@ Then program the .JIC file (output_file.jic) to EPCS flash:
 - make sure the 4 fpga icons have the device 10AX115U4F45ES
 - right-click each fpga icon and attach flash device EPCQL1024
 - right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
-  (in $RADIOHDL/boards/uniboard2/libraries/unb2a_board/quartus)
+  (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2a_board/quartus)
 - right-click each EPCQL1024 and change file from <none> to output_file.jic
 - select click each Program/Configure radiobutton
 - click start and wait for 'Successful'
diff --git a/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg b/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg
index 3a56f16b72e61e3aa5ee2ed96153cc6916bc1a4a..2c8fffa2567b94f4373c5b160b39b0a79d10acad 100644
--- a/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg
@@ -23,10 +23,10 @@ quartus_copy_files =
     quartus/qsys_unb2a_heater.qsys .
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
 
 quartus_tcl_files =
     quartus/unb2a_heater_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_heater/quartus/unb2a_heater_pins.tcl b/boards/uniboard2a/designs/unb2a_heater/quartus/unb2a_heater_pins.tcl
index f0e1fcbcc2838bca140bbe67dfdcb1c17ac639ec..3374b678b991559244f05d0b42f393cde9f1c345 100644
--- a/boards/uniboard2a/designs/unb2a_heater/quartus/unb2a_heater_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_heater/quartus/unb2a_heater_pins.tcl
@@ -19,4 +19,4 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_led/hdllib.cfg b/boards/uniboard2a/designs/unb2a_led/hdllib.cfg
index b02941d9d7053d1b7f6870d07711a78c449dc14b..9060d3ba0226850dfcc6b7d0a48cf9b8c54d9be0 100644
--- a/boards/uniboard2a/designs/unb2a_led/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_led/hdllib.cfg
@@ -20,10 +20,10 @@ synth_top_level_entity =
 quartus_copy_files =
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
 
 quartus_tcl_files =
     quartus/unb2a_minimal_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_led/quartus/unb2a_minimal_pins.tcl b/boards/uniboard2a/designs/unb2a_led/quartus/unb2a_minimal_pins.tcl
index f0e1fcbcc2838bca140bbe67dfdcb1c17ac639ec..3374b678b991559244f05d0b42f393cde9f1c345 100644
--- a/boards/uniboard2a/designs/unb2a_led/quartus/unb2a_minimal_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_led/quartus/unb2a_minimal_pins.tcl
@@ -19,4 +19,4 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt b/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
index 76b19ccab70672452c443ede6553c37aa43fa764..552ed433c518889dfce99210f34f3a5f342229e3 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
+++ b/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
@@ -2,19 +2,19 @@ Quick steps to compile and use design [unb2a_minimal] in RadionHDL
 ------------------------------------------------------------------
 
 -> In case of a new installation, the IP's have to be generated for Arria10.
-   In the: $RADIOHDL/libraries/technology/ip_arria10_e3sge3
+   In the: $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3
    directory; run the bash script: ./generate-all-ip.sh
    -> The TSE IP gives a lot of critical warnings. To fix them, run this patch:
-      cd $RADIOHDL/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
+      cd $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
       ./run_patch.sh
 
 -> In case of a fresh compilation, delete the build directory.
-    rm -r $RADIOHDL/build
+    rm -r $RADIOHDL_WORK/build
 
 
 1. Start with the Oneclick Commands:
-    python $RADIOHDL/tools/oneclick/base/modelsim_config.py -t unb2a
-    python $RADIOHDL/tools/oneclick/base/quartus_config.py -t unb2a
+    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2a
+    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2a
 
 
 2. Generate MMM for QSYS:
@@ -63,7 +63,7 @@ In case of needing the Quartus GUI for inspection (this starts the Quartus 15.1
 ----------------
 Using JTAG: Start the Quartus GUI and open: tools->programmer.
             Then click auto-detect; (click 4x ok)
-            Use 'change file' to select the correct .sof file (in $RADIOHDL/build/unb2a/quartus/unb2a_minimal) for each FPGA
+            Use 'change file' to select the correct .sof file (in $RADIOHDL_WORK/build/unb2a/quartus/unb2a_minimal) for each FPGA
             Select the FPGA(s) which has to be programmed
             Click 'start'
 Using EPCS: See step 6 below.
@@ -98,7 +98,7 @@ For generating a Factory image .RBF file:
 
     run_rbf unb2a --unb2_factory unb2a_minimal
 
-The .RBF file is now in $RADIOHDL/build/unb2a/quartus/unb2a_minimal
+The .RBF file is now in $RADIOHDL_WORK/build/unb2a/quartus/unb2a_minimal
 Now copy the .RBF file to the LCU host with 'scp'
 
 (b)
@@ -109,7 +109,7 @@ Program User image:
 Program Factory image:
     python util_epcs.py --unb 1 --fn 0 -n 3 -s unb2a_minimal.rbf
 
--> For extra info on RBF files on Uniboard2, see: $RADIOHDL/libraries/io/epcs/doc/README.txt
+-> For extra info on RBF files on Uniboard2, see: $RADIOHDL_WORK/libraries/io/epcs/doc/README.txt
 
 To start the User image:
     python util_remu.py --unb 1 --fn 0 -n 6  # ignore timeout error
@@ -146,7 +146,7 @@ Then program the .JIC file (unb2a_minimal.jic) to EPCS flash:
 
 (*1) When error select correct SFL (serial flash loader) from Altera service request for each FPGA:
      right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
-     (in $RADIOHDL/boards/uniboard2/libraries/unb2a_board/quartus)
+     (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2a_board/quartus)
 
 
 7.
diff --git a/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg b/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg
index ddecca0dea6129171b29cb05736289b24833a43f..c569e3b68489b43f8812a797fc3f5d81fb323c76 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg
@@ -23,10 +23,10 @@ quartus_copy_files =
     quartus/qsys_unb2a_minimal.qsys .
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
 
 quartus_tcl_files =
     quartus/unb2a_minimal_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_minimal/quartus/unb2a_minimal_pins.tcl b/boards/uniboard2a/designs/unb2a_minimal/quartus/unb2a_minimal_pins.tcl
index f0e1fcbcc2838bca140bbe67dfdcb1c17ac639ec..3374b678b991559244f05d0b42f393cde9f1c345 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/quartus/unb2a_minimal_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_minimal/quartus/unb2a_minimal_pins.tcl
@@ -19,4 +19,4 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/doc/README.txt b/boards/uniboard2a/designs/unb2a_test/doc/README.txt
index 316b8f22bb7e447cd3cf513f2d9389e0efa60565..4d8244dfcf3ee35e771167de7beabdd10aa47134 100644
--- a/boards/uniboard2a/designs/unb2a_test/doc/README.txt
+++ b/boards/uniboard2a/designs/unb2a_test/doc/README.txt
@@ -25,17 +25,17 @@ The following revisions are available for unb2a_test (see the directories in ../
 
 
 -> In case of a new installation, the IP's have to be generated for Arria10. 
-   In the: $RADIOHDL/libraries/technology/ip_arria10_e3sge3
+   In the: $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3
    directory; run the bash script: ./generate-all-ip.sh
    -> The TSE IP gives a lot of critical warnings. To fix them, run this patch:
-      cd $RADIOHDL/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
+      cd $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
       ./run_patch.sh
 
 
 
 1. Start with the Oneclick Commands:
-    python $RADIOHDL/tools/oneclick/base/modelsim_config.py -t unb2a
-    python $RADIOHDL/tools/oneclick/base/quartus_config.py -t unb2a
+    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2a
+    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2a
 
 
 2. Generate MMM for QSYS (select one of these revisions):
@@ -80,7 +80,7 @@ load the project now from the build directory.
 ----------------
 Using JTAG: Start the Quartus GUI and open: tools->programmer.
             Then click auto-detect; (click 4x ok)
-            Use 'change file' to select the correct .sof file (in $RADIOHDL/build/unb2a/quartus/unb2a_test_...) for each FPGA
+            Use 'change file' to select the correct .sof file (in $RADIOHDL_WORK/build/unb2a/quartus/unb2a_test_...) for each FPGA
             Select the FPGA(s) which has to be programmed
             Click 'start'
 Using EPCS: See step 6 below.
@@ -106,7 +106,7 @@ For generating a Factory image .RBF file:
 
     run_rbf unb2a --unb2_factory unb2a_test_[revision]
 
-The .RBF file is now in $RADIOHDL/build/unb2a/quartus/unb2a_test_[revision]
+The .RBF file is now in $RADIOHDL_WORK/build/unb2a/quartus/unb2a_test_[revision]
 Now copy the .RBF file to the LCU host with 'scp'
 
 (b)
@@ -117,7 +117,7 @@ Program User image:
 Program Factory image:
     python util_epcs.py --unb 1 --fn 0 -n 3 -s unb2a_test_[revision].rbf
 
--> For extra info on RBF files on Uniboard2, see: $RADIOHDL/libraries/io/epcs/doc/README.txt
+-> For extra info on RBF files on Uniboard2, see: $RADIOHDL_WORK/libraries/io/epcs/doc/README.txt
 
 To start the User image:
     python util_remu.py --unb 1 --fn 0 -n 6  # ignore timeout error
@@ -151,7 +151,7 @@ Then program the .JIC file (output_file.jic) to EPCS flash:
 
 (*1) When error select correct SFL (serial flash loader) from Altera service request for each FPGA:
      right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
-     (in $RADIOHDL/boards/uniboard2/libraries/unb2a_board/quartus)
+     (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2a_board/quartus)
 
 
 7.
diff --git a/boards/uniboard2a/designs/unb2a_test/quartus/unb2a_test_pins.tcl b/boards/uniboard2a/designs/unb2a_test/quartus/unb2a_test_pins.tcl
index 553162a115fe12ddb46f6243ecf76ddd3ad925ca..c0483d1585c6903e1a6ef07e604873f630100286 100644
--- a/boards/uniboard2a/designs/unb2a_test/quartus/unb2a_test_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/quartus/unb2a_test_pins.tcl
@@ -19,7 +19,7 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
 
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
index 51f4a2012d864a3c05fe202e296b804ab0499116..f9c0677edd282d054aec4574f72e2c5bca6cbdf6 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
@@ -44,14 +44,14 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
 
 quartus_sdc_pre_files =
     quartus/unb2a_test_10GbE.sdc
-    $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board_pre.sdc
+    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board_pre.sdc
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
 
 quartus_tcl_files =
     quartus/unb2a_test_10GbE_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/quartus/unb2a_test_10GbE_pins.tcl b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/quartus/unb2a_test_10GbE_pins.tcl
index 9f0f3d463eb4c86283ab81554712b6876bfe7a1f..7e83e4b07c8a8ecd7eae37b78eaf47d226a87dfd 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/quartus/unb2a_test_10GbE_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/quartus/unb2a_test_10GbE_pins.tcl
@@ -19,5 +19,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
index 088553ae7971698f325e22a397115fb3c9254629..cbc5c0292e5654e754366b910d623ac62f99f140 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
 
 quartus_tcl_files =
     quartus/unb2a_test_1GbE_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/quartus/unb2a_test_1GbE_pins.tcl b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/quartus/unb2a_test_1GbE_pins.tcl
index f0e1fcbcc2838bca140bbe67dfdcb1c17ac639ec..3374b678b991559244f05d0b42f393cde9f1c345 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/quartus/unb2a_test_1GbE_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/quartus/unb2a_test_1GbE_pins.tcl
@@ -19,4 +19,4 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
index 7e6963de8ffb106d55c32781033cd773de58c319..68466090d055001f770faeb9b4985170f164f434 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
@@ -50,11 +50,11 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
 
 quartus_sdc_files =
     quartus/unb2a_test_10GbE.sdc
-    $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
 
 quartus_tcl_files =
     quartus/unb2a_test_all_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/quartus/unb2a_test_all_pins.tcl b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/quartus/unb2a_test_all_pins.tcl
index e49fd3d11ad9b6bc63bc7bc0a22e070c75f5e15f..91f930b06b77c363b07479fb494161c03431cd09 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/quartus/unb2a_test_all_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/quartus/unb2a_test_all_pins.tcl
@@ -19,6 +19,6 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
index fc2357bf492e3317bd752a08425ed08f3529321e..a7a4643277e802d9ec2e9e418898cc6cd935b93d 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
@@ -23,7 +23,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
 
 
 [quartus_project_file]
@@ -34,7 +34,7 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
 
 quartus_qip_files =
     $HDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_I/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
@@ -43,5 +43,5 @@ quartus_tcl_files =
     quartus/unb2a_test_ddr_MB_I_pins.tcl
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
 
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/quartus/unb2a_test_ddr_MB_I_pins.tcl b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/quartus/unb2a_test_ddr_MB_I_pins.tcl
index c95abcfa28bbbeb42da674b56c1d02e80fe284bb..edf1e7422d1190e0e7b53dc03940471734b2bf3c 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/quartus/unb2a_test_ddr_MB_I_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/quartus/unb2a_test_ddr_MB_I_pins.tcl
@@ -19,5 +19,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
index 2859b2ec94b0b93285b88a826040c587c942e0e7..4030938bace3cdce3e0aca36d45776687c399ad2 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
@@ -23,7 +23,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
     
 
 [quartus_project_file]
@@ -34,7 +34,7 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
 
 quartus_qip_files =
     $HDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_II/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
@@ -43,5 +43,5 @@ quartus_tcl_files =
     quartus/unb2a_test_ddr_MB_II_pins.tcl
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
 
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/quartus/unb2a_test_ddr_MB_II_pins.tcl b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/quartus/unb2a_test_ddr_MB_II_pins.tcl
index c95abcfa28bbbeb42da674b56c1d02e80fe284bb..edf1e7422d1190e0e7b53dc03940471734b2bf3c 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/quartus/unb2a_test_ddr_MB_II_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/quartus/unb2a_test_ddr_MB_II_pins.tcl
@@ -19,5 +19,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
index b80f43f07551c36c7561784c62a590552485b9ea..8b25ef236f7fb6309aa6ad9a9a9d838c4f1820ba 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
@@ -23,7 +23,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
     
 
 [quartus_project_file]
@@ -34,7 +34,7 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
 
 quartus_qip_files =
     $HDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_I_II/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
@@ -43,5 +43,5 @@ quartus_tcl_files =
     quartus/unb2a_test_ddr_MB_I_II_pins.tcl
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
 
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/quartus/unb2a_test_ddr_MB_I_II_pins.tcl b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/quartus/unb2a_test_ddr_MB_I_II_pins.tcl
index c95abcfa28bbbeb42da674b56c1d02e80fe284bb..edf1e7422d1190e0e7b53dc03940471734b2bf3c 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/quartus/unb2a_test_ddr_MB_I_II_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/quartus/unb2a_test_ddr_MB_I_II_pins.tcl
@@ -19,5 +19,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
index f154ef668eea5fcbf738605b5dba6591fea06a5e..2f6c0284ea27441c28ec06739627665859e87e86 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
@@ -26,7 +26,7 @@ PACKAGE qsys_unb2a_test_pkg IS
 
   -----------------------------------------------------------------------------
   -- this component declaration is copy-pasted from Quartus QSYS builder generated file:
-  -- $RADIOHDL/build/unb2a/quartus/unb2a_test_ddr/qsys_unb2a_test/sim/qsys_unb2a_test.vhd
+  -- $RADIOHDL_WORK/build/unb2a/quartus/unb2a_test_ddr/qsys_unb2a_test/sim/qsys_unb2a_test.vhd
   -----------------------------------------------------------------------------
   
     component qsys_unb2a_test is
diff --git a/boards/uniboard2a/doc/unb2a_release_notes.txt b/boards/uniboard2a/doc/unb2a_release_notes.txt
index d2b4fc41986026759bb81032038c30dcac1110ad..18a1851942d8120cc527dd467a50a9df6d12f9a8 100644
--- a/boards/uniboard2a/doc/unb2a_release_notes.txt
+++ b/boards/uniboard2a/doc/unb2a_release_notes.txt
@@ -10,15 +10,15 @@ Date: Tue Apr 26 11:25:24 CEST 2016
   This means that the firmware already flashed still shows a Uniboard 1 version in the python scripts.
   -> So it will be good to re-flash unb2a_minimal. 
   The new .rbf file (factory image) is added in the build directory and the excisting .jic file is removed.
-  Look at  $RADIOHDL/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt  Section 6b how to flash
-  Also see $RADIOHDL/boards/uniboard2a/designs/unb2a_minimal/build/README.txt
+  Look at  $RADIOHDL_WORK/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt  Section 6b how to flash
+  Also see $RADIOHDL_WORK/boards/uniboard2a/designs/unb2a_minimal/build/README.txt
 
 
 Date: Mon Apr 25 11:29:31 CEST 2016
 
 - Added functionality to write to EPCQ flash.
   Now it is possible to write a Factory- and User image
-  See $RADIOHDL/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
+  See $RADIOHDL_WORK/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
   for instructions how to prepare images and how to write them in the flash
 - Added functionality to perform Load from Flash with the REMU (remote update)
 
@@ -32,15 +32,15 @@ In this directory the following designs can be found:
 - unb2a_minimal
   a minimal design which is also programmed in the onboard EPCS flash.
 
-  See: $RADIOHDL/boards/uniboard2a/designs/unb2a_minimal/doc/ASTRON_unb2a_minimal.pdf
-       $RADIOHDL/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
+  See: $RADIOHDL_WORK/boards/uniboard2a/designs/unb2a_minimal/doc/ASTRON_unb2a_minimal.pdf
+       $RADIOHDL_WORK/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
 
 
 
 - unb2_test
   a test design with revisions testing each subsystem. Currently only the DDR4.
 
-  See: $RADIOHDL/boards/uniboard2a/designs/unb2a_test/doc/README.txt
+  See: $RADIOHDL_WORK/boards/uniboard2a/designs/unb2a_test/doc/README.txt
 
 
 
@@ -49,7 +49,7 @@ In this directory the following designs can be found:
   an Altera reference design originally downloaded from
   www.alterawiki.com/wiki/High_Speed_Transceiver_Demo_Designs_For_Current_and_Older_Families
   
-  See: $RADIOHDL/boards/uniboard2a/designs/altera_ref_designs/Arria10_SIBoard_24Ch_3_Phy_TTK_ES3/doc/*
+  See: $RADIOHDL_WORK/boards/uniboard2a/designs/altera_ref_designs/Arria10_SIBoard_24Ch_3_Phy_TTK_ES3/doc/*
 
 
 
@@ -58,9 +58,9 @@ In this directory the following designs can be found:
   ddr4_micron46_mbIIskew
   based on Altera's reference design, autogenerated from the QSYS IP-catalog in Quartus
 
-  See: $RADIOHDL/boards/uniboard2a/designs/altera_ref_designs/ddr4/doc/*
-       $RADIOHDL/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/README.txt
-       $RADIOHDL/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/README.txt
+  See: $RADIOHDL_WORK/boards/uniboard2a/designs/altera_ref_designs/ddr4/doc/*
+       $RADIOHDL_WORK/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/README.txt
+       $RADIOHDL_WORK/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/README.txt
 
 
 
diff --git a/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf b/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
index bef3dcdee8b8b7bcd7b374b7cddd596d275e15e2..422aa619aa3ef2f7d8647125cce8b59e76dc424a 100644
--- a/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+++ b/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
@@ -22,7 +22,7 @@
 # This QSF is sourced by other design QSF files.
 # ==============================================
 # Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
 
 # new in Quartus 16.0:
 set_global_assignment -name NUM_PARALLEL_PROCESSORS 6
@@ -311,8 +311,8 @@ set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_1
 if { [info exists ::env(UNB_COMPILE_STAMPS) ] } {
   set_parameter -name g_stamp_date [clock format [clock seconds] -format {%Y%m%d}]
   set_parameter -name g_stamp_time [clock format [clock seconds] -format {%H%M%S}]
-  post_message -type info "RADIOHDL: using SVN $::env(RADIOHDL_SVN_REVISION)"
-  set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_SVN_REVISION)] ""] 
+  post_message -type info "RADIOHDL: using SVN $::env(RADIOHDL_GIT_REVISION)"
+  set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_GIT_REVISION)] ""] 
 }
 
 #set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "ctrl_unb2_board:u_ctrl|eth:\\gen_eth:u_eth|tech_tse:u_tech_tse|tech_tse_arria10_e3sge3:\\gen_ip_arria10_e3sge3:u0|ip_arria10_e3sge3_tse_sgmii_lvds:\\u_LVDS_tse:u_tse|ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_151_6kz2wlq:eth_tse_0|altera_eth_tse_pcs_pma_nf_lvds:i_tse_pcs_0|tbi_tx_d"
diff --git a/boards/uniboard2b/designs/unb2b_heater/doc/README.txt b/boards/uniboard2b/designs/unb2b_heater/doc/README.txt
index f61d49015e7b120307b21322c3f95a9aae1c3eff..4958c61efd971a89c4784bcd8119226a5cfefe28 100644
--- a/boards/uniboard2b/designs/unb2b_heater/doc/README.txt
+++ b/boards/uniboard2b/designs/unb2b_heater/doc/README.txt
@@ -2,17 +2,17 @@ Quick steps to compile and use design [unb2a_heater] in RadionHDL
 ------------------------------------------------------------------
 
 -> In case of a new installation, the IP's have to be generated for Arria10.
-   In the: $RADIOHDL/libraries/technology/ip_arria10_e1sg
+   In the: $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg
    directory; run the bash script: ./generate-all-ip.sh
 
 -> For compilation it might be necessary to check the .vhd file:
-   $RADIOHDL/libraries/technology/technology_select_pkg.vhd
+   $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
 
 
 
 1. Start with the Oneclick Commands:
-    python $RADIOHDL/tools/oneclick/base/modelsim_config.py -t unb2b
-    python $RADIOHDL/tools/oneclick/base/quartus_config.py -t unb2b
+    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2b
+    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2b
 
 
 2. Generate MMM for QSYS:
@@ -107,7 +107,7 @@ Then program the .JIC file (output_file.jic) to EPCS flash:
 - make sure the 4 fpga icons have the device 10AX115U4F45ES
 - right-click each fpga icon and attach flash device EPCQL1024
 - right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
-  (in $RADIOHDL/boards/uniboard2/libraries/unb2a_board/quartus)
+  (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2a_board/quartus)
 - right-click each EPCQL1024 and change file from <none> to output_file.jic
 - select click each Program/Configure radiobutton
 - click start and wait for 'Successful'
diff --git a/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg b/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg
index 3d95d14a8b9ad2401337705869eea6b5a3f0927b..73def4af4691789b3300fa03b544c9ab57ea2e7c 100644
--- a/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg
@@ -23,10 +23,10 @@ quartus_copy_files =
     quartus .
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
     quartus/unb2b_heater_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_heater/quartus/unb2b_heater_pins.tcl b/boards/uniboard2b/designs/unb2b_heater/quartus/unb2b_heater_pins.tcl
index c2fd8f90e47aff680e97f45214b400951e11fab2..ba69570cfaec3b4b596c43801472bd8c14a884d0 100644
--- a/boards/uniboard2b/designs/unb2b_heater/quartus/unb2b_heater_pins.tcl
+++ b/boards/uniboard2b/designs/unb2b_heater/quartus/unb2b_heater_pins.tcl
@@ -18,4 +18,4 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 ###############################################################################
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_minimal/doc/README b/boards/uniboard2b/designs/unb2b_minimal/doc/README
index 7b4783fb2a1d15d5838feb4c9cf5040ed1b32ada..1c12d1247f00e6840156da2dc3302355e46a0ba1 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/doc/README
+++ b/boards/uniboard2b/designs/unb2b_minimal/doc/README
@@ -5,19 +5,19 @@ On uni-boards 26287-001..26287-005 (unb2b) the used FPGA is '10AX115U2F45E1SG'
 
 
 -> In case of a new installation, the IP's have to be generated for Arria10.
-   In the: $RADIOHDL/libraries/technology/ip_arria10
+   In the: $RADIOHDL_WORK/libraries/technology/ip_arria10
    directory; run the bash script: ./generate-all-ip.sh
 
 -> For compilation it might be necessary to check the .vhd file:
-   $RADIOHDL/libraries/technology/technology_select_pkg.vhd
+   $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
 
 -> Make sure you have set up the RadioHDL/trunk/tools/quartus/set_quartus script correctly to use quartus 17 for unb2b.
 
 -> Make sure you use the modified avs2_eth_coe_hw.tcl (see attachment of this e-mail), this file is placed in RadioHDL/trunk/libraries/io/eth/src/vhdl.
 
 1. Start with the Oneclick Commands:
-    python $RADIOHDL/tools/oneclick/base/modelsim_config.py -t unb2b
-    python $RADIOHDL/tools/oneclick/base/quartus_config.py -t unb2b
+    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2b
+    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2b
 
 # 2. Generate MMM for QSYS:
 #     run_qsys unb2b unb2b_minimal
@@ -59,7 +59,7 @@ Synthesis
 - Open the unb2b_minumal quartus project from the build directory.
 - Open the qsys_unb2b_minimal.qsys file from the build directory.
 - Generate the HDL files for the qsys using the GUI.
-- "cd $RADIOHDL/build/unb2b/quartus/unb2b_minimal"
+- "cd $RADIOHDL_WORK/build/unb2b/quartus/unb2b_minimal"
 - "cp qsys_unb2b_minimal/qsys_unb2b_minimal* ."
 - "run_app unb2b unb2b_minimal use=gen2"
 - In Quartus, click the play button to compile the design.
diff --git a/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg b/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
index 68528b77d7ab47fc3cba5d3295f9b86360b17c6a..213b7154455f891fd12eeedd3d7bed6f3f94dd4a 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
     quartus .
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
     quartus/unb2b_minimal_pins.tcl
@@ -37,3 +37,6 @@ quartus_vhdl_files =
 quartus_qip_files =
     $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/qsys_unb2b_minimal/qsys_unb2b_minimal.qip
 
+nios2_app_userflags =
+    "use=gen2"
+
diff --git a/boards/uniboard2b/designs/unb2b_minimal/quartus/unb2b_minimal_pins.tcl b/boards/uniboard2b/designs/unb2b_minimal/quartus/unb2b_minimal_pins.tcl
index f0e1fcbcc2838bca140bbe67dfdcb1c17ac639ec..3374b678b991559244f05d0b42f393cde9f1c345 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/quartus/unb2b_minimal_pins.tcl
+++ b/boards/uniboard2b/designs/unb2b_minimal/quartus/unb2b_minimal_pins.tcl
@@ -19,4 +19,4 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_test/doc/README.txt b/boards/uniboard2b/designs/unb2b_test/doc/README.txt
index 8c667b071b3f83adfe10ee5fa014091db625aa53..7dbf81984351624dd2eafbc0701c3b960c403318 100644
--- a/boards/uniboard2b/designs/unb2b_test/doc/README.txt
+++ b/boards/uniboard2b/designs/unb2b_test/doc/README.txt
@@ -25,17 +25,17 @@ The following revisions are available for unb2b_test (see the directories in ../
 
 
 -> In case of a new installation, the IP's have to be generated for Arria10. 
-   In the: $RADIOHDL/libraries/technology/ip_arria10_e1sg
+   In the: $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg
    directory; run the bash script: ./generate-all-ip.sh
    -> The TSE IP gives a lot of critical warnings. To fix them, run this patch:
-      cd $RADIOHDL/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds
+      cd $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds
       ./run_patch.sh
 
 
 
 1. Start with the Oneclick Commands:
-    python $RADIOHDL/tools/oneclick/base/modelsim_config.py -t unb2b
-    python $RADIOHDL/tools/oneclick/base/quartus_config.py -t unb2b
+    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2b
+    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2b
 
 
 2. Generate MMM for QSYS (select one of these revisions):
@@ -80,7 +80,7 @@ load the project now from the build directory.
 ----------------
 Using JTAG: Start the Quartus GUI and open: tools->programmer.
             Then click auto-detect; (click 4x ok)
-            Use 'change file' to select the correct .sof file (in $RADIOHDL/build/unb2b/quartus/unb2b_test_...) for each FPGA
+            Use 'change file' to select the correct .sof file (in $RADIOHDL_WORK/build/unb2b/quartus/unb2b_test_...) for each FPGA
             Select the FPGA(s) which has to be programmed
             Click 'start'
 Using EPCS: See step 6 below.
@@ -106,7 +106,7 @@ For generating a Factory image .RBF file:
 
     run_rbf unb2b --unb2_factory unb2b_test_[revision]
 
-The .RBF file is now in $RADIOHDL/build/unb2b/quartus/unb2b_test_[revision]
+The .RBF file is now in $RADIOHDL_WORK/build/unb2b/quartus/unb2b_test_[revision]
 Now copy the .RBF file to the LCU host with 'scp'
 
 (b)
@@ -117,7 +117,7 @@ Program User image:
 Program Factory image:
     python util_epcs.py --unb 1 --fn 0 -n 3 -s unb2b_test_[revision].rbf
 
--> For extra info on RBF files on Uniboard2, see: $RADIOHDL/libraries/io/epcs/doc/README.txt
+-> For extra info on RBF files on Uniboard2, see: $RADIOHDL_WORK/libraries/io/epcs/doc/README.txt
 
 To start the User image:
     python util_remu.py --unb 1 --fn 0 -n 6  # ignore timeout error
@@ -151,7 +151,7 @@ Then program the .JIC file (output_file.jic) to EPCS flash:
 
 (*1) When error select correct SFL (serial flash loader) from Altera service request for each FPGA:
      right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
-     (in $RADIOHDL/boards/uniboard2/libraries/unb2b_board/quartus)
+     (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2b_board/quartus)
 
 
 7.
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/unb2b_test_pins.tcl b/boards/uniboard2b/designs/unb2b_test/quartus/unb2b_test_pins.tcl
index 553162a115fe12ddb46f6243ecf76ddd3ad925ca..c0483d1585c6903e1a6ef07e604873f630100286 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/unb2b_test_pins.tcl
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/unb2b_test_pins.tcl
@@ -19,7 +19,7 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
 
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg
index 33ad1deec5b20a092a149290d5cf6cf572196da4..8d7faee81bd9a2d92aeb0d401134c5bcab5db331 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg
@@ -45,14 +45,14 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 quartus_sdc_pre_files =
     quartus/unb2b_test_10GbE.sdc
-    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board_pre.sdc
+    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board_pre.sdc
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
     quartus/unb2b_test_10GbE_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/quartus/unb2b_test_10GbE_pins.tcl b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/quartus/unb2b_test_10GbE_pins.tcl
index 9f0f3d463eb4c86283ab81554712b6876bfe7a1f..7e83e4b07c8a8ecd7eae37b78eaf47d226a87dfd 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/quartus/unb2b_test_10GbE_pins.tcl
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/quartus/unb2b_test_10GbE_pins.tcl
@@ -19,5 +19,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
index e9c7328a338459141d0f97d3198a62ce7c6e1e7d..d6154e79bb6d6b413468eb5d2524e00f2a5bc960 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
@@ -26,7 +26,7 @@ PACKAGE qsys_unb2b_test_pkg IS
 
   -----------------------------------------------------------------------------
   -- this component declaration is copy-pasted from Quartus QSYS builder generated file:
-  -- $RADIOHDL/build/unb2b/quartus/unb2b_test_ddr/qsys_unb2b_test/sim/qsys_unb2b_test.vhd
+  -- $RADIOHDL_WORK/build/unb2b/quartus/unb2b_test_ddr/qsys_unb2b_test/sim/qsys_unb2b_test.vhd
   -----------------------------------------------------------------------------
   
     component qsys_unb2b_test is
diff --git a/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf b/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
index 7a372076f5fd4042106334a06940b2917da0aa28..3b4085e313ea011759114ae008e1328756aa370d 100644
--- a/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+++ b/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
@@ -22,7 +22,7 @@
 # This QSF is sourced by other design QSF files.
 # ==============================================
 # Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
 
 # new in Quartus 16.0:
 set_global_assignment -name NUM_PARALLEL_PROCESSORS 6
@@ -311,8 +311,8 @@ set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_1
 if { [info exists ::env(UNB_COMPILE_STAMPS) ] } {
   set_parameter -name g_stamp_date [clock format [clock seconds] -format {%Y%m%d}]
   set_parameter -name g_stamp_time [clock format [clock seconds] -format {%H%M%S}]
-  post_message -type info "RADIOHDL: using SVN $::env(RADIOHDL_SVN_REVISION)"
-  set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_SVN_REVISION)] ""] 
+  post_message -type info "RADIOHDL: using GIT $::env(RADIOHDL_GIT_REVISION)"
+  set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_GIT_REVISION)] ""] 
 }
 
 #set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "ctrl_unb2_board:u_ctrl|eth:\\gen_eth:u_eth|tech_tse:u_tech_tse|tech_tse_arria10_e1sg:\\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_tse_sgmii_lvds:\\u_LVDS_tse:u_tse|ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_151_6kz2wlq:eth_tse_0|altera_eth_tse_pcs_pma_nf_lvds:i_tse_pcs_0|tbi_tx_d"
diff --git a/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg b/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg
index 4e1c6925aba277145ea4c6d426fef5903d2a73b9..94b17e0841c475fa90fe58521f057d77a27affbf 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg
+++ b/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg
@@ -26,8 +26,8 @@ quartus_copy_files =
     src/hex hex
 
 quartus_qsf_files = 
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.qsf
     
 quartus_tcl_files =
     quartus/unb1_dp_offload_pins.tcl
diff --git a/libraries/base/reorder/hdllib.cfg b/libraries/base/reorder/hdllib.cfg
index c1357b093ddcce29ae42ef3565d10dfe781d912a..445fd783dd7dc1e1d32e6acdee463392a550452a 100644
--- a/libraries/base/reorder/hdllib.cfg
+++ b/libraries/base/reorder/hdllib.cfg
@@ -41,7 +41,7 @@ regression_test_vhdl =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg b/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg
index 3e3089912f52d14e61f45f8acf5a1b7312e2c9a9..b7626df3590b7e715529b4bef1ca1883d149c1d8 100644
--- a/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg
@@ -24,7 +24,7 @@ synth_top_level_entity =
 quartus_copy_files = quartus/sopc_unb1_fn_bf.sopc .
 
 quartus_qsf_files =                                                       
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_tcl_files =
     quartus/unb1_fn_bf_constraints.tcl  
diff --git a/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg b/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg
index b59f6067a5c293c60423f22128db77e1fa2a6e9a..be1afe4a89ad54c26fca6a86b57dc909559d94e8 100644
--- a/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg
+++ b/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg
@@ -23,7 +23,7 @@ quartus_copy_files =
     quartus/qsys_unb1_correlator.qsys .
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_tcl_files =
     quartus/unb1_correlator_pins.tcl
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd b/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd
index ec4315320793480d6157293dd73b79547469d73b..896a25a6ad54492a1512ac30d3c01c25dc1cd90b 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd
@@ -266,7 +266,7 @@ BEGIN
     g_sim            => TRUE,
     g_pass_through   => FALSE,
     g_rec_not_play   => TRUE,
-    g_rec_play_file  => "$RADIOHDL/libraries/dsp/correlator/tb/rec/correlator_src_out_arr0.rec",
+    g_rec_play_file  => "$RADIOHDL_WORK/libraries/dsp/correlator/tb/rec/correlator_src_out_arr0.rec",
     g_record_invalid => FALSE
   )
   PORT MAP (
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd
index 7d07ce044c9bd3cfe7cfc0ae61c0bd93ba8d5c6d..35a6684bc3a7ef5e41fc9c130657dbb9e6932831 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd
@@ -26,7 +26,7 @@
 --   The g_data_file with input and expected output data is created by the
 --   Matlab script:
 --
---     $RADIOHDL/applications/apertif/matlab/run_pfft.m
+--     $RADIOHDL_WORK/applications/apertif/matlab/run_pfft.m
 --
 --   yields:
 --
diff --git a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd
index 7f36136eea9c97e56dc9d0c105b9d241486d2dda..6c155ee41d06019287272c604f1800f9e34fe903 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd
@@ -22,7 +22,7 @@
 -- Purpose: Multi-testbench for fft_r2_par using file data
 -- Description:
 --   Verify fft_r2_par using and data generated by Matlab
---   $RADIOHDL/applications/apertif/matlab/run_pfft.m
+--   $RADIOHDL_WORK/applications/apertif/matlab/run_pfft.m
 --   
 -- Usage:
 --   > as 4
diff --git a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd
index 485c3d11fe76785ebb098793b0ee2dc3e84d6fb9..3efd0d0917221ec7c194f8916c34f543a0f8a585 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd
@@ -22,7 +22,7 @@
 -- Purpose: Multi-testbench for fft_r2_pipe using file data
 -- Description:
 --   Verify fft_r2_pipe using and data generated by Matlab
---   $RADIOHDL/applications/apertif/matlab/run_pfft.m
+--   $RADIOHDL_WORK/applications/apertif/matlab/run_pfft.m
 --   
 -- Usage:
 --   > as 4
diff --git a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd
index ab34ea103dd7dff01b28edccb6f7c51654761318..9c2132abc6726e4f55a46d391649827f1d5fd1fb 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd
@@ -23,8 +23,8 @@
 -- Description:
 --   Verify fft_r2_wide using and data generated by Matlab scripts:
 --
---   - $RADIOHDL/applications/apertif/matlab/run_pfft.m
---   - $RADIOHDL/applications/apertif/matlab/run_pfft_complex.m
+--   - $RADIOHDL_WORK/applications/apertif/matlab/run_pfft.m
+--   - $RADIOHDL_WORK/applications/apertif/matlab/run_pfft_complex.m
 --
 -- Usage:
 --   > as 4
diff --git a/libraries/dsp/filter/src/python/diff_lofar_coefs b/libraries/dsp/filter/src/python/diff_lofar_coefs
index 1a0a6070fed5a01d523c208c9a848ca929b14d3c..529bf5381fb43b31da9a5dcc4768102bff4793a3 100755
--- a/libraries/dsp/filter/src/python/diff_lofar_coefs
+++ b/libraries/dsp/filter/src/python/diff_lofar_coefs
@@ -31,81 +31,81 @@
 #   the subband statistics will not peak low to 0 dB.
 
 echo "1) Check that copies of LOFAR FIR coefficient reference files are equal"
-diff $RADIOHDL/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $UPE_GEAR/apps/commissioning_apertif_beamformer/coeffs16384Kaiser-quant.dat
-diff $RADIOHDL/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $UNB/Firmware/modules/Lofar/pfs/src/data/Coeffs16384Kaiser-quant.dat
-diff $RADIOHDL/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $RADIOHDL/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-withdc.dat
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $UPE_GEAR/apps/commissioning_apertif_beamformer/coeffs16384Kaiser-quant.dat
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $UNB/Firmware/modules/Lofar/pfs/src/data/Coeffs16384Kaiser-quant.dat
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-withdc.dat
 
-diff $RADIOHDL/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-nodc.dat $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_no_dc_lofar_subband_16taps_1024points_16b.dat 
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-nodc.dat $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_no_dc_lofar_subband_16taps_1024points_16b.dat 
 
 echo "2) Check that the local stored LOFAR FIR coefficients mif files are the same as in apertif_unb1_bn_filterbank"
-cd $RADIOHDL/libraries/dsp/filter/src/hex
-diff coefs_wide4_p1024_t16_0.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_0.mif
-diff coefs_wide4_p1024_t16_1.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_1.mif
-diff coefs_wide4_p1024_t16_2.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_2.mif
-diff coefs_wide4_p1024_t16_3.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_3.mif
-diff coefs_wide4_p1024_t16_4.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_4.mif
-diff coefs_wide4_p1024_t16_5.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_5.mif
-diff coefs_wide4_p1024_t16_6.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_6.mif
-diff coefs_wide4_p1024_t16_7.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_7.mif
-diff coefs_wide4_p1024_t16_8.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_8.mif
-diff coefs_wide4_p1024_t16_9.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_9.mif
-diff coefs_wide4_p1024_t16_10.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_10.mif
-diff coefs_wide4_p1024_t16_11.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_11.mif
-diff coefs_wide4_p1024_t16_12.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_12.mif
-diff coefs_wide4_p1024_t16_13.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_13.mif
-diff coefs_wide4_p1024_t16_14.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_14.mif
-diff coefs_wide4_p1024_t16_15.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_15.mif
-diff coefs_wide4_p1024_t16_16.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_16.mif
-diff coefs_wide4_p1024_t16_17.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_17.mif
-diff coefs_wide4_p1024_t16_18.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_18.mif
-diff coefs_wide4_p1024_t16_19.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_19.mif
-diff coefs_wide4_p1024_t16_20.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_20.mif
-diff coefs_wide4_p1024_t16_21.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_21.mif
-diff coefs_wide4_p1024_t16_22.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_22.mif
-diff coefs_wide4_p1024_t16_23.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_23.mif
-diff coefs_wide4_p1024_t16_24.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_24.mif
-diff coefs_wide4_p1024_t16_25.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_25.mif
-diff coefs_wide4_p1024_t16_26.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_26.mif
-diff coefs_wide4_p1024_t16_27.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_27.mif
-diff coefs_wide4_p1024_t16_28.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_28.mif
-diff coefs_wide4_p1024_t16_29.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_29.mif
-diff coefs_wide4_p1024_t16_30.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_30.mif
-diff coefs_wide4_p1024_t16_31.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_31.mif
-diff coefs_wide4_p1024_t16_32.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_32.mif
-diff coefs_wide4_p1024_t16_33.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_33.mif
-diff coefs_wide4_p1024_t16_34.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_34.mif
-diff coefs_wide4_p1024_t16_35.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_35.mif
-diff coefs_wide4_p1024_t16_36.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_36.mif
-diff coefs_wide4_p1024_t16_37.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_37.mif
-diff coefs_wide4_p1024_t16_38.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_38.mif
-diff coefs_wide4_p1024_t16_39.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_39.mif
-diff coefs_wide4_p1024_t16_40.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_40.mif
-diff coefs_wide4_p1024_t16_41.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_41.mif
-diff coefs_wide4_p1024_t16_42.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_42.mif
-diff coefs_wide4_p1024_t16_43.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_43.mif
-diff coefs_wide4_p1024_t16_44.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_44.mif
-diff coefs_wide4_p1024_t16_45.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_45.mif
-diff coefs_wide4_p1024_t16_46.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_46.mif
-diff coefs_wide4_p1024_t16_47.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_47.mif
-diff coefs_wide4_p1024_t16_48.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_48.mif
-diff coefs_wide4_p1024_t16_49.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_49.mif
-diff coefs_wide4_p1024_t16_50.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_50.mif
-diff coefs_wide4_p1024_t16_51.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_51.mif
-diff coefs_wide4_p1024_t16_52.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_52.mif
-diff coefs_wide4_p1024_t16_53.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_53.mif
-diff coefs_wide4_p1024_t16_54.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_54.mif
-diff coefs_wide4_p1024_t16_55.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_55.mif
-diff coefs_wide4_p1024_t16_56.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_56.mif
-diff coefs_wide4_p1024_t16_57.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_57.mif
-diff coefs_wide4_p1024_t16_58.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_58.mif
-diff coefs_wide4_p1024_t16_59.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_59.mif
-diff coefs_wide4_p1024_t16_60.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_60.mif
-diff coefs_wide4_p1024_t16_61.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_61.mif
-diff coefs_wide4_p1024_t16_62.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_62.mif
-diff coefs_wide4_p1024_t16_63.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_63.mif
+cd $RADIOHDL_WORK/libraries/dsp/filter/src/hex
+diff coefs_wide4_p1024_t16_0.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_0.mif
+diff coefs_wide4_p1024_t16_1.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_1.mif
+diff coefs_wide4_p1024_t16_2.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_2.mif
+diff coefs_wide4_p1024_t16_3.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_3.mif
+diff coefs_wide4_p1024_t16_4.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_4.mif
+diff coefs_wide4_p1024_t16_5.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_5.mif
+diff coefs_wide4_p1024_t16_6.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_6.mif
+diff coefs_wide4_p1024_t16_7.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_7.mif
+diff coefs_wide4_p1024_t16_8.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_8.mif
+diff coefs_wide4_p1024_t16_9.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_9.mif
+diff coefs_wide4_p1024_t16_10.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_10.mif
+diff coefs_wide4_p1024_t16_11.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_11.mif
+diff coefs_wide4_p1024_t16_12.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_12.mif
+diff coefs_wide4_p1024_t16_13.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_13.mif
+diff coefs_wide4_p1024_t16_14.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_14.mif
+diff coefs_wide4_p1024_t16_15.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_15.mif
+diff coefs_wide4_p1024_t16_16.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_16.mif
+diff coefs_wide4_p1024_t16_17.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_17.mif
+diff coefs_wide4_p1024_t16_18.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_18.mif
+diff coefs_wide4_p1024_t16_19.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_19.mif
+diff coefs_wide4_p1024_t16_20.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_20.mif
+diff coefs_wide4_p1024_t16_21.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_21.mif
+diff coefs_wide4_p1024_t16_22.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_22.mif
+diff coefs_wide4_p1024_t16_23.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_23.mif
+diff coefs_wide4_p1024_t16_24.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_24.mif
+diff coefs_wide4_p1024_t16_25.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_25.mif
+diff coefs_wide4_p1024_t16_26.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_26.mif
+diff coefs_wide4_p1024_t16_27.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_27.mif
+diff coefs_wide4_p1024_t16_28.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_28.mif
+diff coefs_wide4_p1024_t16_29.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_29.mif
+diff coefs_wide4_p1024_t16_30.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_30.mif
+diff coefs_wide4_p1024_t16_31.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_31.mif
+diff coefs_wide4_p1024_t16_32.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_32.mif
+diff coefs_wide4_p1024_t16_33.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_33.mif
+diff coefs_wide4_p1024_t16_34.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_34.mif
+diff coefs_wide4_p1024_t16_35.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_35.mif
+diff coefs_wide4_p1024_t16_36.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_36.mif
+diff coefs_wide4_p1024_t16_37.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_37.mif
+diff coefs_wide4_p1024_t16_38.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_38.mif
+diff coefs_wide4_p1024_t16_39.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_39.mif
+diff coefs_wide4_p1024_t16_40.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_40.mif
+diff coefs_wide4_p1024_t16_41.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_41.mif
+diff coefs_wide4_p1024_t16_42.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_42.mif
+diff coefs_wide4_p1024_t16_43.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_43.mif
+diff coefs_wide4_p1024_t16_44.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_44.mif
+diff coefs_wide4_p1024_t16_45.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_45.mif
+diff coefs_wide4_p1024_t16_46.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_46.mif
+diff coefs_wide4_p1024_t16_47.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_47.mif
+diff coefs_wide4_p1024_t16_48.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_48.mif
+diff coefs_wide4_p1024_t16_49.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_49.mif
+diff coefs_wide4_p1024_t16_50.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_50.mif
+diff coefs_wide4_p1024_t16_51.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_51.mif
+diff coefs_wide4_p1024_t16_52.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_52.mif
+diff coefs_wide4_p1024_t16_53.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_53.mif
+diff coefs_wide4_p1024_t16_54.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_54.mif
+diff coefs_wide4_p1024_t16_55.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_55.mif
+diff coefs_wide4_p1024_t16_56.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_56.mif
+diff coefs_wide4_p1024_t16_57.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_57.mif
+diff coefs_wide4_p1024_t16_58.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_58.mif
+diff coefs_wide4_p1024_t16_59.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_59.mif
+diff coefs_wide4_p1024_t16_60.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_60.mif
+diff coefs_wide4_p1024_t16_61.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_61.mif
+diff coefs_wide4_p1024_t16_62.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_62.mif
+diff coefs_wide4_p1024_t16_63.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_63.mif
 
 echo "3) Verify that the created reference LOFAR FIR coefficients mif files are equal to the local stored mif files"
-cd $RADIOHDL/libraries/dsp/filter/src/hex
+cd $RADIOHDL_WORK/libraries/dsp/filter/src/hex
 diff Coeffs16384Kaiser-quant_4wb_0.mif  coefs_wide4_p1024_t16_0.mif
 diff Coeffs16384Kaiser-quant_4wb_1.mif  coefs_wide4_p1024_t16_1.mif
 diff Coeffs16384Kaiser-quant_4wb_2.mif  coefs_wide4_p1024_t16_2.mif
@@ -172,142 +172,142 @@ diff Coeffs16384Kaiser-quant_4wb_62.mif coefs_wide4_p1024_t16_62.mif
 diff Coeffs16384Kaiser-quant_4wb_63.mif coefs_wide4_p1024_t16_63.mif
 
 echo "4) Verify that the created reference LOFAR FIR coefficients mif files are equal to the mif files stored at apertif_unb1_bn_filterbank"
-cd $RADIOHDL/libraries/dsp/filter/src/hex
-diff Coeffs16384Kaiser-quant_4wb_0.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_0.mif
-diff Coeffs16384Kaiser-quant_4wb_1.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_1.mif
-diff Coeffs16384Kaiser-quant_4wb_2.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_2.mif
-diff Coeffs16384Kaiser-quant_4wb_3.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_3.mif
-diff Coeffs16384Kaiser-quant_4wb_4.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_4.mif
-diff Coeffs16384Kaiser-quant_4wb_5.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_5.mif
-diff Coeffs16384Kaiser-quant_4wb_6.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_6.mif
-diff Coeffs16384Kaiser-quant_4wb_7.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_7.mif
-diff Coeffs16384Kaiser-quant_4wb_8.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_8.mif
-diff Coeffs16384Kaiser-quant_4wb_9.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_9.mif
-diff Coeffs16384Kaiser-quant_4wb_10.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_10.mif
-diff Coeffs16384Kaiser-quant_4wb_11.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_11.mif
-diff Coeffs16384Kaiser-quant_4wb_12.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_12.mif
-diff Coeffs16384Kaiser-quant_4wb_13.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_13.mif
-diff Coeffs16384Kaiser-quant_4wb_14.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_14.mif
-diff Coeffs16384Kaiser-quant_4wb_15.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_15.mif
-diff Coeffs16384Kaiser-quant_4wb_16.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_16.mif
-diff Coeffs16384Kaiser-quant_4wb_17.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_17.mif
-diff Coeffs16384Kaiser-quant_4wb_18.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_18.mif
-diff Coeffs16384Kaiser-quant_4wb_19.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_19.mif
-diff Coeffs16384Kaiser-quant_4wb_20.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_20.mif
-diff Coeffs16384Kaiser-quant_4wb_21.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_21.mif
-diff Coeffs16384Kaiser-quant_4wb_22.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_22.mif
-diff Coeffs16384Kaiser-quant_4wb_23.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_23.mif
-diff Coeffs16384Kaiser-quant_4wb_24.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_24.mif
-diff Coeffs16384Kaiser-quant_4wb_25.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_25.mif
-diff Coeffs16384Kaiser-quant_4wb_26.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_26.mif
-diff Coeffs16384Kaiser-quant_4wb_27.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_27.mif
-diff Coeffs16384Kaiser-quant_4wb_28.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_28.mif
-diff Coeffs16384Kaiser-quant_4wb_29.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_29.mif
-diff Coeffs16384Kaiser-quant_4wb_30.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_30.mif
-diff Coeffs16384Kaiser-quant_4wb_31.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_31.mif
-diff Coeffs16384Kaiser-quant_4wb_32.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_32.mif
-diff Coeffs16384Kaiser-quant_4wb_33.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_33.mif
-diff Coeffs16384Kaiser-quant_4wb_34.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_34.mif
-diff Coeffs16384Kaiser-quant_4wb_35.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_35.mif
-diff Coeffs16384Kaiser-quant_4wb_36.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_36.mif
-diff Coeffs16384Kaiser-quant_4wb_37.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_37.mif
-diff Coeffs16384Kaiser-quant_4wb_38.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_38.mif
-diff Coeffs16384Kaiser-quant_4wb_39.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_39.mif
-diff Coeffs16384Kaiser-quant_4wb_40.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_40.mif
-diff Coeffs16384Kaiser-quant_4wb_41.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_41.mif
-diff Coeffs16384Kaiser-quant_4wb_42.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_42.mif
-diff Coeffs16384Kaiser-quant_4wb_43.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_43.mif
-diff Coeffs16384Kaiser-quant_4wb_44.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_44.mif
-diff Coeffs16384Kaiser-quant_4wb_45.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_45.mif
-diff Coeffs16384Kaiser-quant_4wb_46.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_46.mif
-diff Coeffs16384Kaiser-quant_4wb_47.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_47.mif
-diff Coeffs16384Kaiser-quant_4wb_48.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_48.mif
-diff Coeffs16384Kaiser-quant_4wb_49.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_49.mif
-diff Coeffs16384Kaiser-quant_4wb_50.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_50.mif
-diff Coeffs16384Kaiser-quant_4wb_51.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_51.mif
-diff Coeffs16384Kaiser-quant_4wb_52.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_52.mif
-diff Coeffs16384Kaiser-quant_4wb_53.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_53.mif
-diff Coeffs16384Kaiser-quant_4wb_54.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_54.mif
-diff Coeffs16384Kaiser-quant_4wb_55.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_55.mif
-diff Coeffs16384Kaiser-quant_4wb_56.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_56.mif
-diff Coeffs16384Kaiser-quant_4wb_57.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_57.mif
-diff Coeffs16384Kaiser-quant_4wb_58.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_58.mif
-diff Coeffs16384Kaiser-quant_4wb_59.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_59.mif
-diff Coeffs16384Kaiser-quant_4wb_60.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_60.mif
-diff Coeffs16384Kaiser-quant_4wb_61.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_61.mif
-diff Coeffs16384Kaiser-quant_4wb_62.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_62.mif
-diff Coeffs16384Kaiser-quant_4wb_63.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_63.mif
+cd $RADIOHDL_WORK/libraries/dsp/filter/src/hex
+diff Coeffs16384Kaiser-quant_4wb_0.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_0.mif
+diff Coeffs16384Kaiser-quant_4wb_1.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_1.mif
+diff Coeffs16384Kaiser-quant_4wb_2.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_2.mif
+diff Coeffs16384Kaiser-quant_4wb_3.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_3.mif
+diff Coeffs16384Kaiser-quant_4wb_4.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_4.mif
+diff Coeffs16384Kaiser-quant_4wb_5.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_5.mif
+diff Coeffs16384Kaiser-quant_4wb_6.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_6.mif
+diff Coeffs16384Kaiser-quant_4wb_7.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_7.mif
+diff Coeffs16384Kaiser-quant_4wb_8.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_8.mif
+diff Coeffs16384Kaiser-quant_4wb_9.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_9.mif
+diff Coeffs16384Kaiser-quant_4wb_10.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_10.mif
+diff Coeffs16384Kaiser-quant_4wb_11.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_11.mif
+diff Coeffs16384Kaiser-quant_4wb_12.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_12.mif
+diff Coeffs16384Kaiser-quant_4wb_13.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_13.mif
+diff Coeffs16384Kaiser-quant_4wb_14.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_14.mif
+diff Coeffs16384Kaiser-quant_4wb_15.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_15.mif
+diff Coeffs16384Kaiser-quant_4wb_16.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_16.mif
+diff Coeffs16384Kaiser-quant_4wb_17.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_17.mif
+diff Coeffs16384Kaiser-quant_4wb_18.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_18.mif
+diff Coeffs16384Kaiser-quant_4wb_19.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_19.mif
+diff Coeffs16384Kaiser-quant_4wb_20.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_20.mif
+diff Coeffs16384Kaiser-quant_4wb_21.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_21.mif
+diff Coeffs16384Kaiser-quant_4wb_22.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_22.mif
+diff Coeffs16384Kaiser-quant_4wb_23.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_23.mif
+diff Coeffs16384Kaiser-quant_4wb_24.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_24.mif
+diff Coeffs16384Kaiser-quant_4wb_25.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_25.mif
+diff Coeffs16384Kaiser-quant_4wb_26.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_26.mif
+diff Coeffs16384Kaiser-quant_4wb_27.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_27.mif
+diff Coeffs16384Kaiser-quant_4wb_28.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_28.mif
+diff Coeffs16384Kaiser-quant_4wb_29.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_29.mif
+diff Coeffs16384Kaiser-quant_4wb_30.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_30.mif
+diff Coeffs16384Kaiser-quant_4wb_31.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_31.mif
+diff Coeffs16384Kaiser-quant_4wb_32.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_32.mif
+diff Coeffs16384Kaiser-quant_4wb_33.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_33.mif
+diff Coeffs16384Kaiser-quant_4wb_34.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_34.mif
+diff Coeffs16384Kaiser-quant_4wb_35.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_35.mif
+diff Coeffs16384Kaiser-quant_4wb_36.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_36.mif
+diff Coeffs16384Kaiser-quant_4wb_37.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_37.mif
+diff Coeffs16384Kaiser-quant_4wb_38.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_38.mif
+diff Coeffs16384Kaiser-quant_4wb_39.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_39.mif
+diff Coeffs16384Kaiser-quant_4wb_40.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_40.mif
+diff Coeffs16384Kaiser-quant_4wb_41.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_41.mif
+diff Coeffs16384Kaiser-quant_4wb_42.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_42.mif
+diff Coeffs16384Kaiser-quant_4wb_43.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_43.mif
+diff Coeffs16384Kaiser-quant_4wb_44.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_44.mif
+diff Coeffs16384Kaiser-quant_4wb_45.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_45.mif
+diff Coeffs16384Kaiser-quant_4wb_46.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_46.mif
+diff Coeffs16384Kaiser-quant_4wb_47.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_47.mif
+diff Coeffs16384Kaiser-quant_4wb_48.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_48.mif
+diff Coeffs16384Kaiser-quant_4wb_49.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_49.mif
+diff Coeffs16384Kaiser-quant_4wb_50.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_50.mif
+diff Coeffs16384Kaiser-quant_4wb_51.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_51.mif
+diff Coeffs16384Kaiser-quant_4wb_52.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_52.mif
+diff Coeffs16384Kaiser-quant_4wb_53.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_53.mif
+diff Coeffs16384Kaiser-quant_4wb_54.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_54.mif
+diff Coeffs16384Kaiser-quant_4wb_55.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_55.mif
+diff Coeffs16384Kaiser-quant_4wb_56.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_56.mif
+diff Coeffs16384Kaiser-quant_4wb_57.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_57.mif
+diff Coeffs16384Kaiser-quant_4wb_58.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_58.mif
+diff Coeffs16384Kaiser-quant_4wb_59.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_59.mif
+diff Coeffs16384Kaiser-quant_4wb_60.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_60.mif
+diff Coeffs16384Kaiser-quant_4wb_61.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_61.mif
+diff Coeffs16384Kaiser-quant_4wb_62.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_62.mif
+diff Coeffs16384Kaiser-quant_4wb_63.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_63.mif
 
 
 echo "5) Verify that the created reference LOFAR No DC FIR coefficients mif files are equal to the mif files stored at apertif_unb1_bn_filterbank"
 # To create the *.mif use recreate_pfir_mifs or directly use:
-# python $RADIOHDL/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py -f $RADIOHDL/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-nodc.dat -t 16 -p 1024 -w 4 -c 16
-cd $RADIOHDL/libraries/dsp/filter/src/hex
-diff Coeffs16384Kaiser-quant-nodc_4wb_0.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_0.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_1.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_1.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_2.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_2.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_3.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_3.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_4.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_4.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_5.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_5.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_6.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_6.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_7.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_7.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_8.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_8.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_9.mif  $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_9.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_10.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_10.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_11.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_11.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_12.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_12.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_13.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_13.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_14.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_14.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_15.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_15.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_16.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_16.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_17.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_17.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_18.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_18.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_19.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_19.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_20.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_20.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_21.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_21.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_22.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_22.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_23.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_23.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_24.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_24.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_25.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_25.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_26.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_26.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_27.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_27.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_28.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_28.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_29.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_29.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_30.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_30.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_31.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_31.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_32.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_32.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_33.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_33.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_34.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_34.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_35.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_35.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_36.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_36.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_37.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_37.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_38.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_38.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_39.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_39.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_40.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_40.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_41.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_41.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_42.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_42.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_43.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_43.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_44.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_44.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_45.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_45.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_46.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_46.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_47.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_47.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_48.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_48.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_49.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_49.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_50.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_50.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_51.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_51.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_52.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_52.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_53.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_53.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_54.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_54.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_55.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_55.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_56.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_56.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_57.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_57.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_58.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_58.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_59.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_59.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_60.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_60.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_61.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_61.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_62.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_62.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_63.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_63.mif
+# python $RADIOHDL_WORK/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py -f $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-nodc.dat -t 16 -p 1024 -w 4 -c 16
+cd $RADIOHDL_WORK/libraries/dsp/filter/src/hex
+diff Coeffs16384Kaiser-quant-nodc_4wb_0.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_0.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_1.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_1.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_2.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_2.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_3.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_3.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_4.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_4.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_5.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_5.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_6.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_6.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_7.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_7.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_8.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_8.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_9.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_9.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_10.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_10.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_11.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_11.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_12.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_12.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_13.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_13.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_14.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_14.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_15.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_15.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_16.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_16.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_17.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_17.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_18.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_18.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_19.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_19.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_20.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_20.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_21.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_21.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_22.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_22.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_23.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_23.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_24.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_24.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_25.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_25.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_26.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_26.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_27.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_27.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_28.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_28.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_29.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_29.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_30.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_30.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_31.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_31.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_32.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_32.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_33.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_33.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_34.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_34.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_35.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_35.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_36.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_36.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_37.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_37.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_38.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_38.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_39.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_39.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_40.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_40.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_41.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_41.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_42.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_42.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_43.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_43.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_44.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_44.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_45.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_45.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_46.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_46.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_47.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_47.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_48.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_48.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_49.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_49.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_50.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_50.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_51.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_51.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_52.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_52.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_53.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_53.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_54.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_54.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_55.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_55.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_56.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_56.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_57.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_57.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_58.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_58.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_59.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_59.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_60.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_60.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_61.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_61.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_62.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_62.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_63.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_63.mif
 
 
 echo "6) Set script exit directory"
-cd $RADIOHDL/libraries/dsp/filter/src/python
+cd $RADIOHDL_WORK/libraries/dsp/filter/src/python
diff --git a/libraries/dsp/filter/src/python/diff_pfir_coefs b/libraries/dsp/filter/src/python/diff_pfir_coefs
index de8b6834af6df06847a3d60c3a28ff28d20cd894..84b0765968753f3634d7cd4b6869324a5d76a793 100755
--- a/libraries/dsp/filter/src/python/diff_pfir_coefs
+++ b/libraries/dsp/filter/src/python/diff_pfir_coefs
@@ -9,16 +9,16 @@
 #
 #   Expected result is that this diff_pfir_coefs script does not report diff's
 
-diff $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_bypass_8taps_64points_16b.dat                ../hex/run_pfir_coeff_m_bypass_8taps_64points_16b.dat          
-diff $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_bypass_8taps_64points_9b.dat                 ../hex/run_pfir_coeff_m_bypass_8taps_64points_9b.dat           
-diff $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_fircls1_16taps_1024points_16b.dat            ../hex/run_pfir_coeff_m_fircls1_16taps_1024points_16b.dat      
-diff $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_fircls1_8taps_32points_9b.dat                ../hex/run_pfir_coeff_m_fircls1_8taps_32points_9b.dat          
-diff $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_fircls1_8taps_64points_9b.dat                ../hex/run_pfir_coeff_m_fircls1_8taps_64points_9b.dat          
-diff $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_fircls1_8taps_32points_9b.dat        ../hex/run_pfir_coeff_m_flat_hp_fircls1_8taps_32points_9b.dat  
-diff $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_fircls1_8taps_64points_9b.dat        ../hex/run_pfir_coeff_m_flat_hp_fircls1_8taps_64points_9b.dat  
-diff $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_32points_9b.dat  ../hex/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_32points_9b.dat
-diff $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_64points_9b.dat  ../hex/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_64points_9b.dat
-diff $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_incrementing_8taps_64points_16b.dat          ../hex/run_pfir_coeff_m_incrementing_8taps_64points_16b.dat    
-diff $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_incrementing_8taps_64points_9b.dat           ../hex/run_pfir_coeff_m_incrementing_8taps_64points_9b.dat     
-diff $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_lofar_subband_16taps_1024points_16b.dat      ../hex/run_pfir_coeff_m_lofar_subband_16taps_1024points_16b.dat
-diff $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_16b.dat      ../hex/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_16b.dat
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_bypass_8taps_64points_16b.dat                ../hex/run_pfir_coeff_m_bypass_8taps_64points_16b.dat          
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_bypass_8taps_64points_9b.dat                 ../hex/run_pfir_coeff_m_bypass_8taps_64points_9b.dat           
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_fircls1_16taps_1024points_16b.dat            ../hex/run_pfir_coeff_m_fircls1_16taps_1024points_16b.dat      
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_fircls1_8taps_32points_9b.dat                ../hex/run_pfir_coeff_m_fircls1_8taps_32points_9b.dat          
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_fircls1_8taps_64points_9b.dat                ../hex/run_pfir_coeff_m_fircls1_8taps_64points_9b.dat          
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_fircls1_8taps_32points_9b.dat        ../hex/run_pfir_coeff_m_flat_hp_fircls1_8taps_32points_9b.dat  
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_fircls1_8taps_64points_9b.dat        ../hex/run_pfir_coeff_m_flat_hp_fircls1_8taps_64points_9b.dat  
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_32points_9b.dat  ../hex/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_32points_9b.dat
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_64points_9b.dat  ../hex/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_64points_9b.dat
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_incrementing_8taps_64points_16b.dat          ../hex/run_pfir_coeff_m_incrementing_8taps_64points_16b.dat    
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_incrementing_8taps_64points_9b.dat           ../hex/run_pfir_coeff_m_incrementing_8taps_64points_9b.dat     
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_lofar_subband_16taps_1024points_16b.dat      ../hex/run_pfir_coeff_m_lofar_subband_16taps_1024points_16b.dat
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_16b.dat      ../hex/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_16b.dat
diff --git a/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py b/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py
index 70023b84c7fb7588f8e200555b217694233b6436..2b18c920e5b1e75750c46d6c2db88efc2c1af1d5 100644
--- a/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py
+++ b/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py
@@ -43,10 +43,10 @@
    line argument and is only used to identify the input dat file.
    
    A pfir_coeff_*.dat file can be created using Matlab:
-   > $RADIOHDL/applications/apertif/matlab/run_pfir_coef.m
+   > $RADIOHDL_WORK/applications/apertif/matlab/run_pfir_coef.m
    
    The result is then (dependend on the actual settings in run_pfir_coef.m):
-   > $RADIOHDL/applications/apertif/matlab/data/pfir_coeff_incrementing_8taps_64points_16b.dat
+   > $RADIOHDL_WORK/applications/apertif/matlab/data/pfir_coeff_incrementing_8taps_64points_16b.dat
    
    This coefficients dat file needs to be copied to the local ../hex directory,
    because both the dat and the MIF files sare used in the VHDL testbenches.
diff --git a/libraries/dsp/filter/src/python/recreate_4wb_mifs b/libraries/dsp/filter/src/python/recreate_4wb_mifs
index 67dcca54d00d39767095bf904aa5ddd482e116c0..f285a59c2bb0720165df5d1c104e5f8ae3922243 100755
--- a/libraries/dsp/filter/src/python/recreate_4wb_mifs
+++ b/libraries/dsp/filter/src/python/recreate_4wb_mifs
@@ -2,7 +2,7 @@
 #find . -name "*4wb_0.mif" - print
 
 # It appears they only are created in the filter library:
-#cd $RADIOHDL/libraries/dsp/filter/src/hex/
+#cd $RADIOHDL_WORK/libraries/dsp/filter/src/hex/
 #ll *4wb_0.mif
 # yields:
 #    run_pfb_m_pfir_coeff_fircls1_16taps_32points_16b_4wb_0.mif
@@ -23,7 +23,7 @@
 # any Python scripts that Hajee made to access the FIR coefficients in apertif_unb1_bn_filterbank
 # will still also work for wpfb_unit_dev.
 
-cd $RADIOHDL/libraries/dsp/filter/src/python
+cd $RADIOHDL_WORK/libraries/dsp/filter/src/python
 
 python fil_ppf_create_mifs.py -f ../hex/run_pfb_m_pfir_coeff_fircls1_16taps_32points_16b.dat           -t 16 -p   32 -w 4 -c 16
 python fil_ppf_create_mifs.py -f ../hex/run_pfir_m_pfir_coeff_fircls1_15taps_128points_16b.dat         -t 15 -p  128 -w 4 -c 16
diff --git a/libraries/dsp/filter/src/python/recreate_pfir_mifs b/libraries/dsp/filter/src/python/recreate_pfir_mifs
index ee493f3b174d1e403ab37068dc76c5dd84b52294..05bcc11aa0bb3e6690b3cfa32c32ce2993e36585 100755
--- a/libraries/dsp/filter/src/python/recreate_pfir_mifs
+++ b/libraries/dsp/filter/src/python/recreate_pfir_mifs
@@ -17,7 +17,7 @@
 #   > svn status -q ../hex
 #
 
-cd $RADIOHDL/libraries/dsp/filter/src/python
+cd $RADIOHDL_WORK/libraries/dsp/filter/src/python
 
 # run_pfir.m
 python fil_ppf_create_mifs.py -f ../hex/run_pfir_m_pfir_coeff_fircls1_15taps_128points_16b.dat          -t 15 -p  128 -w 4 -c 16
@@ -37,9 +37,9 @@ python fil_ppf_create_mifs.py -f ../hex/run_pfb_complex_m_pfir_coeff_fircls1_16t
 python fil_ppf_create_mifs.py -f ../hex/run_pfir_coeff_m_fircls1_16taps_1024points_16b.dat              -t 16 -p 1024 -w 4 -c 16
 python fil_ppf_create_mifs.py -f ../hex/run_pfir_coeff_m_lofar_subband_16taps_1024points_16b.dat        -t 16 -p 1024 -w 4 -c 16
 python fil_ppf_create_mifs.py -f ../hex/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_16b.dat        -t 16 -p 1024 -w 4 -c 16
-python fil_ppf_create_mifs.py -f $RADIOHDL/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat -t 16 -p 1024 -w 4 -c 16
+python fil_ppf_create_mifs.py -f $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat -t 16 -p 1024 -w 4 -c 16
 
-python fil_ppf_create_mifs.py -f $RADIOHDL/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-nodc.dat -t 16 -p 1024 -w 4 -c 16
+python fil_ppf_create_mifs.py -f $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-nodc.dat -t 16 -p 1024 -w 4 -c 16
                                                                                 
 # run_pfir_coeff.m : channel filterbank (wb = 1)
 python fil_ppf_create_mifs.py -f ../hex/run_pfir_coeff_m_bypass_8taps_64points_16b.dat                  -t  8 -p   64 -w 1 -c 16
diff --git a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd
index 2cb9e0ed7645e269a70df7ae4101784e4bcff33a..11a108d75c59d6afb1af7f1490c1a6b88c46b627 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd
@@ -68,11 +68,11 @@
 --
 --   The reference dat file is generated by the Matlab program:
 --
---     $RADIOHDL/applications/apertif/matlab/run_pfir_coeff.m
+--     $RADIOHDL_WORK/applications/apertif/matlab/run_pfir_coeff.m
 --
 --   The MIF files are generated by the Python script:
 --
---     $RADIOHDL/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py
+--     $RADIOHDL_WORK/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py
 --
 --   The reference dat file and the MIF files use the same g_coefs_file_prefix.
 --   For the reference dat file this prefix is expanded by nof_taps, nof_bands
diff --git a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd
index 3e99ad78a3e8d4d4d74a7fd1d6e4a389cf3e17fa..103f01b59270e47ad366b88ee4c74a08102d75f9 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd
@@ -29,7 +29,7 @@
 --   The g_coefs_file_prefix dat-file and g_data_file dat-file are created by
 --   the Matlab script:
 --
---     $RADIOHDL/applications/apertif/matlab/run_pfir.m
+--     $RADIOHDL_WORK/applications/apertif/matlab/run_pfir.m
 --
 --   yields:
 --
@@ -51,7 +51,7 @@
 --   The MIF files are generated from the g_coefs_file_prefix dat-file by
 --   the Python script:
 --
---     $RADIOHDL/libraries/dsp/filter/src/python/
+--     $RADIOHDL_WORK/libraries/dsp/filter/src/python/
 --      python fil_ppf_create_mifs.py -f ../hex/run_pfir_m_pfir_coeff_fircls1_16taps_128points_16b.dat -t 16 -p 128 -w 1 -c 16
 --      python fil_ppf_create_mifs.py -f ../hex/run_pfir_m_pfir_coeff_fircls1_16taps_128points_16b.dat -t 16 -p 128 -w 4 -c 16
 --
diff --git a/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd b/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd
index 033699fc041aef2475ed79c77a6c427ea02301ae..68d13225235664348fd416716f9517c83147c72e 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd
@@ -22,7 +22,7 @@
 -- Purpose: Multi-testbench for fil_ppf_wide using file data
 -- Description:
 --   Verify fil_ppf_wide using coefficients and data generated by
---   Matlab $RADIOHDL/applications/apertif/matlab/run_pfir.m
+--   Matlab $RADIOHDL_WORK/applications/apertif/matlab/run_pfir.m
 --   
 -- Usage:
 --   > as 4
diff --git a/libraries/dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd b/libraries/dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd
index 176c202950f84f4cc68482ab51d5276939f55670..c76e25a5c80ea78416b0292cabbc09bb31d4601b 100644
--- a/libraries/dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd
+++ b/libraries/dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd
@@ -23,8 +23,8 @@
 -- Description:
 --   Verify wpfb_unit_wide using and data generated by Matlab scripts:
 --
---   - $RADIOHDL/applications/apertif/matlab/run_pfb.m
---   - $RADIOHDL/applications/apertif/matlab/run_pfb_complex.m
+--   - $RADIOHDL_WORK/applications/apertif/matlab/run_pfb.m
+--   - $RADIOHDL_WORK/applications/apertif/matlab/run_pfb_complex.m
 --
 -- Usage:
 --   > as 4
diff --git a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
index 87ef454477017013623910893437f2bbda842b65..cc5285d65f13cb922e06d09bbee6c2fecf80c9e8 100644
--- a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
+++ b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
@@ -25,8 +25,8 @@
 -- Description:
 --   This tb uses the Matlab stimuli and expected results obtained with:
 --
---   $RADIOHDL/applications/apertif/matlab/run_pfb.m
---   $RADIOHDL/applications/apertif/matlab/run_pfb_complex.m
+--   $RADIOHDL_WORK/applications/apertif/matlab/run_pfb.m
+--   $RADIOHDL_WORK/applications/apertif/matlab/run_pfb_complex.m
 --
 --   For more description see:
 --   . tb_fil_ppf_wide_file_data.vhd
diff --git a/libraries/io/ddr/hdllib.cfg b/libraries/io/ddr/hdllib.cfg
index 260e7b16a399fa3e8b30e121b0b4fb9218c74ec7..e095989542574effa2e6ded63b7f0bebdb20f18b 100644
--- a/libraries/io/ddr/hdllib.cfg
+++ b/libraries/io/ddr/hdllib.cfg
@@ -23,9 +23,9 @@ regression_test_vhdl =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
-    $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/io/ddr3/hdllib.cfg b/libraries/io/ddr3/hdllib.cfg
index 31551a6fba849e4cf4f78ffc5c7240839a289aac..fe384d7392455d52937ed2c907c1e9701e225b1c 100644
--- a/libraries/io/ddr3/hdllib.cfg
+++ b/libraries/io/ddr3/hdllib.cfg
@@ -28,13 +28,13 @@ regression_test_vhdl =
 
 [modelsim_project_file]
 modelsim_copy_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_AC_ROM.hex .
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_inst_ROM.hex .
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_sequencer_mem.hex .
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_AC_ROM.hex .
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_inst_ROM.hex .
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_sequencer_mem.hex .
 
 modelsim_compile_ip_files =
-     $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
-     #$RADIOHDL/libraries/io/ddr3/src/tcl/compile_ip.tcl
+     $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+     #$RADIOHDL_WORK/libraries/io/ddr3/src/tcl/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd b/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
index 924b2dfd30c34fae64cef35a8ebe5928cf2460da..c5353b22629392eedda2458ebc7059fce8b09583 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
@@ -121,7 +121,7 @@ PACKAGE ddr3_pkg IS
 
   CONSTANT c_ddr3_seq : t_ddr3_seq := (64, 1, 16, 4, 0, 5);  
   
-  -- Manually derived VHDL entity from Verilog module $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.v
+  -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.v
   COMPONENT ip_stratixiv_ddr3_uphy_4g_800_master IS
   PORT (
     pll_ref_clk                : IN    STD_LOGIC;                       --  pll_ref_clk.clk
@@ -173,7 +173,7 @@ PACKAGE ddr3_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from Verilog module $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.v
+  -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.v
   -- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
   COMPONENT ip_stratixiv_ddr3_uphy_4g_800_slave IS
   PORT (
diff --git a/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg b/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg
index de4897048d707e1c242551ae6ac97be8ec8c83b1..062af006fcfc12e03263e0a5622207dd98421aa4 100644
--- a/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg
+++ b/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg
@@ -1,6 +1,7 @@
 hdl_lib_name = unb1_eth_10g
 hdl_library_clause_name = unb1_eth_10g_lib
 hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag tr_10GbE
+hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
@@ -20,7 +21,7 @@ synth_top_level_entity =
 quartus_copy_files = quartus/qsys_unb1_eth_10g.qsys .  
 
 quartus_qsf_files = 
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_tcl_files =
     quartus/unb1_eth_10g_pins.tcl
@@ -28,4 +29,4 @@ quartus_tcl_files =
 quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_eth_10g/qsys_unb1_eth_10g/synthesis/qsys_unb1_eth_10g.qip
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
index f10bba2ef5364519137ae123d40d300d8960dcdc..1d9473211b4f12c609a38297f04888887af9304f 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
@@ -9,14 +9,14 @@
 # | ASTRON 2014.07.23.09:36:00
 # | MM slave port to conduit for the ETH module
 # | 
-# | $RADIOHDL/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
+# | $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
 # | 
 # |    ./avs2_eth_coe.vhd syn, sim
-# |    $RADIOHDL/libraries/base/common/src/vhdl/common_pkg.vhd syn, sim
-# |    $RADIOHDL/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
-# |    $RADIOHDL/libraries/technology/tse/tech_tse_pkg.vhd syn, sim
+# |    $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_pkg.vhd syn, sim
+# |    $RADIOHDL_WORK/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
+# |    $RADIOHDL_WORK/libraries/technology/tse/tech_tse_pkg.vhd syn, sim
 # |    ./eth_pkg.vhd syn, sim
-# |    $RADIOHDL/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
+# |    $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
 # | 
 # +-----------------------------------
 
diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl
index f10bba2ef5364519137ae123d40d300d8960dcdc..1d9473211b4f12c609a38297f04888887af9304f 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl
@@ -9,14 +9,14 @@
 # | ASTRON 2014.07.23.09:36:00
 # | MM slave port to conduit for the ETH module
 # | 
-# | $RADIOHDL/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
+# | $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
 # | 
 # |    ./avs2_eth_coe.vhd syn, sim
-# |    $RADIOHDL/libraries/base/common/src/vhdl/common_pkg.vhd syn, sim
-# |    $RADIOHDL/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
-# |    $RADIOHDL/libraries/technology/tse/tech_tse_pkg.vhd syn, sim
+# |    $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_pkg.vhd syn, sim
+# |    $RADIOHDL_WORK/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
+# |    $RADIOHDL_WORK/libraries/technology/tse/tech_tse_pkg.vhd syn, sim
 # |    ./eth_pkg.vhd syn, sim
-# |    $RADIOHDL/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
+# |    $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
 # | 
 # +-----------------------------------
 
diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2.tcl b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2.tcl
index f10bba2ef5364519137ae123d40d300d8960dcdc..1d9473211b4f12c609a38297f04888887af9304f 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2.tcl
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2.tcl
@@ -9,14 +9,14 @@
 # | ASTRON 2014.07.23.09:36:00
 # | MM slave port to conduit for the ETH module
 # | 
-# | $RADIOHDL/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
+# | $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
 # | 
 # |    ./avs2_eth_coe.vhd syn, sim
-# |    $RADIOHDL/libraries/base/common/src/vhdl/common_pkg.vhd syn, sim
-# |    $RADIOHDL/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
-# |    $RADIOHDL/libraries/technology/tse/tech_tse_pkg.vhd syn, sim
+# |    $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_pkg.vhd syn, sim
+# |    $RADIOHDL_WORK/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
+# |    $RADIOHDL_WORK/libraries/technology/tse/tech_tse_pkg.vhd syn, sim
 # |    ./eth_pkg.vhd syn, sim
-# |    $RADIOHDL/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
+# |    $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
 # | 
 # +-----------------------------------
 
diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2a.tcl b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2a.tcl
index f10bba2ef5364519137ae123d40d300d8960dcdc..1d9473211b4f12c609a38297f04888887af9304f 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2a.tcl
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2a.tcl
@@ -9,14 +9,14 @@
 # | ASTRON 2014.07.23.09:36:00
 # | MM slave port to conduit for the ETH module
 # | 
-# | $RADIOHDL/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
+# | $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
 # | 
 # |    ./avs2_eth_coe.vhd syn, sim
-# |    $RADIOHDL/libraries/base/common/src/vhdl/common_pkg.vhd syn, sim
-# |    $RADIOHDL/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
-# |    $RADIOHDL/libraries/technology/tse/tech_tse_pkg.vhd syn, sim
+# |    $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_pkg.vhd syn, sim
+# |    $RADIOHDL_WORK/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
+# |    $RADIOHDL_WORK/libraries/technology/tse/tech_tse_pkg.vhd syn, sim
 # |    ./eth_pkg.vhd syn, sim
-# |    $RADIOHDL/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
+# |    $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
 # | 
 # +-----------------------------------
 
diff --git a/libraries/technology/ddr/tech_ddr_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
index 2c34cc0b1db0f7c2e1abca761f2cb5f6491a2a2d..64314ddc33cf7363c3ae7c7fc9c394a67b62246f 100644
--- a/libraries/technology/ddr/tech_ddr_component_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
@@ -31,7 +31,7 @@ PACKAGE tech_ddr_component_pkg IS
   -- ip_stratixiv
   ------------------------------------------------------------------------------
   
-  -- Manually derived VHDL entity from Verilog module $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.v
+  -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.v
   COMPONENT ip_stratixiv_ddr3_uphy_4g_800_master IS
   PORT (
     pll_ref_clk                : IN    STD_LOGIC;                       --  pll_ref_clk.clk
@@ -83,7 +83,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
   
-  -- Manually derived VHDL entity from Verilog module $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.v
+  -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.v
   -- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
   COMPONENT ip_stratixiv_ddr3_uphy_4g_800_slave IS
   PORT (
@@ -134,7 +134,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from Verilog module $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.v
+  -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.v
   COMPONENT ip_stratixiv_ddr3_uphy_4g_single_rank_800_master IS
   PORT (
     pll_ref_clk                	: IN    STD_LOGIC;                       --  pll_ref_clk.clk
@@ -186,7 +186,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from Verilog module $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
+  -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
   -- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
   COMPONENT ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave IS
   PORT (
@@ -237,7 +237,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from Verilog module $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.v
+  -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.v
   COMPONENT ip_stratixiv_ddr3_uphy_16g_dual_rank_800 IS
   PORT (
     pll_ref_clk                : IN    STD_LOGIC;                       --  pll_ref_clk.clk
@@ -293,7 +293,7 @@ PACKAGE tech_ddr_component_pkg IS
   -- ip_arria10
   ------------------------------------------------------------------------------
   
-  -- Manually derived VHDL entity from VHDL file $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/generated/sim/ip_arria10_ddr4_4g_1600.vhd
+  -- Manually derived VHDL entity from VHDL file $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/generated/sim/ip_arria10_ddr4_4g_1600.vhd
   COMPONENT ip_arria10_ddr4_4g_1600 IS
   PORT (
     amm_ready_0         : out   std_logic;                                         --     ctrl_amm_avalon_slave_0.waitrequest_n
@@ -331,7 +331,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from VHDL file $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_2000/generated/sim/ip_arria10_ddr4_4g_2000.vhd
+  -- Manually derived VHDL entity from VHDL file $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_2000/generated/sim/ip_arria10_ddr4_4g_2000.vhd
   COMPONENT ip_arria10_ddr4_4g_2000 IS
   PORT (
     amm_ready_0         : out   std_logic;                                         --     ctrl_amm_avalon_slave_0.waitrequest_n
@@ -373,7 +373,7 @@ PACKAGE tech_ddr_component_pkg IS
   -- ip_arria10_e3sge3
   ------------------------------------------------------------------------------
   
-  -- Manually derived VHDL entity from VHDL file $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/generated/sim/ip_arria10_e3sge3_ddr4_4g_1600.vhd
+  -- Manually derived VHDL entity from VHDL file $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/generated/sim/ip_arria10_e3sge3_ddr4_4g_1600.vhd
   COMPONENT ip_arria10_e3sge3_ddr4_4g_1600 IS
   PORT (
     amm_ready_0         : out   std_logic;                                         --     ctrl_amm_avalon_slave_0.waitrequest_n
@@ -449,7 +449,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from VHDL file $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/generated/sim/ip_arria10_e3sge3_ddr4_4g_2000.vhd
+  -- Manually derived VHDL entity from VHDL file $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/generated/sim/ip_arria10_e3sge3_ddr4_4g_2000.vhd
   COMPONENT ip_arria10_e3sge3_ddr4_4g_2000 IS
   PORT (
     amm_ready_0         : out   std_logic;                                         --     ctrl_amm_avalon_slave_0.waitrequest_n
@@ -491,7 +491,7 @@ PACKAGE tech_ddr_component_pkg IS
   -- ip_arria10_e1sg
   ------------------------------------------------------------------------------
   
-  -- Manually derived VHDL entity from VHDL file $RADIOHDL/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim/ip_arria10_e1sg_ddr4_4g_1600.vhd
+  -- Manually derived VHDL entity from VHDL file $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim/ip_arria10_e1sg_ddr4_4g_1600.vhd
   COMPONENT ip_arria10_e1sg_ddr4_4g_1600 IS
   PORT (
     amm_ready_0         : out   std_logic;                                         --     ctrl_amm_avalon_slave_0.waitrequest_n
@@ -567,7 +567,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from VHDL file $RADIOHDL/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim/ip_arria10_e1sg_ddr4_4g_2000.vhd
+  -- Manually derived VHDL entity from VHDL file $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim/ip_arria10_e1sg_ddr4_4g_2000.vhd
   COMPONENT ip_arria10_e1sg_ddr4_4g_2000 IS
   PORT (
     amm_ready_0         : out   std_logic;                                         --     ctrl_amm_avalon_slave_0.waitrequest_n
diff --git a/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
index a715eed9a500e4b774924d50ca00325ad21a30a9..229a8e1824ac0c18c50960c22bd93b3ce967a9c0 100644
--- a/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
@@ -32,7 +32,7 @@ PACKAGE tech_ddr_mem_model_component_pkg IS
   ------------------------------------------------------------------------------
   
   -- Manually derived VHDL entity from Verilog module alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en.sv in:
-  -- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_example_design/simulation/vhdl/submodules/
+  -- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_example_design/simulation/vhdl/submodules/
  
   COMPONENT alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en IS
   GENERIC (
@@ -86,7 +86,7 @@ PACKAGE tech_ddr_mem_model_component_pkg IS
   ------------------------------------------------------------------------------
   
   -- Manually derived VHDL entity from ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd in:
-  -- $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_141/sim
+  -- $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_141/sim
   COMPONENT ed_sim_altera_emif_mem_model_141_z3tvrmq IS
 	PORT (
 		mem_ck      : in    std_logic_vector(0 downto 0)  := (others => '0'); -- mem_conduit_end.mem_ck
diff --git a/libraries/technology/hdllib.cfg b/libraries/technology/hdllib.cfg
index cba939b37b33a09217b287098ac26cf91eb79f07..4286581aace7feb963ddf2079aaf09ce9ca52ed6 100644
--- a/libraries/technology/hdllib.cfg
+++ b/libraries/technology/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology =
 
 synth_files =
     technology_pkg.vhd
-    $HDL_BUILD_DIR/<toolset_name>/technology_select_pkg.vhd
+    $HDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
 test_bench_files =
 
 regression_test_vhdl = 
@@ -15,10 +15,10 @@ regression_test_vhdl =
 
 [modelsim_project_file]
 modelsim_copy_files = 
-    technology_select_pkg_<toolset_name>.vhd $HDL_BUILD_DIR/<toolset_name>/technology_select_pkg.vhd
+    technology_select_pkg_<buildset_name>.vhd $HDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
 
 
 
 [quartus_project_file]
 quartus_copy_files =
-    technology_select_pkg_<toolset_name>.vhd $HDL_BUILD_DIR/<toolset_name>/technology_select_pkg.vhd
+    technology_select_pkg_<buildset_name>.vhd $HDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
diff --git a/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
index a33a1065533481db305df77f5fd27a2dd4f2eb47..ae2df593eb788c1bd856c3ef4ee6bfcc51f31e55 100644
--- a/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/clkbuf_global/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/clkbuf_global/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/clkbuf_global/generate_ip.sh b/libraries/technology/ip_arria10/clkbuf_global/generate_ip.sh
index f587c230c0f68ff5e93807ccb10e0383606b3f55..2a0e27bb2bd6977f2cfd1235d8e1f5a928bce982 100755
--- a/libraries/technology/ip_arria10/clkbuf_global/generate_ip.sh
+++ b/libraries/technology/ip_arria10/clkbuf_global/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg
index dab29a0357d53ad33059e86077df9dfb345b093e..e38e606ee6e735426a912c5499be80d51a91643a 100644
--- a/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/complex_mult/README.txt b/libraries/technology/ip_arria10/complex_mult/README.txt
index 6884ec9c599bf7d01ffed812c8a3a2a9bbb09398..3e33649f60f2659c1bd624a9ee30584f601033b4 100644
--- a/libraries/technology/ip_arria10/complex_mult/README.txt
+++ b/libraries/technology/ip_arria10/complex_mult/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/complex_mult
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/complex_mult
 
 1) Porting
 2) IP component
diff --git a/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
index 3605025500e6c982ffd70b0fa128c6ad8f6bef76..6827e855133514c5e2adaf423974175ad78b49f5 100644
--- a/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/complex_mult/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/complex_mult/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/complex_mult/generate_ip.sh b/libraries/technology/ip_arria10/complex_mult/generate_ip.sh
index 32f0f2c0987bdb4e93d39198bb6e34564e13cf27..ae842eb1c461268cac0a71ecf5772fc721a539e6 100755
--- a/libraries/technology/ip_arria10/complex_mult/generate_ip.sh
+++ b/libraries/technology/ip_arria10/complex_mult/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10/complex_mult/hdllib.cfg
index 8e7b0c0c0b6d2db8a63cabb5fd9b856198f82366..09e6c2196de5c23b7e2a8dbb22fdc642ba91ea5b 100644
--- a/libraries/technology/ip_arria10/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10/complex_mult/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/ddio/README.txt b/libraries/technology/ip_arria10/ddio/README.txt
index 6ba19729bb9e0c499398db1ef5661a55845e419f..1823e822ffac72fd6dfccb16917ab9972bed2a75 100755
--- a/libraries/technology/ip_arria10/ddio/README.txt
+++ b/libraries/technology/ip_arria10/ddio/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/ddio
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ddio
 
 Contents:
 
diff --git a/libraries/technology/ip_arria10/ddio/compile_ip.tcl b/libraries/technology/ip_arria10/ddio/compile_ip.tcl
index 701077b07f4c9685881b5c84af92203ada875830..430497004bbcb70c56ca34534f296ffe2fc3fdf6 100644
--- a/libraries/technology/ip_arria10/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddio/compile_ip.tcl
@@ -26,7 +26,7 @@ set IPMODEL "SIM";
 if {$IPMODEL=="PHY"} {
 
     # This file is based on Qsys-generated file msim_setup.tcl.
-    set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/ddio/generated/"
+    set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddio/generated/"
         
     #vlib ./work/         ;# Assume library work already exists
     vmap ip_arria10_ddio_in_1_altera_gpio_core_150  ./work/
@@ -52,7 +52,7 @@ if {$IPMODEL=="PHY"} {
 } else {
 
     # This file uses a behavioral model because the PHY model does not compile OK, see README.txt.
-    set SIM_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/ddio/sim/"
+    set SIM_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddio/sim/"
     
     vcom "$SIM_DIR/ip_arria10_ddio_in_1.vhd"
     vcom "$SIM_DIR/ip_arria10_ddio_out_1.vhd"
diff --git a/libraries/technology/ip_arria10/ddio/generate_ip.sh b/libraries/technology/ip_arria10/ddio/generate_ip.sh
index 0f136b9599ba9a82d8a5fd69e63c7ccae36569d8..a3eae3c6801a76b29fbee92740a5d8c11297070b 100755
--- a/libraries/technology/ip_arria10/ddio/generate_ip.sh
+++ b/libraries/technology/ip_arria10/ddio/generate_ip.sh
@@ -34,7 +34,7 @@
 #   
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/ddio/hdllib.cfg b/libraries/technology/ip_arria10/ddio/hdllib.cfg
index f3881529baccfb2ae8dd6fca916d93d8f0816464..b3a726e9aae11cd489522fe0666af1d239c2d94c 100644
--- a/libraries/technology/ip_arria10/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddio/hdllib.cfg
@@ -13,7 +13,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/ddio/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/ddio/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
index 2fce2100258cefe5848361703adb2f4c8ec100ac..5dd0355376532c7b3214892a6530bd077cb58587 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_4g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_1600/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
index 933716aae34cb0cdd1556cc362b22023703570a9..ffbd501ac2f754bbc505a70c1faa6c686c2d72e5 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_1600/generated/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/doc/README_ddr4.txt b/libraries/technology/ip_arria10/ddr4_4g_1600/doc/README_ddr4.txt
index b2efc7da1dbb8d00fabc3af7e65f233934abfe93..6799054f2c0179804f2a228dbdf588306dc5a37c 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/doc/README_ddr4.txt
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/doc/README_ddr4.txt
@@ -142,7 +142,7 @@ Quartus IP catalog "Arria10 External Memory Interface" fill in:
 
   run:
   cd emif_0_example_design
-  . ${RADIOHDL}/tools/quartus/set_quartus unb2 && quartus_sh -t make_qii_design.tcl
+  . ${RADIOHDL_GEAR}/quartus/set_quartus unb2 && quartus_sh -t make_qii_design.tcl
 
   add to qii/ed_synth.qsf:
   source ../../unb2_pins_ed_synth.tcl
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/generate_ip.sh b/libraries/technology/ip_arria10/ddr4_4g_1600/generate_ip.sh
index e1b94a498f1de40bb2cb0a7a0df3b7f87e828181..9300771833cbd9551f3727dbc107b2eff386c60a 100755
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/generate_ip.sh
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg
index df28a123cd9738269d9269e6a85ba0bbaf8ca98e..bf240135084c43b5d81534fd6adce5fc3687fd0e 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
index f95c590f229ef4a5db517bedc1d8be092adbf294..3bd52fc0270ab1f1fa7bd13720bcb94c23bf7f5d 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_4g_2000/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_2000/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl b/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl
index 562340ef4a3372ebdae0727543acd3fefc48ab96..91add01c14d05f35e42525157fa5332d4264a84b 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_2000/generated/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10/ddr4_4g_2000/generate_ip.sh b/libraries/technology/ip_arria10/ddr4_4g_2000/generate_ip.sh
index ee4f6f3fb14d080c4c4dea86b892685c322f1510..edad8d1cf7aee682361563861e20f4ab662c6e07 100755
--- a/libraries/technology/ip_arria10/ddr4_4g_2000/generate_ip.sh
+++ b/libraries/technology/ip_arria10/ddr4_4g_2000/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg
index b11af9b2177265a5a6f99679b205428d9b5eb2e2..6b605ee02fcb6d736af6323c8911d4496289c29b 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
index b68632f744ca0821374bd4cfe1e139085b97d1fe..24bb783efeda7bd7e3e3f9587f1caf695c27371f 100644
--- a/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_8g_2400/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_8g_2400/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl
index 8aef634019339efdf02c770a8b46a9c74436e73b..e1301d8ab0afd141a15613adc3972036a6da6be8 100644
--- a/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_8g_2400/generated/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10/ddr4_8g_2400/generate_ip.sh b/libraries/technology/ip_arria10/ddr4_8g_2400/generate_ip.sh
index a6c63a8a24ee1edabe18ddfb0f90cadb6c05a857..0eed84da4b66feb6c634dea9b7b8b1b3829742db 100755
--- a/libraries/technology/ip_arria10/ddr4_8g_2400/generate_ip.sh
+++ b/libraries/technology/ip_arria10/ddr4_8g_2400/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg
index 9a802df0eebc0d0a45854ed9c157a6a8be9d28b1..7272be213a74166afafdcdc64815219ca09e22fa 100644
--- a/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/README.txt b/libraries/technology/ip_arria10/ddr4_mem_model_141/README.txt
index 59bbb650230ca9fb1e6e1e7f53692e27dc97a4e7..4921c9d617ae8bda0524b60e8a2633082c6931a2 100644
--- a/libraries/technology/ip_arria10/ddr4_mem_model_141/README.txt
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/ddr4_mem_model
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_mem_model
 
 1) DDR4 memory simulation model
 2) Automated scripts and one time manual actions
@@ -11,7 +11,7 @@ README.txt for $RADIOHDL/libraries/technology/ip_arria10/ddr4_mem_model
 The DDR memory model is obtained from the example design that can be generated with Qsys when a DDR IP component is defined.
 The first DDR4 component that was created is available via:
 
-  $env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_4g_1600/ip_arria10_ddr4_4g_1600.qsys
+  $env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_1600/ip_arria10_ddr4_4g_1600.qsys
 
 Unfortunately the example design needs to be created via the GUI by pressing the 'Example Design...' button, because the qsys-generate command
 that is used in ddr4_4g_1600/generate_ip.sh to create the component does not have an option to also create the example design. After that the
@@ -21,20 +21,20 @@ memory model have been copied to a fixed location in SVN. In this way it is no l
 
 In the example design for ddr4_4g_1600 the generic core files of the DDR model are located at:
 
-  $env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_core_ddr4_141
+  $env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_core_ddr4_141
 
 The size specific entity of the DDR model is created in:
 
-  $env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_141/ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd
+  $env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_141/ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd
 
 The generic core files of the DDR memory model are the same for every DDR size. These files only depend on the Quartus tool version as indicated by 141
 (Quartus 14.1) in their name. Therefore the generic core files have been copied to:
 
-  $env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core
+  $env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core
 
 The size specific DDR component file is copied to:
 
-  $env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_4g_1600/ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd
+  $env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_4g_1600/ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd
   
 and other size DDR component files can be store there as well.
 
@@ -49,7 +49,7 @@ but it is good to manually check with Linux 'diff' as in diff_mem_model.sh that
 
 2) Automated scripts and one time manual actions
 
-Relative to $RADIOHDL/libraries/technology/ip_arria10/:
+Relative to $RADIOHDL_WORK/libraries/technology/ip_arria10/:
 
 - ddr4_4g_1600/ip_arria10_ddr4_4g_1600.qsys : Qsys definition file for size and speed specific DDR4 controller
 - ddr4_4g_1600/generate_ip.sh               : Use qsys-generate to create the size and speed specific DDR4 controller
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl
index ff31689fcc9857e0751649d8fa2f6f246ca948cc..94d8e8d0c54deb3d953c9755d69035224bb106ed 100644
--- a/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl
@@ -20,9 +20,9 @@
 #
 #------------------------------------------------------------------------------
 
-# This file is based on Qsys-generated file $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/mentor/msim_setup.tcl.
+# This file is based on Qsys-generated file $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/mentor/msim_setup.tcl.
 # 
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_mem_model_141"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_mem_model_141"
 
 # Assume library work already exists
 vmap ed_sim_altera_emif_mem_model_core_ddr4_141 ./work/
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/diff_mem_model.sh b/libraries/technology/ip_arria10/ddr4_mem_model_141/diff_mem_model.sh
index 32f282b561f20e4bef942754cbac0596025527f5..bd39700d7f2aafbd6471f4e1a67d27461681c523 100755
--- a/libraries/technology/ip_arria10/ddr4_mem_model_141/diff_mem_model.sh
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/diff_mem_model.sh
@@ -31,7 +31,7 @@
 #
 #   eg:
 #
-#   ./diff_mem_model.sh $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design
+#   ./diff_mem_model.sh $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design
 #
 
 EXAMPLE_DESIGN_DIR=${1}
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/generate_mem_model.sh b/libraries/technology/ip_arria10/ddr4_mem_model_141/generate_mem_model.sh
index d001ff86d3db82df5f008dd6bb9d20f6fafeb95a..631fcbba98a94ba1754ca58a36abf394b1ef09b6 100755
--- a/libraries/technology/ip_arria10/ddr4_mem_model_141/generate_mem_model.sh
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/generate_mem_model.sh
@@ -43,7 +43,7 @@
 #   ./generate_mem_model.sh ../ddr4_8g_2400/ddr4_inst_example_design
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_mem_model_141/hdllib.cfg
index c574aeda56d607e0ed15db84ecc6d51e6e9db0f8..bdd0226b2496dfdc4ee354d1d3a436e73ad11878 100644
--- a/libraries/technology/ip_arria10/ddr4_mem_model_141/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/fifo/README.txt b/libraries/technology/ip_arria10/fifo/README.txt
index 48f19d8f0da8b25abe9f0f1f63591777534c35c5..cfe2a2a2d88c7a058d3596d9b1297941b2b0e8a3 100755
--- a/libraries/technology/ip_arria10/fifo/README.txt
+++ b/libraries/technology/ip_arria10/fifo/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/fifo
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/fifo
 
 Contents:
 
diff --git a/libraries/technology/ip_arria10/fifo/generate_ip.sh b/libraries/technology/ip_arria10/fifo/generate_ip.sh
index 7b86d6fd9cd1a61465e508f5ad3a24d98caff086..11005f95c6c894c6e0a9143d58263d6c12f02d30 100755
--- a/libraries/technology/ip_arria10/fifo/generate_ip.sh
+++ b/libraries/technology/ip_arria10/fifo/generate_ip.sh
@@ -39,7 +39,7 @@
 #   
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
index f4f1a6b202daa8caf849ad3642126a9e51a10ab6..94b0a67c51d3bd0140cb7b4d16ac3b26c2ae28b5 100644
--- a/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/flash/asmi_parallel/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/flash/asmi_parallel/generated/sim"
 
 vmap ip_arria10_asmi_parallel_altera_asmi_parallel_150 ./work/
 
diff --git a/libraries/technology/ip_arria10/flash/asmi_parallel/generate_ip.sh b/libraries/technology/ip_arria10/flash/asmi_parallel/generate_ip.sh
index fc5fb64f74804ae740fe0ef017ba251b1356112e..89aa2bdc59c5d1929bb9855b84549abe85f9bc56 100755
--- a/libraries/technology/ip_arria10/flash/asmi_parallel/generate_ip.sh
+++ b/libraries/technology/ip_arria10/flash/asmi_parallel/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
index ff92bbf78ccbd3d2818665be6fca15372785f11f..b07ad14a4324b1cbef7ab1545e532684aeada43a 100644
--- a/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
index f5746aa6f660d8e92f86ae9dc42719eda4d30e1d..525eab6a87858831ec23804a673ee3d31db94264 100644
--- a/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/flash/remote_update/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/flash/remote_update/generated/sim"
 
 vmap ip_arria10_remote_update_altera_remote_update_core_150  ./work/
 vmap ip_arria10_remote_update_altera_remote_update_150       ./work/
diff --git a/libraries/technology/ip_arria10/flash/remote_update/generate_ip.sh b/libraries/technology/ip_arria10/flash/remote_update/generate_ip.sh
index 1174a08ec00891f6d0ded7ef76c57c7fd6bda664..806e3f578adb14ca48e7e8e36caa6c35cbd88395 100755
--- a/libraries/technology/ip_arria10/flash/remote_update/generate_ip.sh
+++ b/libraries/technology/ip_arria10/flash/remote_update/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
index a1da1edce33e8dd6bac0b2befbf005eeb11ffcfb..732cd7b07254de1a80b48bb44ba54b6b1935db5b 100644
--- a/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
index 709861b137c381ddde8eaf114a9ea36640131fd9..9611ac9b640e6937da631f0a8e67af2508e6b8f2 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/fractional_pll_clk125/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/fractional_pll_clk125/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk125/generate_ip.sh b/libraries/technology/ip_arria10/fractional_pll_clk125/generate_ip.sh
index e4a41166da164dcffb2ff241d5b5501aec4cd322..3be0eff6064a9e687c9215423ac31906e8a52c89 100755
--- a/libraries/technology/ip_arria10/fractional_pll_clk125/generate_ip.sh
+++ b/libraries/technology/ip_arria10/fractional_pll_clk125/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg
index e3e1e4ab6952a4d1b6f514a1076932043c28fb56..825eb56fb47688051e777c31e1be53e319aa6cd7 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
index 032b1953a939ad8a1feb23c1c0a7377377338c2f..09f0c82f72c1d92c125e6b881f965cc730ee5896 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/fractional_pll_clk200/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/fractional_pll_clk200/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk200/generate_ip.sh b/libraries/technology/ip_arria10/fractional_pll_clk200/generate_ip.sh
index f13fa2ffe330f3065fd15bd931fb13fa2ee8a02a..7a5fa7f5906984b1837728839e20853d9144e5fa 100755
--- a/libraries/technology/ip_arria10/fractional_pll_clk200/generate_ip.sh
+++ b/libraries/technology/ip_arria10/fractional_pll_clk200/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg
index 9efe341b9cdd9407d62381dfb8f5a35788e607e3..4b8ecae7488f796d9bddbd69806d7d185420c096 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/generate-all-ip.sh b/libraries/technology/ip_arria10/generate-all-ip.sh
index 6f3aacaf5cc9366d5e0752c364edc96b32d42816..f31bf6126c42ea64a976ace746d7024c75ec5bad 100755
--- a/libraries/technology/ip_arria10/generate-all-ip.sh
+++ b/libraries/technology/ip_arria10/generate-all-ip.sh
@@ -1,6 +1,6 @@
 #!/bin/bash 
 
-files=`find $RADIOHDL/libraries/technology/ip_arria10 -name 'generate_ip.sh' `
+files=`find $RADIOHDL_WORK/libraries/technology/ip_arria10 -name 'generate_ip.sh' `
 
 echo -e "About to generate the following IP blocks:\n$files\n"
 
diff --git a/libraries/technology/ip_arria10/mac_10g/README.txt b/libraries/technology/ip_arria10/mac_10g/README.txt
index 39766e46ccf196734329497a8fd824781a9b3fc1..1809358e9cffbc914b28099a977ad0b8ff8cc4b6 100644
--- a/libraries/technology/ip_arria10/mac_10g/README.txt
+++ b/libraries/technology/ip_arria10/mac_10g/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/mac_10g
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/mac_10g
 
 1) Porting
 2) IP component
diff --git a/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
index b73a1147b97facd0be71176efde57dac1227f0d7..0f37f969c407d542e6c39cb771790847d679b240 100644
--- a/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
@@ -26,8 +26,8 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/mac_10g/generated/sim"
-set IP_TBDIR "$env(RADIOHDL)/libraries/technology/ip_arria10/mac_10g/generated_tb/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/mac_10g/generated/sim"
+set IP_TBDIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/mac_10g/generated_tb/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/mac_10g/generate_ip.sh b/libraries/technology/ip_arria10/mac_10g/generate_ip.sh
index 3ea107bec536f0059208133f931916b5692cf7e8..ec19d818167141c516e9e58ff93057066eb2864c 100755
--- a/libraries/technology/ip_arria10/mac_10g/generate_ip.sh
+++ b/libraries/technology/ip_arria10/mac_10g/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
index 432addcdba34207a925193a706ec1575ad870875..fe9d8cfe4c8dd251033d72c7030f35d7a7f9c677 100644
--- a/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
 test_bench_files = 
     # The generated testbench is listed here to create a simulation configuration for it. However
     # the tb is commented because it is not useful, see generate_ip.sh.
-    #$RADIOHDL/libraries/technology/ip_arria10/mac_10g/generated_tb/generated/sim/ip_arria10_mac_10g_tb.vhd
+    #$RADIOHDL_WORK/libraries/technology/ip_arria10/mac_10g/generated_tb/generated/sim/ip_arria10_mac_10g_tb.vhd
 
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/README.txt b/libraries/technology/ip_arria10/phy_10gbase_r/README.txt
index 3d1237a61bcab34db7cc557f382b6aee283732c1..f834dcc99eb443ed8c4fb4a82c4d8bba55fb4623 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/README.txt
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r
 
 1) Porting
 2) IP component
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
index 2783be20538dd109eba49020954b8ae661f4893e..a2f5e5be1005fd0c87a9b9d2b4213100f20d2752 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/phy_10gbase_r/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/phy_10gbase_r/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/generate_ip.sh b/libraries/technology/ip_arria10/phy_10gbase_r/generate_ip.sh
index bb732ad54dfcdc5f9c0f3a00f8433ac48191d7b9..5b4909fd4ede29a480688d77a36d0222a992240f 100755
--- a/libraries/technology/ip_arria10/phy_10gbase_r/generate_ip.sh
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
index a9da96f5ea9795f156168e4be17199426ef20f02..1d90fe04e695499b479765ee256c5a1dc46834a9 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
index 907ffbb15bc73548a506ca7f7a900c1a6f6dfe71..7130d548d2b43fb60c27b172af0354138c42070e 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/phy_10gbase_r_12/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/phy_10gbase_r_12/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_12/generate_ip.sh b/libraries/technology/ip_arria10/phy_10gbase_r_12/generate_ip.sh
index f8fe9dbf9924fe85ce0b4978c4180d70f94c02c7..0054ec1bb8a31f3476d196c22cc74c2ee5497971 100755
--- a/libraries/technology/ip_arria10/phy_10gbase_r_12/generate_ip.sh
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_12/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg
index df2b66e38e77302107d81bfa4461335744ad63db..52f291e04463be06a3d4fba30a8368462d11e82c 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
index 761c5fa7f6dedbf8ec1fe1a5384964fcf6ce1e21..ecd8cac0a1db77d42b518b869cd7520538d58e4f 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/phy_10gbase_r_24/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/phy_10gbase_r_24/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_24/generate_ip.sh b/libraries/technology/ip_arria10/phy_10gbase_r_24/generate_ip.sh
index b6193040d70e358551ae16ad21407360672a55d5..236321fe683df54b59cc8c6703723616af3834ec 100755
--- a/libraries/technology/ip_arria10/phy_10gbase_r_24/generate_ip.sh
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_24/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
index ca1857cf4427a2f62e177dc9c2f281df595a0998..f203933b41feabc4462724aea3e576f8d05f8172 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
index e78106bd1ee6032a34bec37299b08f29fedf087f..319a66812304e280e64a50fbec79edbfc9d25358 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/phy_10gbase_r_4/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/phy_10gbase_r_4/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_4/generate_ip.sh b/libraries/technology/ip_arria10/phy_10gbase_r_4/generate_ip.sh
index 795a08c05682316aa3c6162f76a97975ebbeca12..deee2d03d93a855cf452d54f921c2456cffee856 100755
--- a/libraries/technology/ip_arria10/phy_10gbase_r_4/generate_ip.sh
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_4/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg
index b41ddab9729d0531ab11a620f2ee470721ba2bb0..84ed2d979e89683f862066ff9283bb11d2fa4584 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
index 51a15947a3ea56660cfe5997cc39994a5f0760a7..89d1df9134cef0c6b0081d0b886cae0179b5b028 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/phy_10gbase_r_48/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/phy_10gbase_r_48/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_48/generate_ip.sh b/libraries/technology/ip_arria10/phy_10gbase_r_48/generate_ip.sh
index 658a300732a2c455d501cce90cf192653abfd4a1..16e4ca4479b53402e6397ad4df49061c1dc1606c 100755
--- a/libraries/technology/ip_arria10/phy_10gbase_r_48/generate_ip.sh
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_48/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg
index 0a0ae1bc3b39c41d94730c8cf001f35b5b93663d..23b996d5d148241af2f163e9450d3dde27559e25 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
index c138d560d338883763b84a898b516d868269b690..ceb880b97151f1e52528716b1e5e3dbf763ad785 100644
--- a/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/pll_clk125/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/pll_clk125/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/pll_clk125/generate_ip.sh b/libraries/technology/ip_arria10/pll_clk125/generate_ip.sh
index e0036549162a3f7fbbe7bb0026515281b9b7e84f..6e80538495ae1a8f43dcddcdd1b246d6e3ef9211 100755
--- a/libraries/technology/ip_arria10/pll_clk125/generate_ip.sh
+++ b/libraries/technology/ip_arria10/pll_clk125/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
index fbef174b2a9c3b185cb16a44ae1e3548aac79646..ba0c574b95aa6fe301befe681227a15e3f3e87cd 100644
--- a/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
index ffec45c41bfa93a1af191e848c37a8c7757c229c..45f591f9ebf41e504a4c58b319ea086c1af08c90 100644
--- a/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/pll_clk200/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/pll_clk200/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/pll_clk200/generate_ip.sh b/libraries/technology/ip_arria10/pll_clk200/generate_ip.sh
index 61e5e819cad7c443c5af88f85e1aa6de8abfac89..15f6b491073d5ac3f46284d2bb84898b80ef5264 100755
--- a/libraries/technology/ip_arria10/pll_clk200/generate_ip.sh
+++ b/libraries/technology/ip_arria10/pll_clk200/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg
index 03522a7e1e346152f097664fc4cdd1f995a895ed..876299925e1650ef6afee9903fdc0e4d54f26f5b 100644
--- a/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
index ce59df714da77afc1aee98d2e137144b8b65d3f7..8d6c1ffe3a9a802a240f3a4ac23ef0f2e77bb616 100644
--- a/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/pll_clk25/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/pll_clk25/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/pll_clk25/generate_ip.sh b/libraries/technology/ip_arria10/pll_clk25/generate_ip.sh
index a71dc4b23a1a649d67e0889029715dc2ae7f6642..ee890b1030eb03074285410f8331129d40224a1b 100755
--- a/libraries/technology/ip_arria10/pll_clk25/generate_ip.sh
+++ b/libraries/technology/ip_arria10/pll_clk25/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg
index 55e9e73b6a9383e02e1eef7d2dc48e419f273914..85ec82a965e60edac43dd86f760a307faffc72ab 100644
--- a/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
index 7a9eb933fb9fca235de94ff16f565473ba486f0e..b9f8625f8c0f54a5f49dc8bf7fecafea804b1501 100644
--- a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/generate_ip.sh b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/generate_ip.sh
index fd6d0e68778bb53ae27c0aeb63b1f199ff81d722..0ab8ca262f3602d674a92c6f6375c4512fe87286 100755
--- a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/generate_ip.sh
+++ b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg
index deacb41f9e273b0f249c15c52b3d0f112ea2916e..7fe81748c95ed17355f0fe553b1ea509d54c7452 100644
--- a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/ram/README.txt b/libraries/technology/ip_arria10/ram/README.txt
index 334f704974a248b117cd90c5b6b1af9286c49322..a9fe41102a7d2cec63b7c2f3846b28447c1b4bc0 100755
--- a/libraries/technology/ip_arria10/ram/README.txt
+++ b/libraries/technology/ip_arria10/ram/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/ram
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ram
 
 Contents:
 
diff --git a/libraries/technology/ip_arria10/ram/generate_ip.sh b/libraries/technology/ip_arria10/ram/generate_ip.sh
index c6dac88191b280e1924fa19f8733b9d152445d09..c1ca91ebd03b0d97ba2f14f2f8740f1c59263ebc 100755
--- a/libraries/technology/ip_arria10/ram/generate_ip.sh
+++ b/libraries/technology/ip_arria10/ram/generate_ip.sh
@@ -39,7 +39,7 @@
 #   
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
index 8011a1bc4130df89e84a615065a415c93472a4ff..fa0b733b4853cc48862ca4e049c911dce64dff3e 100644
--- a/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/temp_sense/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/temp_sense/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/temp_sense/generate_ip.sh b/libraries/technology/ip_arria10/temp_sense/generate_ip.sh
index a64704b54a08406c93dd32e279e819493f5dfe47..3bad9f0bb204073f1866c0c03eeffc568b68149a 100755
--- a/libraries/technology/ip_arria10/temp_sense/generate_ip.sh
+++ b/libraries/technology/ip_arria10/temp_sense/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10/temp_sense/hdllib.cfg
index 5266b8bcf507c411827d3305a781fd0523ddf391..0d4162d734d3173cd98e1b9b9fbdafd04e4358ac 100644
--- a/libraries/technology/ip_arria10/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10/temp_sense/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 #modelsim_compile_ip_files =
-#    $RADIOHDL/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
+#    $RADIOHDL_WORK/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
index 92551c4742fa49f1c466a22abb3890963a094c25..51e4722bd7e3add5f21714c9bf2351cf5e4341fa 100644
--- a/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/transceiver_pll_10g/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/transceiver_pll_10g/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/generate_ip.sh b/libraries/technology/ip_arria10/transceiver_pll_10g/generate_ip.sh
index d52cddda76b9768775c7ae1edbdbd81df9c22e74..d42f2ed74c4a5917545f830d683f2ce2355e6a90 100755
--- a/libraries/technology/ip_arria10/transceiver_pll_10g/generate_ip.sh
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
index 0858e529e88f7920f15a49c92012f6d6a04f4bd7..75dcfa5eca31bedbd576b633855b598cd41f8ea1 100644
--- a/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
index e6ea2fbfb0f8584da0fb8862ba05cb4016943d5a..69d241877320e2292a00293b4adf82a1827fce59 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/transceiver_reset_controller_1/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/transceiver_reset_controller_1/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/generate_ip.sh b/libraries/technology/ip_arria10/transceiver_reset_controller_1/generate_ip.sh
index c6562df088914ce097b48be74d2a0263fb41dc22..7fc9610b9d0b8faea0a8614ef946495849fe2c6f 100755
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_1/generate_ip.sh
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
index 180275109acb0b7f090d075b0ca2430f892e2097..11f7683e31cf1614e911206328e297c91547a6b4 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
index eb0fa8bfa87c116687f3f11d3c641aebbec867b9..22ce7e0c271a82712cf70a260e84be6fe772fae3 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/transceiver_reset_controller_12/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/transceiver_reset_controller_12/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_12/generate_ip.sh b/libraries/technology/ip_arria10/transceiver_reset_controller_12/generate_ip.sh
index 053a98b3a8a22a66998b40bc9cb0aedfaa0319e8..df0523bb938800177b757c8b4dd6d66b3147ba66 100755
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_12/generate_ip.sh
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_12/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg
index 11b372a73fb6c239c89d5b23051b19376c908492..c6a5d3b797c1d4ee5d6983665f3c0d2ac4320d8f 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
index 368d36c564913e30e1695d38df28f0d7c90ed66b..1a97798dde2932572b1feead56ca43d71af97743 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/transceiver_reset_controller_24/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/transceiver_reset_controller_24/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_24/generate_ip.sh b/libraries/technology/ip_arria10/transceiver_reset_controller_24/generate_ip.sh
index 0b67c011a23c13c4bb7936599c075f36d411372d..5d2df2513ef1f4e4e10788b09e8f6bee1473f2fd 100755
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_24/generate_ip.sh
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_24/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
index bb7b3626ee122d11066bb07c0ca4f11c80659816..490fa6c30d7f318893efd48ee2e8a7e43d78c32d 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
index 21e3d5e43f3b78e395cf34f19c4d2e191d955fa8..1d2e7d499738e57987f28d28adc2fb8db607b818 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/transceiver_reset_controller_4/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/transceiver_reset_controller_4/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_4/generate_ip.sh b/libraries/technology/ip_arria10/transceiver_reset_controller_4/generate_ip.sh
index a1132f0673a6d067525348712a1360c28579d46b..9fbe56760ff48d450d8c803df12d8e0482944e39 100755
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_4/generate_ip.sh
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_4/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg
index fa0c96d38c6a383b35284b4b00e8073e16a71ae4..d24b6726af1afc1e5a1633d7ac36b81f7714de97 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
index 23d218e509264edce1f1b7920a4fa71302c7f895..62da163837b3521bc9e2ba2f5cef403c7e4971ee 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/transceiver_reset_controller_48/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/transceiver_reset_controller_48/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_48/generate_ip.sh b/libraries/technology/ip_arria10/transceiver_reset_controller_48/generate_ip.sh
index 0f94b206ad421ceb373670895923a47f7c51cc84..1e975d9e0302defee412257bef8dffef8350be6f 100755
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_48/generate_ip.sh
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_48/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg
index 0db9821b674a4b34d06cc83f433c63c960e01ebb..58e0413fd08b143c8ac39c727ee9ff9d90680c34 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/README.txt b/libraries/technology/ip_arria10/tse_sgmii_gx/README.txt
index 846e784f55181cb84a27903a7e897ac3d01fa383..fa105db173e0dc963f59b1e10b143cf5cc782167 100755
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/README.txt
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/README.txt
@@ -1,8 +1,8 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_gx
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx
 
 The ip_arria10_tse_sgmii_gx IP was ported to Quartus 14.0a10 for Arria10 by creating it in Qsys using the same parameter settings as the ip_arria10_tse_sgmii_lvds, but with GX IO.
 
 The tb_ip_arria10_tse_sgmii_gx.vhd verifies the DUT and simulates OK.
 
-For more information see: $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
+For more information see: $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
 
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
index df199ab12ac6244670f1c34f034d57ca2f4d0176..22a2478a6c2c24a7563d556a71e18b11dbe72ebb 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
 # - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/tse_sgmii_gx/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/tse_sgmii_gx/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/generate_ip.sh b/libraries/technology/ip_arria10/tse_sgmii_gx/generate_ip.sh
index c993bc3aa38ffcd2541d93ff816753b6b7015b6d..949fda1d55c536a60e8187c6a12def9ebbebd463 100755
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/generate_ip.sh
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
index aad3d57375cbecb35f6430da62c800625254a2b7..26d59ecf13f191248414d36b5235f63d8bd8b19e 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
     
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt b/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
index db333f5675fc3468ba413ea5e12310908949a135..ae9545e000d01218915aa99cdf67e00146add477 100755
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds
 
 Contents:
 1) Porting
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
index cd1d34428e96ba0d8d922ed3898a8900f4f51d1c..395170e9f5ae765c201cde515fc867c5945bdbee 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
 # - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/tse_sgmii_lvds/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/tse_sgmii_lvds/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/generate_ip.sh b/libraries/technology/ip_arria10/tse_sgmii_lvds/generate_ip.sh
index 92e4b67be2812d5ad163745aabbe360f71dfbc61..16270092806ea722f983b9db527c1a2a4b810582 100755
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/generate_ip.sh
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
index d8a27e38483ade4d553e8a88616a30334cc57f2d..694b6c70f6bb42b69dbb875b219768ec5b516972 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
index ae08e35d37b326c97f6408db138752a9ba4b3f21..0e319959043dea8f60899f2629bdc3ac11058ec0 100644
--- a/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/voltage_sense/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/voltage_sense/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/voltage_sense/generate_ip.sh b/libraries/technology/ip_arria10/voltage_sense/generate_ip.sh
index 86b053bc2e17e200c14bcee6308fff236cd42321..44c0232a86536951e3a6d0e0adbe92f7b5bf8e03 100755
--- a/libraries/technology/ip_arria10/voltage_sense/generate_ip.sh
+++ b/libraries/technology/ip_arria10/voltage_sense/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
index 7268d16a041547fac9b27bf6dc3e2b21198223b8..a2e3ec5155bb6187b3401ee0ca4293a9be493c10 100644
--- a/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
 [modelsim_project_file]
 # There is no simulation model for the FPGA voltage sensor IP
 #modelsim_compile_ip_files =
-#    $RADIOHDL/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
+#    $RADIOHDL_WORK/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl
index 8900569e3fc2394d17f30584c10c0719e615a243..44e8d9f4bcc1d5ef44759c50e1997242107f695e 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/mac_10g/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/mac_10g/generated/sim"
 
 vmap alt_em10g32_170 ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/hdllib.cfg
index 4e64f58057901ee77c5dd788fa352e9050f84272..383c4a3204bf774ef51740745a6d4e8c0d140de0 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
 test_bench_files = 
     # The generated testbench is listed here to create a simulation configuration for it. However
     # the tb is commented because it is not useful, see generate_ip.sh.
-    #$RADIOHDL/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
+    #$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
 
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl
index b9a61bdaafea6e56df44d428160f1b7daab89fb4..ff2e50d8d208b7dd34b5d16e49023d1f0a3b3c33 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
 
 vmap  alt_mem_if_jtag_master_170            ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/hdllib.cfg
index 6bd71be1be42da2bb37342d80567bd7504885e22..189c63a2b6562c000a976d029ae6abb440f454ca 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl
index 4e0148cb6db4783ba218efd355ba136dcccbfe64..b445f7e5008bc9a0671698f7080112ec775d72b9 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/clkbuf_global/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/clkbuf_global/generated/sim"
 
 vmap altclkctrl_170 ./work/
   vcom  "$IP_DIR/../altclkctrl_170/sim/ip_arria10_e1sg_clkbuf_global_altclkctrl_170_7fwzyby.vhd" -work altclkctrl_170                                           
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/hdllib.cfg
index 53e52737dcf6841b8262f47a3e3dd5bb7a4867ca..150dab121407f6ea5247cfba2422b49a422808bc 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl
index 678571d01d97d42e5b225b91747b4564ba3fb628..036ea3f388b1c1abb75cef8ff17103763b546e78 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl
@@ -29,7 +29,7 @@
 vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generated/sim"
 
 vmap altera_asmi_parallel_170 ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/hdllib.cfg
index 03dcebf48d341b78a9bd7e33ca0ab6af8b2d44e1..0e8e55c1e66a7cf84fb1832f5ed9cd4566232e5d 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/hdllib.cfg
@@ -11,5 +11,5 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl
index 34a1a261f4f892fff467eb56e06ecc766c806562..242b0df1d1260db2fe00811b03e6a236ca4446ec 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl
@@ -28,7 +28,7 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
 
 vmap  altera_avalon_mm_bridge_170         ./work/                       
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/hdllib.cfg
index 13d14719a40b3580598b166e433e0ba0a5ccb8d1..1f0e8108fd2c3ac34bc3004d4cc4f1a5101237c4 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
 test_bench_files = 
     # The generated testbench is listed here to create a simulation configuration for it. However
     # the tb is commented because it is not useful, see generate_ip.sh.
-    #$RADIOHDL/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
+    #$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
 
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl
index 992f0730611b95df0961a162dea38f532640be1c..f2394512b8b0a605d9ff7dcfc7ec0588d4c8d582 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl
@@ -30,16 +30,16 @@
 #
 vmap  altera_avalon_onchip_memory2_170    ./work/
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
                       
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/hdllib.cfg
index 5ceeb58a7de1cf66c16b4c3c017d6dbe8aba983d..2edea37fa91875f04b9549e9bdebfc457efe2a71 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl
index 281337133e5a6ee269e5b845f4a309fab1495fd0..afd0617db004e8589b42737e88cd49628eb31d7c 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
                 
 vmap  altera_avalon_packets_to_master_170   ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/hdllib.cfg
index 5ab90e77c5b8dc86fdd70af7b6a3b053b935761d..0dc7501636e1a4dde423d7e9b1e7fe132b8681ae 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl
index 12ef7165fee7c08070e80bbd182879e3efcd5cc3..5eda20d2ab82020202bd010789bbbc691f24405e 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
 
 vmap  altera_avalon_sc_fifo_170             ./work/
   vlog      "$IP_DIR/../altera_avalon_sc_fifo_170/sim/altera_avalon_sc_fifo.v"                                                          -work altera_avalon_sc_fifo_170            
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/hdllib.cfg
index 9bc4b55fb344b3ea5d0b6a4fe622c45a3ed90023..f8ab200bc09097dba9bbd9fc92a2749814a9738d 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl
index ea418480bedb74b05966009647b9f05a094eb416..6c4839b6606f209834bd6af3ab4fbe01b2a5b7d4 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
 
 vmap  altera_avalon_st_bytes_to_packets_170 ./work/
                                                       
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/hdllib.cfg
index ed679b2fad65fce0ece4ba5e96a1e1adb85efcd0..0662c5a3d2d3992f6c1c2fce438e9375b3f4a64d 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl
index 201e991ee885f5b07bb620c71847055e73db5e56..c5e0f22569da6493c9d1d345bcc295250f7c3731 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
 vmap  altera_avalon_st_packets_to_bytes_170 ./work/
    
   vlog      "$IP_DIR/../altera_avalon_st_packets_to_bytes_170/sim/altera_avalon_st_packets_to_bytes.v"                                  -work altera_avalon_st_packets_to_bytes_170
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/hdllib.cfg
index d04ecd20c4854e543fa76c49451f96758e22fb2e..f8cf50573a24551facc73d506e8bb6501eac3bd7 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl
index 972892c08103be99e0d64d9e7e9a92c248e0b425..45d574b99d18c109b861ba25a1583d888c28f6b6 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl
@@ -29,42 +29,42 @@
 #vlib ./work/         ;# Assume library work already exist      
 #
 vmap  altera_emif_170                     ./work/
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
   vlog      "$IP_DIR/../altera_emif_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_170_fpxzpei.v"                                     -work altera_emif_170                    
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
   vlog      "$IP_DIR/../altera_emif_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_170_e7aaa3y.v"                                     -work altera_emif_170                    
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
   vlog      "$IP_DIR/../altera_emif_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_170_zmrgaza.v"                                     -work altera_emif_170                      
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
   vlog      "$IP_DIR/../altera_emif_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_170_xxodvzi.v"                                     -work altera_emif_170                    
                       
 vmap altera_emif_arch_nf_170 ./work/
 # ddr4_4g_1600
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti_top.sv"                -work altera_emif_arch_nf_170            
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti_io_aux.sv"             -work altera_emif_arch_nf_170            
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti.sv"                    -work altera_emif_arch_nf_170 
 
 # ddr4_4g_2000
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq_top.sv"                -work altera_emif_arch_nf_170            
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq_io_aux.sv"             -work altera_emif_arch_nf_170            
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq.sv"                    -work altera_emif_arch_nf_170 
   
 # ddr4_8g_1600
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei_top.sv"                -work altera_emif_arch_nf_170               
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei_io_aux.sv"             -work altera_emif_arch_nf_170                
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei.sv"                    -work altera_emif_arch_nf_170  
 
 # ddr4_8g_2400
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_170_as3yf3i_top.sv"                -work altera_emif_arch_nf_170            
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_170_as3yf3i_io_aux.sv"             -work altera_emif_arch_nf_170            
@@ -110,53 +110,53 @@ set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/g
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_170/sim/io_12_lane__nf5es_abphy.sv"                                                         -work altera_emif_arch_nf_170                                                                               
 
 vmap  altera_emif_cal_slave_nf_170        ./work/
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
   vlog      "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_cal_slave_nf_170_6qfmevy.v"           -work altera_emif_cal_slave_nf_170       
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
   vlog      "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_cal_slave_nf_170_6qfmevy.v"           -work altera_emif_cal_slave_nf_170       
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
   vlog      "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_cal_slave_nf_170_6qfmevy.v"           -work altera_emif_cal_slave_nf_170
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
   vlog      "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_cal_slave_nf_170_6qfmevy.v"           -work altera_emif_cal_slave_nf_170       
                       
 vmap  altera_reset_controller_170         ./work/
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
   vlog      "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_controller.v"                                               -work altera_reset_controller_170        
   vlog      "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_synchronizer.v"                                             -work altera_reset_controller_170 
 
 vmap  altera_mm_interconnect_170          ./work/
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_mm_interconnect_170_o2ys4ki.vhd"             -work altera_mm_interconnect_170         
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_mm_interconnect_170_o2ys4ki.vhd"             -work altera_mm_interconnect_170         
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_3gbam2q.vhd"             -work altera_mm_interconnect_170
   vcom         "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_o2ys4ki.vhd"             -work altera_mm_interconnect_170
   vcom         "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_lcqbbfq.vhd"             -work altera_mm_interconnect_170
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_170_o2ys4ki.vhd"             -work altera_mm_interconnect_170
 
 vmap  altera_avalon_onchip_memory2_170    ./work/
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
   
 
 vmap  altera_avalon_mm_bridge_170         ./work/                       
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
 
   vlog      "$IP_DIR/../altera_avalon_mm_bridge_170/sim/altera_avalon_mm_bridge.v"  -work altera_avalon_mm_bridge_170 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/hdllib.cfg
index 827dca10e520c206dccde21c7ef08f516a25adae..7e1017d4fddbf395af61b31df28c2e4428e91687 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl
index 0cabfc5b6e28454bcc08c96f9df1a6d53299df92..74fd1d14f33dd60c6a1671a53064130187abfd84 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl
@@ -31,28 +31,28 @@
 vmap altera_emif_arch_nf_170 ./work/
 
 # ddr4_4g_1600
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti_top.sv"                -work altera_emif_arch_nf_170            
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti_io_aux.sv"             -work altera_emif_arch_nf_170            
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti.sv"                    -work altera_emif_arch_nf_170 
 
 # ddr4_4g_2000
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq_top.sv"                -work altera_emif_arch_nf_170            
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq_io_aux.sv"             -work altera_emif_arch_nf_170            
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq.sv"                    -work altera_emif_arch_nf_170 
   
 # ddr4_8g_1600
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei_top.sv"                -work altera_emif_arch_nf_170               
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei_io_aux.sv"             -work altera_emif_arch_nf_170                
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei.sv"                    -work altera_emif_arch_nf_170  
 
 # ddr4_8g_2400
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_170_as3yf3i_top.sv"                -work altera_emif_arch_nf_170            
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_170_as3yf3i_io_aux.sv"             -work altera_emif_arch_nf_170            
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/hdllib.cfg
index 9ae9875f19a08a88b0f996abc952faf1d201efbd..8ee9e20c45828af05b9fa638324716cf1ee15d73 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
 test_bench_files = 
     # The generated testbench is listed here to create a simulation configuration for it. However
     # the tb is commented because it is not useful, see generate_ip.sh.
-    #$RADIOHDL/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
+    #$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
 
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl
index fd26318dbf0f0cbe99ca59ed6ecde2b4ec607d74..8a3a1fc7b47cc6a89a6c5de84054ec4dd35cd6ab 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl
@@ -31,16 +31,16 @@
 
 vmap  altera_emif_cal_slave_nf_170        ./work/
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
   vlog      "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_cal_slave_nf_170_6qfmevy.v"           -work altera_emif_cal_slave_nf_170       
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
   vlog      "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_cal_slave_nf_170_6qfmevy.v"           -work altera_emif_cal_slave_nf_170       
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
   vlog      "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_cal_slave_nf_170_6qfmevy.v"           -work altera_emif_cal_slave_nf_170
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
   vlog      "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_cal_slave_nf_170_6qfmevy.v"           -work altera_emif_cal_slave_nf_170       
                       
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/hdllib.cfg
index 880bfa7199d0b13dec9922f7649baf90c6322934..c56bf53d57b495d9993c7d25ef95deac432d03b2 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl
index a67e4e717b8b3eb3a82be3289550327418a9cf0d..c2ab5646d96ca7468cafe08c97280c53524991bf 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl
@@ -31,10 +31,10 @@
 vmap  altera_eth_tse_170                     ./work/
 
 # tse_sgmii_gx
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
 vcom         "$IP_DIR/../altera_eth_tse_170/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_170_bs6nd6i.vhd"            -work altera_eth_tse_170     
 
 # tse_sgmii_lvds
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
 vcom         "$IP_DIR/../altera_eth_tse_170/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_170_kv2t7sq.vhd"          -work altera_eth_tse_170                   
             
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/hdllib.cfg
index 90be1751ea05ce14cb77c7ae1e280d537f9b2228..a21ef74c59d0a5c854f86e48a0c557129baaf750 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/hdllib.cfg
@@ -21,7 +21,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl
index 632980b0facc6d4e6bf3bb3f7e85be02b27776e8..ee572db721fae267c5d6c3cc9914bbc03504ee39 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl
@@ -28,6 +28,6 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
 vmap  altera_eth_tse_avalon_arbiter_170      ./work/
   vlog      "$IP_DIR/../altera_eth_tse_avalon_arbiter_170/sim/mentor/altera_eth_tse_avalon_arbiter.v"                                                   -work altera_eth_tse_avalon_arbiter_170  
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/hdllib.cfg
index 8e921110df9b900a32dad541998eaee9de32ca63..71a9c4e0ccefa77ed0b2e5be5bbccf68222ccee4 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl
index 6f5d022c1b8892b25df8394bb0bc97f44d074765..4380a9977249bf0960fb273895e43a2917a49132 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl
@@ -28,7 +28,7 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
 
 vmap  altera_eth_tse_mac_170                 ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/hdllib.cfg
index 82ce945d2d4bf6543ec4008ee0f27fdcb275cee7..c8e2e0ffd18c89f4b602ba39e0c5e6d438af94d0 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/hdllib.cfg
@@ -11,6 +11,6 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl
index 4456ba8f179220c8e8ba19618dde95f3e652ec78..60a0afa582ca3440e0121bacc8e1dd87a7822c3f 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl
@@ -28,7 +28,7 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
 vmap  altera_eth_tse_nf_lvds_terminator_170 ./work/
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/hdllib.cfg
index 66e05d3284ff9e91335b0d986f5cdceb14fe28b1..ad8113152b568e100f561238fa51a0f3119c220e 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl
index 35458f1cde2873e3f8dd895067ac4ab09377ce39..26ab10609316bcbe095e654230c9d517e3282b05 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl
@@ -28,7 +28,7 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
 
 vmap  altera_eth_tse_nf_phyip_terminator_170 ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/hdllib.cfg
index a8c8cb1e80b2df5842c1f4ceadc11d455726ce57..4a68c345a399bbe25d3de95fca7c004ef5ba7ee0 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl
index 335a9a7e94aa98c60fc19ae1d7a38ef4507f7150..ade847195f05a2dfb518393402d040d4b3605f9d 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl
@@ -28,7 +28,7 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
     
 vmap  altera_eth_tse_pcs_pma_nf_lvds_170    ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/hdllib.cfg
index 41c2ef397078e0b89f457820590c3a5544ae8b4d..0bb69ecf007e80ef1de8b796ff5d88e0d27bf4bb 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl
index 8563952cf886168ff8f492dd1d3b999bed031180..47e92aa0fe4e7648331f94ef6419b149e077b157 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl
@@ -28,7 +28,7 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
 
               
 vmap  altera_eth_tse_pcs_pma_nf_phyip_170    ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/hdllib.cfg
index 8c6e48e6b8eb428735ac5d6276656c10b5478642..14e02053d5240acae9c43e5170e86f713fc0cd5c 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl
index bc26c17783a82bcd7140e7c0ee08032fc84f2c70..d4b2bfb7df44018e2bed09e98c3aeb5ce0f1de55 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl
@@ -30,12 +30,12 @@
 
 vmap  altera_iopll_170           ./work/
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/pll_clk25/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_clk25/generated/sim"
   vlog  "$IP_DIR/../altera_iopll_170/sim/ip_arria10_e1sg_pll_clk25_altera_iopll_170_7lq52ua.vo"  -work altera_iopll_170         
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/pll_clk125/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_clk125/generated/sim"
   vlog  "$IP_DIR/../altera_iopll_170/sim/ip_arria10_e1sg_pll_clk125_altera_iopll_170_3a4ewza.vo" -work altera_iopll_170          
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/pll_clk200/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_clk200/generated/sim"
   vlog  "$IP_DIR/../altera_iopll_170/sim/ip_arria10_e1sg_pll_clk200_altera_iopll_170_bqwoevq.vo" -work altera_iopll_170          
                                          
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/hdllib.cfg
index fbb4d7a81c4946a68cd62df8bfef02dbf3c636a4..d75309def40467ad136aec37d367b6a3c33688eb 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl
index 66f56205ddc64a363f3ceb2dc8ab5c476b980325..4da1aeca690c7c38d1393da3694d8b679ae2285b 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
 
 vmap  altera_ip_col_if_170                  ./work/
                                               
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/hdllib.cfg
index 50fbc5fe6eba88f6327a59d369a2dc60d7448207..540bef90d6fe2a9db186358879b1354089256691 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl
index 1d4cac7395d91bcbf1846b9d2b152c03539cd62a..657e2f6557942df70cd8e1e080bbd4eaeb86cfb5 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
 
 vmap  altera_jtag_dc_streaming_170          ./work/
   vlog      "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_jtag_interface.v"                                             -work altera_jtag_dc_streaming_170         
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/hdllib.cfg
index 97ab5a0c8e2d50b40e259343b040b38d90fd0c29..58633386cd5c011ca51c43a592fc2c92e01a7cbb 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl
index 7848c8ff289fa7b4638ae5df12a893d76e692b90..1add231a2d55b79b3cfe6ac0e5045e99600e26da 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl
@@ -27,7 +27,7 @@
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
 vmap altera_lvds_170                 ./work/
   vcom         "$IP_DIR/../altera_lvds_170/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_170_m5pqrlq.vhd"                -work altera_lvds_170  
   vcom         "$IP_DIR/../altera_lvds_170/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_170_o42lhkq.vhd"                -work altera_lvds_170  
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/hdllib.cfg
index 7c57a46fc7efc66f2417e6b79c75933ff5294cfd..5aafdf155e3fe629c525162641215ac1638449ad 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl
index 5fd24f5b7a45ecaec73925a327b4ad8055236e3d..fba2fedca1f63692aa568697a0ccb526d2a4aa2e 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl
@@ -27,7 +27,7 @@
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
 vmap  altera_lvds_core20_170                ./work/
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/hdllib.cfg
index fdc2c867769481393be830aa311fe6fb4a4656eb..a72e4c297c86cd067dce135fa623c5eb45c8e1ba 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl
index a270f3550830742924fc5ea2891681e128589cee..3cff03c2cc5f6d349714e32bed5abea43ce2087d 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl
@@ -28,7 +28,7 @@
 
 #vlib ./work/         ;# Assume library work already exist      
 #
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
 
 vmap  altera_merlin_master_translator_170 ./work/
         
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/hdllib.cfg
index d0ccefa672e8c8514c58c2912f3a3a35bd6bb8d7..1f2a23c00eaea07409b423479743715cd60d1ff1 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl
index 66fdebf4414e1c98aeec564391ce51f8f475abc1..e62f1475ff6472edb8470cccbac139b2ccb119ab 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist      
 #
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
  
 vmap  altera_merlin_slave_translator_170  ./work/
                                                       
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/hdllib.cfg
index c063d07c3f99d0cde926a2401b90c6b096f2960b..ef9b259c5ff1a3aa044ac8c6b3e8eeb37fa88283 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl
index 8b15c1f71d5561180608d7c63537712c86db3d2d..26070a82858aa734b80a7f765c4e2d3348f08830 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl
@@ -30,17 +30,17 @@
 #
 vmap  altera_mm_interconnect_170          ./work/
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_mm_interconnect_170_o2ys4ki.vhd"             -work altera_mm_interconnect_170         
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_mm_interconnect_170_o2ys4ki.vhd"             -work altera_mm_interconnect_170         
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_3gbam2q.vhd"             -work altera_mm_interconnect_170
   vcom         "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_o2ys4ki.vhd"             -work altera_mm_interconnect_170
   vcom         "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_lcqbbfq.vhd"             -work altera_mm_interconnect_170
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_170_o2ys4ki.vhd"             -work altera_mm_interconnect_170         
                                                       
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/hdllib.cfg
index aa6f8e7f04401b232740c9323f160cd1f577903d..f08778a0208c0c258c17e2375d8699df74d3c166 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl
index 1a89c9e523dfb7470d38a740e407fda2d7d6e6fb..f6c6f073cc083e1beec754d9302b8d500df7e493 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/flash/remote_update/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/flash/remote_update/generated/sim"
 
 vmap  altera_remote_update_170      ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/hdllib.cfg
index 6e71bd65da67ea8eda8b896c54c642b56814701b..fed8c35d6ca2b458e6af524df5870e7bad3a81d3 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/hdllib.cfg
@@ -11,5 +11,5 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl
index fbf003ec00b742824233a010c189d2467aada6c2..534817e5a023e9c13fc15bfb67bff13dd4738260 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/flash/remote_update/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/flash/remote_update/generated/sim"
 
 
 vmap  altera_remote_update_core_170 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/hdllib.cfg
index 15d9e9c9948ecbd0a27a7c89ecaa07de77d6d999..ef449921eb509296d6c7b5cda971164613d316fb 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/hdllib.cfg
@@ -1,5 +1,7 @@
 hdl_lib_name = ip_arria10_e1sg_altera_remote_update_core_170
 hdl_library_clause_name = altera_remote_update_core_170
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim =
 hdl_lib_technology = ip_arria10_e1sg
 
 synth_files =
@@ -7,4 +9,4 @@ synth_files =
 test_bench_files = 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl
index bdb77d6c74d8f51afb931ae9eb0725aad3292bce..872cb90083bd1c76e186de9946bc37a19b629a54 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist      
 #
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
  
 vmap  altera_reset_controller_170         ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/hdllib.cfg
index 092ef35e7d9fb56d3eb22d69529868d3661a78c9..2bf3f307467bf0b53b5663fe7a044f50a215b74b 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl
index 709cb2f5f789afbf624a9995dfa7e884855d381a..16bbd179c384805b61d28c0e98ab5a6f7b1c6384 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generated/sim"
 
 vmap  altera_common_sv_packages           ./work/
 vmap  altera_xcvr_atx_pll_a10_170         ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/hdllib.cfg
index 0f41fa58464ab5cfaca54dfafe2eebcbd6b8830c..db46806823bd89d278e67d87196878b91c1c3dbc 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl
index d96408232b82bfa3d78d91f7dc725e829d0f4838..b390847fb3b656c001c926aed71f5320d8fdf4ff 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generated/sim"
 
 vmap  altera_xcvr_fpll_a10_170             ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/hdllib.cfg
index 7796dcce2e883b4fd99df5ff0338e9353d3db184..fbcddbb6b9e60f55b5c5c9ec042ab2316c3e83de 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl
index 578bb1e0bfd2ff7198127cf6bc202bebc0be7f3d..6a82671583af10032005de2e8a5c0488ba9f3e88 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl
@@ -32,7 +32,7 @@ vmap  altera_xcvr_native_a10_170       ./work/
 vmap  altera_common_sv_packages        ./work/
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generated/sim"
 
 # common dependencies
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_a10_functions_h.sv"                                                               -work altera_common_sv_packages       
@@ -68,31 +68,31 @@ set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_otmjdta.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_170  
 
 # phy_10gbase_r_24
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generated/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_170_edf7tdy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170      
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_edf7tdy.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_170  
 
 # phy_10gbase_r_12
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generated/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_170_uyp7wca.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170      
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_uyp7wca.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_170  
 
 # phy_10gbase_r_4
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generated/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_170_5bntvuq.sv"  -L altera_common_sv_packages -work altera_xcvr_native_a10_170     
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_5bntvuq.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_170  
 
 # phy_10gbase_r_3
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generated/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_170_exiqljq.sv"  -L altera_common_sv_packages -work altera_xcvr_native_a10_170     
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_exiqljq.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_170  
 
 # phy_10gbase_r
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generated/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_170_s7t4kxy.sv"    -L altera_common_sv_packages -work altera_xcvr_native_a10_170   
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_s7t4kxy.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_170 
 
 # tse_sgmii_gx
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_xcvr_native_a10_170_q6y47ey.sv"     -L altera_common_sv_packages -work altera_xcvr_native_a10_170            
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_q6y47ey.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_170  
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/hdllib.cfg
index 2183a5d0ce693c01786a8bf73d0e8f3f9a349a88..96fde27cdff0dbd5fc1cca407adf30a44e89a767 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/hdllib.cfg
@@ -11,6 +11,6 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl
index 24d690a758f77cd828542919b8a832b12cbf4fea..a2ab22b40edb7bea98032134943f9ff635f0549e 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generated/sim"
 
 vmap  altera_xcvr_reset_control_170                  ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/hdllib.cfg
index 14d4ae7d74d3cbde4ab29daa66adf11f05991e5d..eedb9c51bd0e8f966791754164558e028dcf1426 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/hdllib.cfg
@@ -11,6 +11,6 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl
index 012fb6f793f1a56db443bb6d26d5b2632dbf1f19..5e29d06a31da0b7a33bee7ce82ef2899d8146812 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
 
 vmap  channel_adapter_170                   ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/hdllib.cfg
index 85458499014994e882dab3270e12021c99240511..eebe788ab1ab82f06d0bb80dc1c65c2f1ed59caa 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl
index 205892f0f95760f9c0374734ba756b0b193ba468..1f7ca180550b28f7278995ff7483f0da208f0b84 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
 
 vmap  timing_adapter_170                    ./work/
                   
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/hdllib.cfg
index 05cae0c6e50045da2ba1010c47b019377ba6e292..4633fb177d9ecea8e48d40cf06f04a3cb6aad243 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
index 941bd98e5ebbe7231b0b5abe83047ef57eb1e906..3ec2cd3bae0752cf489d438d600d0c3ceb7db2b9 100644
--- a/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/clkbuf_global/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/clkbuf_global/generated/sim"
 
   vcom  "$IP_DIR/ip_arria10_e1sg_clkbuf_global.vhd"                                             
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/clkbuf_global/generate_ip.sh
index 39a7312b5aea86d6d9d13ec5e36eb700ec66c700..878b355c4b57a937cf55c205a4600a2ebbc5c0a6 100755
--- a/libraries/technology/ip_arria10_e1sg/clkbuf_global/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
index 66fbcda43e68220539ea10e78d68be775a9bea1e..7504ddb609095a635a3e274e61666650c114d86b 100644
--- a/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/README.txt b/libraries/technology/ip_arria10_e1sg/complex_mult/README.txt
index 6884ec9c599bf7d01ffed812c8a3a2a9bbb09398..3e33649f60f2659c1bd624a9ee30584f601033b4 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/complex_mult
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/complex_mult
 
 1) Porting
 2) IP component
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
index d583f8dd2fed822c190aa0fa8d6e348608f86f24..30b5ed4fdf80e46ef33ae33f528e9721bfcb84b4 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/complex_mult/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/complex_mult/generated/sim"
  vmap altmult_complex_170 ./work/
 
   vlog "$IP_DIR/../altmult_complex_170/sim/ip_arria10_e1sg_complex_mult_altmult_complex_170_myrk3hi.v" -work altmult_complex_170
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/complex_mult/generate_ip.sh
index 96be7f292600bd729d715fc0547932a51a884082..c09f8f660fabe8930db6ffcea74be99cc0fb32d3 100755
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
index a13aea7eeafab73585d18639c3bec1e261bd06d8..02a6d4874a9af44692b4b4064fbf137d3b7edad5 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/README.txt b/libraries/technology/ip_arria10_e1sg/ddio/README.txt
index 6ba19729bb9e0c499398db1ef5661a55845e419f..1823e822ffac72fd6dfccb16917ab9972bed2a75 100755
--- a/libraries/technology/ip_arria10_e1sg/ddio/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/ddio/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/ddio
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ddio
 
 Contents:
 
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
index d0750f0b4aa99515372e83ba69b83ba2859cff20..dbab4802e06e7a85e77241dfb0dc361040979b68 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
@@ -34,7 +34,7 @@ set IPMODEL "SIM";
 if {$IPMODEL=="PHY"} { 
     # OUTDATED AND NOT USED!!
     # This file is based on Qsys-generated file msim_setup.tcl.
-    set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddio/generated/"
+    set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddio/generated/"
         
     #vlib ./work/         ;# Assume library work already exists
     vmap ip_arria10_ddio_in_1_altera_gpio_core_150  ./work/
@@ -60,7 +60,7 @@ if {$IPMODEL=="PHY"} {
 } else {
 
     # This file uses a behavioral model because the PHY model does not compile OK, see README.txt.
-    set SIM_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddio/sim/"
+    set SIM_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddio/sim/"
     
     vcom "$SIM_DIR/ip_arria10_e1sg_ddio_in_1.vhd"
     vcom "$SIM_DIR/ip_arria10_e1sg_ddio_out_1.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ddio/generate_ip.sh
index 38843a33037ea6f47ed7430e5ab1ce4d9a996502..389f44f5116766060cb0cb93ad685fa72bde71dc 100755
--- a/libraries/technology/ip_arria10_e1sg/ddio/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/ddio/generate_ip.sh
@@ -34,7 +34,7 @@
 #   
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
index 4e22b8d9620d1fe0ecf1b54bb05435d87e53a7b5..8fd1e669ff70035761e455a49515b99f12090a03 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
@@ -13,7 +13,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
index 0940d7bc607b19dff053f19b22cf024975255a0c..46dff72ef5d8321a872ef7c08bb2f2f9cbe7c8a9 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
 
                
   vcom         "$IP_DIR/ip_arria10_e1sg_ddr4_4g_1600.vhd"                                                                               
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
index 2665360e001a23d37a6a3acf179b0bd3078c10bc..357e27bb3de566c63deacfe4592d18626f291fdc 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generate_ip.sh
index 9d98e72bcecf2225560e012317310689f02c6eee..9e63a80dc1b25adab2fe4421e7810403b5eae868 100755
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
index 0d945c2c2e876e948b69625ea77bbed443b325ea..9fa46dcfabe4b7b411bb72de9ca52ed5ce26442f 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
index cda82b8f1ad46bd29bcc1cacb2dd8b835b9fdd24..9497e3c7cc7147645711e3e93c60b78aedee6453 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
 
               
   vcom         "$IP_DIR/ip_arria10_e1sg_ddr4_4g_2000.vhd"                                                                                       
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
index d1d4ac6eee0ec9a6192832f216b159d80ab91dd4..44a321affd24f73f3c64029e30bd6afd2b399b85 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generate_ip.sh
index 64364ce034a0cc001573064b4e3faf8751f931c8..bbbc8b7d3aba357cd67070648e8a20a71822bce9 100755
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
index 536c9de8e31e47aad336d425081160ad37f8c7f5..695d6e9a6bbab055030e239cdb86c0cdfd6cbb98 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
index 5b537b74468da8cd84b2d9ca0ee034130c89e41e..ef04250d0394ce6a84ea1163b80eef291e8d0bd2 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
                     
   vcom         "$IP_DIR/ip_arria10_e1sg_ddr4_8g_1600.vhd"                                                                              
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
index 7999771512bdcf2d6865c503a905d6e0c248bf60..d384a4b5ea1bd06de5397111cb534b94d8e7c208 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generate_ip.sh
index cf24b8c0fc07ed16ecd535e3207b97793ffa5e4b..92679228d07f5e9c5db6de3ee92f3ac367394f9b 100755
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
index cd9f99df195e6963ea62ad19a2c9688923c84a83..fb991b3967d5bee811dddb40fa9790de4d3a0027 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
index 9fc229d78e74f11fa0041ffe90f0771e0825e9f2..5798a026b414db3f79f7068f52ed8d56dd2bba27 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
 
   vcom         "$IP_DIR/ip_arria10_e1sg_ddr4_8g_2400.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
index 474979c64cc05310799c5c096ed8d4951dee229f..c8089fe8591a6915d44e7381375adb56704a9671 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generate_ip.sh
index b1212614046a9bc1491c10d7e1fa6c4c74394290..14eafe55890689b7f67158285dc8355731d25260 100755
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
index 24326c3dab2b376c55c1e09f465f4d9669dfdafb..ceea1ea066f44fa63e53beb23e4aa1ff422861c7 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/README.txt b/libraries/technology/ip_arria10_e1sg/fifo/README.txt
index 48f19d8f0da8b25abe9f0f1f63591777534c35c5..cfe2a2a2d88c7a058d3596d9b1297941b2b0e8a3 100755
--- a/libraries/technology/ip_arria10_e1sg/fifo/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/fifo/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/fifo
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/fifo
 
 Contents:
 
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/fifo/generate_ip.sh
index bf3d60117dc35b41f0437547bcf1ae7140023f02..0a36be76c247ce189f600382c2e4aa58bea87b46 100755
--- a/libraries/technology/ip_arria10_e1sg/fifo/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/fifo/generate_ip.sh
@@ -39,7 +39,7 @@
 #   
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
index 564d9fee8a607cdc6e9d7d924581722222118944..381c1944ae2303a406eb431687bc2f7ea6d94bf4 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
@@ -29,7 +29,7 @@
 vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generated/sim"
 
 
   vcom  "$IP_DIR/ip_arria10_e1sg_asmi_parallel.vhd"                                                                
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generate_ip.sh
index c5d32303594607539ab7115f55e9094052c50054..6bac379b60d17aa26e6c87e045b2e288468a3986 100755
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
index d320b46a36a6a1e7c8ab25b3f9e3c51cc875ceaa..05b50ddd820c1737d1237f11378db09c3b1bbde1 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
index 661d93389c766ee5dfc1e14db72b7d69242e09b5..71a2b64c03778c01e9f8bb3b15bec0e26f5874b8 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/flash/remote_update/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/flash/remote_update/generated/sim"
 
  
   vcom  "$IP_DIR/ip_arria10_e1sg_remote_update.vhd"                                                                 
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/flash/remote_update/generate_ip.sh
index f9d585f8bb83069e338337a5dd7892a869ea1b72..fdc94c04b3261ea07d23656add6452bcd1cdd103 100755
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
index 3573f2b97b5b844affa9e03c5d07bf21abf8c7b5..9db01d2cbd95e589a4edb096f087b3ffc4a94bed 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
index c322b04b888b1eb38649e28f391b87fa6bf487a4..6f767532c6ebc07ad9a9a3e7d61c006dbb22c588 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/generated/sim"
          
   vcom   "$IP_DIR/ip_arria10_e1sg_fractional_pll_clk125.vhd"                           
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/generate_ip.sh
index a64d398529413e191b164a5a64c1f2e0a13730f4..739ce3f27efc0f9fcd25939b433b385a61bf4e2c 100755
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
index 9634b02d1a0cc006df7ec755a94234400c9ee4b4..f4a814161ae8e110335d88ce71d6208e5fb0c53e 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
index 66b0acffe21c463dd95a007c638db6857c7a9a74..5c8674a583e8f07a28241f7d66216cb166e01df2 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/generated/sim"
 
        
   vcom         "$IP_DIR/ip_arria10_e1sg_fractional_pll_clk200.vhd"                            
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/generate_ip.sh
index 10802670a735484a08fb1aca9eb9bc54aed6a010..b5aa72958821b47ba664842561a72e3b3a410a9a 100755
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
index 44cd4208ee3cc5ed7cd49f5405af97c010331f65..1a6b0a376b32e2a898640aaba1ea4f37c93e08ee 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/generate-all-ip.sh b/libraries/technology/ip_arria10_e1sg/generate-all-ip.sh
index 5a4792151f7d612e57c1dfc4717b7962d38aa4be..c35c6f1060310afcc7e7171bd10195cc48abcdb7 100755
--- a/libraries/technology/ip_arria10_e1sg/generate-all-ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/generate-all-ip.sh
@@ -1,6 +1,6 @@
 #!/bin/bash 
 
-files=`find $RADIOHDL/libraries/technology/ip_arria10_e1sg -name 'generate_ip.sh' `
+files=`find $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg -name 'generate_ip.sh' `
 
 echo -e "About to generate the following IP blocks:\n$files\n"
 
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/README.txt b/libraries/technology/ip_arria10_e1sg/mac_10g/README.txt
index 39766e46ccf196734329497a8fd824781a9b3fc1..1809358e9cffbc914b28099a977ad0b8ff8cc4b6 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/mac_10g
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/mac_10g
 
 1) Porting
 2) IP component
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
index 182854c2ae2d693c4b29e9adb1ef5806fe724538..afd8e94094f136d9e28b77d62ef95bd1bd50b558 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/mac_10g/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/mac_10g/generated/sim"
 
      
   vcom     "$IP_DIR/ip_arria10_e1sg_mac_10g.vhd"                                                                                        
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/mac_10g/generate_ip.sh
index 510c550c2cde57fafd8285beecd7edfdd9c5c951..2cfec0ecc4d8508d801ba069ccb5b829639b30f6 100755
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2a" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
index df5dd2cd6f6cfef1086af9fddf78fd75a3d58126..8b45746380e7bc10ae6ad8dfb0f03d77d696826f 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
 test_bench_files = 
     # The generated testbench is listed here to create a simulation configuration for it. However
     # the tb is commented because it is not useful, see generate_ip.sh.
-    #$RADIOHDL/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
+    #$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
 
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
index b1f2e646f445271713fc9601d3741904a09bda58..d1275d8574a49a0d8d546f0b672315a4ce65cb1b 100644
--- a/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/mult_add4/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/mult_add4/generated/sim"
 
 vmap  ip_arria10_e1sg_mult_add4 ./work/
 vmap  altera_mult_add_170       ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/mult_add4/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/mult_add4/generate_ip.sh
index 7e679ec72fb2adcb72f24126a5787db94a765e6b..b52b5b14f7ce153c51e4d79b634da2d32ce24dea 100755
--- a/libraries/technology/ip_arria10_e1sg/mult_add4/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/mult_add4/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
index d1975b4cdbba9b2b89647cea762ad1b235d2c6b7..41b87622bf791973ba65e36ee30cfe3553688903 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generated/sim"
 
 
   vcom         "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r.vhd"                                                                                                  
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generate_ip.sh
index 7f651810baa949a80b1f767b82d0dab38eb6a9c7..310c756aee8f1077260d28b8c9c81b0481f723c1 100755
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
index 0512f9e534ca1909c86e7afd82d5b6a5e2fdf0ab..d35beb3b4e341f4087c33d13a039065d9b7c3653 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
index 5d77e22a0f4e23f3b7aa3c9df9556630d581bc5e..32a75009b879b0781360e5b508fae141461c6ff0 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generated/sim"
 
     
   vcom         "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_12.vhd"   
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generate_ip.sh
index 0ecdbd7fef0dbff418e3b608dcd9b4d52f40efa2..0102778d11366e4bfbd71d13d75eeab70694d386 100755
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
index d3cdd5c5e83b2715e5e31289fe1b6e129507e748..29adb1d9b8eefdeb8afea27c7368e7ca549909c4 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
index f0a762da1bdbb94e75b92c80cc006bc257d323b3..9cc7830fe8844557b589aeecb23e95ef7125f184 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generated/sim"
 
 
   vcom         "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_24.vhd"         
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generate_ip.sh
index 32c3254360f24ef9a15f1372ca50500e1be94abc..58b28fabec4df5c2560be749a258201053ea0123 100755
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
index 0bbce083bb2acf9492ebe18ebec6a263377ec1c2..4bd7fc021eea05eea60792374ce599e010085d56 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
index ee72e73fa03130818ca9a64558b89a7075ef3fa7..4a869f57e294a9b6176048af1b831e03e817c540 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generated/sim"
 
    
   vcom         "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_3.vhd"                                                                                               
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generate_ip.sh
index 3240ee8311c58bb31337e23b87fc67f251ebf133..1bb64ac723956180d9e4602cdf252553892956d4 100755
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
index 54dc0969061fe6b72b67098e54478071382d5290..decc5b54b1139aa66a0cf2eba1503caccd445515 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
index 99833e4807d27ef358590e43939038ef2db2421e..4f4b143abd07af4b14d7ddf5dd457be853d7ee04 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generated/sim"
 
    
   vcom         "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_4.vhd"                                                                                               
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generate_ip.sh
index 445f2fed57c45685fc5e2a62706da6e6f271a308..ee4b74eceb498217f48d2c270e7c5562aafa367b 100755
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
index 1e221ad11820cf41bf2c629d4ca5490c66e06f4d..89b33cab67aacfbdf8e111757c92a81e73d0c0bd 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
index 29557e8e1a9cfaae5a842530b6143dbb0da31e8d..f9487e1a4f415cefacc85f516d18a398a2d04f1e 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generated/sim"
 
     
   vcom      "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_48.vhd"                                                                    
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generate_ip.sh
index 552a7a512e3009ede312770acde9f9377922acc8..c0fc1047afd6bf1b1b19a135622dfd3c3e0a7825 100755
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
index 0ab9d6043a020ff35fedfd5d42d59c26e37eb5da..8876a23c016ff0027bd6c96ea119d3d75ebb353d 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
index b77afd9f1fb8d407ada7dc210a39de2dab2dc994..643d6d409661103826c47e907c4209d7157c97c6 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/pll_clk125/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_clk125/generated/sim"
    
   vcom     "$IP_DIR/ip_arria10_e1sg_pll_clk125.vhd"                                              
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/pll_clk125/generate_ip.sh
index 17e6673b38fc72cc8c74d22859e0d0d01adcdd88..a00ef44c622996885b9eeb43b2850f383a7fab13 100755
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
index 26aa9670ad8b20d9db384a45d292c3ef56387439..5d46c79cf04af9d5d04df963796743071750834e 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
index e6c1c486d5b2c7fd8f040dd07d07a16787fcab2c..281a4c3d46f377ddc12a9d0f1ccabb0c94fcbee6 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
@@ -29,5 +29,5 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/pll_clk200/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_clk200/generated/sim"
   vcom  "$IP_DIR/ip_arria10_e1sg_pll_clk200.vhd"                                           
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/pll_clk200/generate_ip.sh
index 33378d48f5938d5fdae540eb07aae6262bf7772c..cf60d4df54f999d0e1e0ad17bc20c97afd0d79fb 100755
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
index 3e4b94666b31a354eb140e3577c0b27de1d15440..f931e6073894f649df6d50aa49ec26a7a591f91b 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
index f7704430d605236f2d3a8b9c992b3ad25c1d4766..278ea6499a777256e438d3135cb842e2f2b969ea 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/pll_clk25/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_clk25/generated/sim"
 
      
   vcom  "$IP_DIR/ip_arria10_e1sg_pll_clk25.vhd"                                        
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/pll_clk25/generate_ip.sh
index ef4a1a818453dc0c080036ebb3fa20c7e51f4a47..525783f424d60b6f4bd8baeb046ac03612b9a5e5 100755
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
index a48c2fd1381eb6a2fc0e4f1245d4c74bebdd21d0..776f7257d61e053f5340b0990167fbf9a7e555e8 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
index 7a9a224c07e36dc51ce9066781fa53ef9c9ed50f..36568c9bf3567d9b7022bbb4382eb89145f089d1 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generated/sim"
 
        
   vcom         "$IP_DIR/ip_arria10_e1sg_pll_xgmii_mac_clocks.vhd"                              
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generate_ip.sh
index 77f31d835c09eb748bbf8d85c9d4b808bdd3cdfa..37e803de614ae1bfdf99137ad3bbee1db21f944a 100755
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
index 646acb5d17b27e0b509b52d8e41c2fb6075925ef..9bbc02a2ca36f93540b5e3b7fc02d44cb62e4535 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/ram/README.txt b/libraries/technology/ip_arria10_e1sg/ram/README.txt
index 334f704974a248b117cd90c5b6b1af9286c49322..a9fe41102a7d2cec63b7c2f3846b28447c1b4bc0 100755
--- a/libraries/technology/ip_arria10_e1sg/ram/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/ram/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/ram
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ram
 
 Contents:
 
diff --git a/libraries/technology/ip_arria10_e1sg/ram/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ram/generate_ip.sh
index 3349722ddf66df22d8b2b5b72bec6889fb9ad4f9..a1a766d44dbaf7e52a90f41edb926a99ed423840 100755
--- a/libraries/technology/ip_arria10_e1sg/ram/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/ram/generate_ip.sh
@@ -39,7 +39,7 @@
 #   
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
index 9718b9d6eb70f446e6ae622866ff750edaee38a5..c0cef1e9d8961e98a9ba678ad5b4941616464bda 100644
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/temp_sense/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/temp_sense/generated/sim"
 
 vmap  altera_temp_sense_170      ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/temp_sense/generate_ip.sh
index ab8fbc6a740fbfb1b4f48a70f96ec45a4b5d0006..be991c110a1a3a0163771a5a066f9fe4cb0c18d6 100755
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
index 7b8c823272ab874c573033a7dcd8b52c4c9efcc6..0d72950c53b8664e732e2c98cfc51d03b050a4fe 100644
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 #modelsim_compile_ip_files =
-#    $RADIOHDL/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
+#    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
index e98b88b1eb1e257119ab091ea1c60683e39cbf69..63f8171a4bf4727b6a3e1038b32adab99cf003d0 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generated/sim"
 
   vcom       "$IP_DIR/ip_arria10_e1sg_transceiver_pll_10g.vhd"                                                                                                    
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generate_ip.sh
index 12de447a123ef957c2f267135432bb1c783a31c9..c4af138a6c65124de1d44c21ae9504a8bd0014e6 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
index 4e68a1f0175b5760992605e3167afaa9ecad4ca7..08c2ac709b765d656dc5c22ac2216b3c076b9dc7 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
index d87085932993af738a40f7fcbd569d81cf807f4f..01c8d37521f992435ab8396cf90db3ee96a0f3b6 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generated/sim"
 
                
   vcom         "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_1.vhd"                    
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generate_ip.sh
index 17e84e3a490d62221312a8fcd6301aa6a4c23561..bdf2f728e8449b0d21584605d12dbef6e03b8b50 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
index 4e0fa44f85607026d423264a2cc352f5bd2795a0..66e3ff86ed3378ae4ff903e631db714a3aa8aa31 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
index be4e8146ae3bbb88e1d59dd68f5d8498c6f3d020..b4cc6457dcd4c57e6b57dbea613e3b513c8031d8 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/generated/sim"
 
   vcom         "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_12.vhd"                      
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/generate_ip.sh
index db50fda3d1c23b1fba99b29b706585e04f519493..9dc526c3bb016f14dcb303f4b6696292e9c144da 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
index 127271a2950691364cedef58e46e2375f3750d76..23934188a7e0054ef7766c5cd75e33537d33d493 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
index 9a3467b8c887d510208ceb874c303f08676a1a52..21b8cb5187edd66c106dc61f19d2d268d77707b9 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/generated/sim"
 
                 
   vcom         "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_24.vhd"                    
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/generate_ip.sh
index 761d94c86955a2bfa768b6d837eb61929e4c33eb..ab440cf7a0b3648362abd11490c50654fe6e7af4 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
index 810f75c8b0dd4c6d5c1048340dc11ad879767115..f71b8b1bd41fec38f2395b501671cbdc8c05936e 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
index af3b3937c3230c99cdf17890d5bd14b368d617fa..aed0f2bedc861a172f400a7b033fc16ee0c4c31c 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generated/sim"
                 
   vcom         "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_3.vhd"                     
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generate_ip.sh
index ed92ce368e17e8b8bf6acf9fefcfe24075b18816..db457e873cb8006eed2d2041e12c506a2053c706 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
index 591a426a5da0f73fcba5d84c4ab19ff56770922e..b12597b826319a079a8ee26e00b94101f14aec5f 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
index 18b928a9ee3640f472b69237d868b61587dc76b9..a4e0bc1b15fdf7df5c6278a223d9e2c5819f79c8 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/generated/sim"
                 
   vcom         "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_4.vhd"                     
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/generate_ip.sh
index ad1d84d8d18b04d91936446ff8dfbdf90c3448eb..cb635dde75cc1dcfefbf57ef9d0468b25c364e98 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
index 6415a1556fa2dc38f07f6a14e43b577c0b78c21a..49ae9060620a7154e8bfdb07c852894a82f07a2d 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
index 0673565d445491e152b0600278bee4be6c7eee8c..7ef9776084c464a25bafca2158d2c0e23e9e54ea 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/generated/sim"
 
                  
   vcom      "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_48.vhd"                     
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/generate_ip.sh
index 81f461f352dfdcb41c9d6b086edea7f1b2c374b7..9aac11c07a0f4e0f5737a7ff00070133a58c5e4b 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
index 5a8b7cda1b42008029c390ec92e9f985fb41611e..51f03a221a31aef8fe7d2aaa8e01326309efb83a 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/README.txt b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/README.txt
index 846e784f55181cb84a27903a7e897ac3d01fa383..fa105db173e0dc963f59b1e10b143cf5cc782167 100755
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/README.txt
@@ -1,8 +1,8 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_gx
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx
 
 The ip_arria10_tse_sgmii_gx IP was ported to Quartus 14.0a10 for Arria10 by creating it in Qsys using the same parameter settings as the ip_arria10_tse_sgmii_lvds, but with GX IO.
 
 The tb_ip_arria10_tse_sgmii_gx.vhd verifies the DUT and simulates OK.
 
-For more information see: $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
+For more information see: $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
 
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
index 4c2692eead40b8133c477c8a21672a61e23eabe6..fcc8f3f3cb628213365ad645c6cf00e17de43a55 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
 
   vcom         "$IP_DIR/ip_arria10_e1sg_tse_sgmii_gx.vhd"        
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generate_ip.sh
index 91152f6cd89e4dad4f848dd56816f60f2499bb8d..e949f73d028b9df820fbd5f549a5538d4c1bc84b 100755
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
index 03743cf8326128e14b520342029dde963389c256..abfacc5cb9919dff5d1600e74e7a7f91afc24bbc 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
     
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/README.txt b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/README.txt
index 0120d49c00e2d190883becf573ccc25eabdf798f..efe749e3a03ff7e95c29fd5bfc6bb62ae55040a2 100755
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
 
-See README.txt for $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds
+See README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds
   
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
index 5172f9ab3e5912a6f3b6d3ea90e8af4f170ba88e..28a6acf47c7a62f3574f8c9277d30ac644faa22e 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
         
   vcom         "$IP_DIR/ip_arria10_e1sg_tse_sgmii_lvds.vhd"                                                                 
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generate_ip.sh
index 759e0042528a23b777bec5d2baed1fc684275a83..27c0af99a90f57741a253723098cd21a66b36dcc 100755
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
index 437900089292241d55200b72c01457e197e2838c..9a67954387c5e62aa380fa9b364a1497ee71ed75 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
@@ -13,7 +13,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
index 74b7f80f1796e9331ced14130c8021a972ef279e..3f9a54b2ab4a121e72a38b609aaecd2304683b17 100644
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/voltage_sense/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/voltage_sense/generated/sim"
 
 vmap  ip_arria10_e1sg_voltage_sense          ./work/
 vmap  altera_voltage_sensor_170              ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/voltage_sense/generate_ip.sh
index df1e1b6ff727ca0cd5c9bc91047f547d0ff2fb9b..2aa4ddd7b16c29497d49708cc8d0a65c6513aabc 100755
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
index fb423817ca925ad3cbdd8a877212a81e77ac44ae..58a16e411907b12618b1216d8a6606e51277dd84 100644
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
 [modelsim_project_file]
 # There is no simulation model for the FPGA voltage sensor IP
 #modelsim_compile_ip_files =
-#    $RADIOHDL/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
+#    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
index 73468f76815d0138de0fd1d617d36806571ec5f2..53c76e2b5ea78f85a2131a8aae684dd5015cd30a 100644
--- a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/clkbuf_global/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/clkbuf_global/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/generate_ip.sh
index 49379c421c6a8d62a2f2c2318bfb623679b57aa7..758a7a1300e10c5d5802182883bfe60d1f1f4d6e 100755
--- a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg
index d2f19999520dc452bdeb821a512638e3eb022026..0c279c174911401301a0bfd1c4768e6b075f2234 100644
--- a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/complex_mult/README.txt b/libraries/technology/ip_arria10_e3sge3/complex_mult/README.txt
index 6884ec9c599bf7d01ffed812c8a3a2a9bbb09398..3e33649f60f2659c1bd624a9ee30584f601033b4 100644
--- a/libraries/technology/ip_arria10_e3sge3/complex_mult/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/complex_mult/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/complex_mult
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/complex_mult
 
 1) Porting
 2) IP component
diff --git a/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
index 3208d6b9909de9560c5de8b82454fbdbc05f7596..7692d23a29ff8badebfed871757a5b20b7d21ad5 100644
--- a/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/complex_mult/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/complex_mult/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/complex_mult/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/complex_mult/generate_ip.sh
index 17ce37998c7c54b2809d8ac6ee1b373931cb904e..c6270c47fdac3cc5b787f618fca58db3a40fea31 100755
--- a/libraries/technology/ip_arria10_e3sge3/complex_mult/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/complex_mult/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg
index 43be8eb9553a48ff1e001165b30948243e22ce02..66eec3257070738ba46d5abcdbbb995ad876357b 100644
--- a/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/README.txt b/libraries/technology/ip_arria10_e3sge3/ddio/README.txt
index 6ba19729bb9e0c499398db1ef5661a55845e419f..1823e822ffac72fd6dfccb16917ab9972bed2a75 100755
--- a/libraries/technology/ip_arria10_e3sge3/ddio/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/ddio
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ddio
 
 Contents:
 
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
index effc6fdee45f3be59d313cc0c8b881c0a0797397..4a9ef46272c8d914fcb19512e69b2798f61447a8 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
@@ -26,7 +26,7 @@ set IPMODEL "SIM";
 if {$IPMODEL=="PHY"} {
 
     # This file is based on Qsys-generated file msim_setup.tcl.
-    set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/ddio/generated/"
+    set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddio/generated/"
         
     #vlib ./work/         ;# Assume library work already exists
     vmap ip_arria10_e3sge3_ddio_in_1_altera_gpio_core_151  ./work/
@@ -52,7 +52,7 @@ if {$IPMODEL=="PHY"} {
 } else {
 
     # This file uses a behavioral model because the PHY model does not compile OK, see README.txt.
-    set SIM_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/ddio/sim/"
+    set SIM_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddio/sim/"
     
     vcom "$SIM_DIR/ip_arria10_e3sge3_ddio_in_1.vhd"
     vcom "$SIM_DIR/ip_arria10_e3sge3_ddio_out_1.vhd"
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/ddio/generate_ip.sh
index 03a3952849ec9bceb03b4d36233664baa97de349..6e82be25a625e2c3eeee8e2b1ea5f61ee607dede 100755
--- a/libraries/technology/ip_arria10_e3sge3/ddio/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/generate_ip.sh
@@ -34,7 +34,7 @@
 #   
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg
index 32435e25bc26e332970cfb915287ef36fddc7f74..ffdcf8e0d817bb8c49b35e432ab61e266bf30bbc 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg
@@ -13,7 +13,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
index d84123a805e4d3b9a8596208195edb79b5812530..6d0ae35297df83f743aa2bd2865b44e355b95eda 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
index 078caca747f8dc057c519746846d5f7152c0a877..8c69969d8b207d4fd80cea4b663f74e91b07b3b0 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/generated/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/generate_ip.sh
index 456bf4082da195cd7a09d656b9e8f6c651bbc02a..a7d8a8c99adc58ba1318c332853aab03fe612685 100755
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg
index a725f7255c9a6acbf885914f75a2b0655aba59f6..7de6d9cc7e0179aafb4ec67fcbb4b97726e6152b 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
index 6d60c70c53f3d445eb2be3cdfb8b2a18cdbc8910..c7213abdc72e8387a1c22c6dc882fc76d0a6bb4d 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl
index 970a198dfe3288987470d304993c80e161a10260..a7fa910541183ffb7bbb395e0ea13d8f1f779f4f 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/generated/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/generate_ip.sh
index d4e86d057468399a8d91369ccc8d4498346bf5fe..f9cc3a792fbb51621f449b0c3e12b64262d7d5ba 100755
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg
index ef60735a9138b800530d28a2dcf92453b3ec0f66..5b8927482ca8d909c73fcea6e3feb20b99f864e5 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
index d938e48e59a10662da8287be70ad2a8d9ce85da2..b9cad2a73e9ac340ab98957b37bc64677c03a90a 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
index bca2ea4f57154906b566b3edb75cbc8e1c85afd1..ced3c0a509e3d6e73ec30a150057b6d9ba8b0ddf 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/generated/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/generate_ip.sh
index f33d5f1a97e704644f96b17872dc30124c0ee2f0..e69749253fa1a5f055aae98f00b80a964c0ce123 100755
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg
index 2ecb131124ae1028bd64168ec0ce800b3c858323..a90e81ff44e7ce2967b99494e6f3a539d133aea2 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
index e739c5bafd4fecc5078f1a157ffc958eb99dc671..3cefb93eccdb88a5e36d64f5ceaf7d8077e94448 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl
index 9e393f40f0fc0d35aad689d48db913f58a08e331..80794294d5c0968caa85c768817df202f7d6e8e6 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/generated/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/generate_ip.sh
index c596a2ed7606f5dbff8feed481e9436d0cfd92cc..d94b5a367b400e816e8de91a86429d6c54dac10c 100755
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg
index 8c19e34ac81049413b10f681af37de392951610f..91a0f974724f1e569fab5418fe25729c6d389109 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/fifo/README.txt b/libraries/technology/ip_arria10_e3sge3/fifo/README.txt
index 48f19d8f0da8b25abe9f0f1f63591777534c35c5..cfe2a2a2d88c7a058d3596d9b1297941b2b0e8a3 100755
--- a/libraries/technology/ip_arria10_e3sge3/fifo/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/fifo/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/fifo
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/fifo
 
 Contents:
 
diff --git a/libraries/technology/ip_arria10_e3sge3/fifo/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/fifo/generate_ip.sh
index bc69bfb3cffcb9aea506ba3bdfc8f91f0db1324f..9ba8d5f30fe645c8598c0bc36f533a35e2ea3be6 100755
--- a/libraries/technology/ip_arria10_e3sge3/fifo/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/fifo/generate_ip.sh
@@ -39,7 +39,7 @@
 #   
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
index 986ce3beb7d9f356864f9aa88b3396f95c41c504..c48cca790f2bad26ffc6a28a3aee631c4f4c07e6 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/generated/sim"
 
 vmap ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151 ./work/
 
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/generate_ip.sh
index bbb1b3d8620f730b6aba79d74ade6e896885b88f..415afb38df6d860bf830f73ce1b05b132ce27b4b 100755
--- a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg
index 704be79dca133b41f8688315080bc76b94600247..0ceeddd60a3a5ce3fbe390ef542356e38eed62c3 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
index 896f4912a39c3e4f83643ff224f8f25abcb9e3fe..995703d1817b63abd3742837ce6a1ea94e6eb555 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/flash/remote_update/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/flash/remote_update/generated/sim"
 
 vmap ip_arria10_e3sge3_remote_update_altera_remote_update_core_151  ./work/
 vmap ip_arria10_e3sge3_remote_update_altera_remote_update_151       ./work/
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/generate_ip.sh
index afdc526af2247e0f3079560a2134884c703cff69..c7f75c95a3bff919eccfdcc2da5e3b9d76bb7557 100755
--- a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg
index 697564797b4002322a1faf433b42a5f14aa31b5f..4bf49a5928f6c6b1fc81466478081f83e2379ea1 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
index feed76c69359a1dec4a3d6e9d01d7c9a4c92c002..26d0ca325d333b3e8c6da2d10ecbba57bcd3cbd1 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/generate_ip.sh
index 41436995e9ccfd6212fc10291dcc54f051f71e5f..39c66a5756969c0143535dc030c2f063a8af14a5 100755
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg
index febed22b2c259ac19b713f3874b271ee8a6dd4f3..86e2ac2c1a13334fa0119bea0e6af2d16a4ee6ff 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
index c5c3f0f8f753eb50ae5478c823ce0abfc3fe62ff..0383174c3bf4520da2b5c97b6293331bd4d214f4 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/generate_ip.sh
index 9d8d321ab604254f5a8b62ef79b065e060b374b2..ae8e7c1453d7668cac79ac15ccffe5489ff589b6 100755
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg
index fd683a26a024e9bc05c6c5d1fdc8b92c431a725b..dc5a2ead34d552e0321031b8d4afb5a4fe72502d 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/generate-all-ip.sh b/libraries/technology/ip_arria10_e3sge3/generate-all-ip.sh
index efb1fd404f15399f5d8d17ddea5bc86beed1fd76..a4edc2b256eef815daf66d1f3d7ff4271f84bc52 100755
--- a/libraries/technology/ip_arria10_e3sge3/generate-all-ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/generate-all-ip.sh
@@ -1,6 +1,6 @@
 #!/bin/bash 
 
-files=`find $RADIOHDL/libraries/technology/ip_arria10_e3sge3 -name 'generate_ip.sh' `
+files=`find $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3 -name 'generate_ip.sh' `
 
 echo -e "About to generate the following IP blocks:\n$files\n"
 
diff --git a/libraries/technology/ip_arria10_e3sge3/mac_10g/README.txt b/libraries/technology/ip_arria10_e3sge3/mac_10g/README.txt
index 39766e46ccf196734329497a8fd824781a9b3fc1..1809358e9cffbc914b28099a977ad0b8ff8cc4b6 100644
--- a/libraries/technology/ip_arria10_e3sge3/mac_10g/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/mac_10g/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/mac_10g
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/mac_10g
 
 1) Porting
 2) IP component
diff --git a/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
index 91dc85f7e8fedcd5a10a28fc2ead422856dd843f..23647961fcd4e08dd731001fddd696fdaaae619a 100644
--- a/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
@@ -26,8 +26,8 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/mac_10g/generated/sim"
-set IP_TBDIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/mac_10g/generated_tb/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/mac_10g/generated/sim"
+set IP_TBDIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/mac_10g/generated_tb/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/mac_10g/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/mac_10g/generate_ip.sh
index c7844fb9c7d83e1caf830ba8a7926eaf1196c655..f044512e6f9553f32f5ee27b24f1167174e10065 100755
--- a/libraries/technology/ip_arria10_e3sge3/mac_10g/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/mac_10g/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2a" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
index 0363ce82a4481ee0d6a6bb496dc20ebd3d5e91e1..98c627b440a5e8bf0d4b0d247742c8855b411d95 100644
--- a/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
 test_bench_files = 
     # The generated testbench is listed here to create a simulation configuration for it. However
     # the tb is commented because it is not useful, see generate_ip.sh.
-    #$RADIOHDL/libraries/technology/ip_arria10_e3sge3/mac_10g/generated_tb/generated/sim/ip_arria10_e3sge3_mac_10g_tb.vhd
+    #$RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/mac_10g/generated_tb/generated/sim/ip_arria10_e3sge3_mac_10g_tb.vhd
 
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl
index 2cb6b47731f212340d7ffcea5c87b7d151c1284e..e3aa9bf13c5e3f1aa838ea2b857e87bb75ff0e78 100644
--- a/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/mult_add4/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/mult_add4/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/mult_add4/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/mult_add4/generate_ip.sh
index 49a8d3f6d7a0a7db7af913fd2d7cfc00585bc74c..f69815f399c6a40ffe776a1b5cf71321b5ec1ac3 100755
--- a/libraries/technology/ip_arria10_e3sge3/mult_add4/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/mult_add4/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
index cc299be02357c4ca2dab0381fd657c5103814a12..c58d590f77b1df91ba2e8a01b9327e92ed940db8 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/generate_ip.sh
index a018e42cb547efec6247282fea66c1713729f6a8..5c4ec99b8394e1efa2513bd45b5b96fb8511ccc1 100755
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg
index 849af13e09f18579eae4a33eb5086f4e9d28a148..ef62134daee68f36cf6a2daf9b07e8aa6e283feb 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
index 07133cd4a653e0189a107c5cabc4f65b4071bc11..7b2e6c3379e357802f2b87a4b41f3d392c612ca6 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/generate_ip.sh
index 8de924c9141282a2644717fa78de07f13db9d7cf..50c4340cbf7c8b0ed9e4dcd15dfd8978af127e2c 100755
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg
index fba55e697b907a8822fbf7cffe71d4723cebbe48..7f282e184137f6a810e2a24aefae92dbadced41a 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
index 2458a6a32962728d03a9469cdd2cb253b1ebbe07..86a711170a0b1e8e856faf5bbf8a29fd46cc5c67 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/generate_ip.sh
index 1c2ecad6dd80ab0b601d83c1d3cd92dab28f1a37..67d5db7845fa36389967eca0c29e28ad88207074 100755
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg
index b04864d239bafa6707b06f1f78ddec43241d1eff..c71586e6376d9ed53b0104636067c50b4ab010cd 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
index 12fd3803c8a6e31112409c12b31d8385cdb647cf..52f79da7b2e4a3e7e193f2e0df8d65589733279c 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/generate_ip.sh
index d8e452c2262f58e4f4d69ac09f18680741d469ba..8d5eea44ca7a85371782e55003e2bd507db43f7c 100755
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg
index efb4fdc211d4635c5e4f6e5dfa308b47d4e99276..fa9eb5787592eb9663bde46397998372eb0e3140 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
index 0c4828bfe85448710e1fc03437330ff8a2cc8fb1..82b3ff12a72276d40de0fb18f489bcc7380635a5 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/generate_ip.sh
index 8053bf8985097813fb02427a6d7d43dc5d4ee7fb..be0fa4e3dfcfd3c93ae428078a6bac99e841c377 100755
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg
index 6182b3cd25fe0582b834dad1a514cd46b9cb8b62..a9a4f25f2a6b46e437526ad61ca5a3e47aedf7cf 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
index e1a730824cf8c7fbca74bfce283c71b728e1fc1f..71564250c52e54e7521a28286110696303257d6a 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/pll_clk125/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/pll_clk125/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk125/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/pll_clk125/generate_ip.sh
index bd6d2631875a311a7f62b0ce0692875980e030d5..4719ca011f6517f8873835e9442570acc5deae86 100755
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk125/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk125/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg
index b87c3842cdb7540ebac76db78ccc61f7d82b03c2..4744956c3432b434afc01abbf188c49b25183791 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
index 10b86dcf0f9345df10da2a3bb4808961f0bdf84f..5418dc79a17342a077163765116282c049758566 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/pll_clk200/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/pll_clk200/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk200/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/pll_clk200/generate_ip.sh
index 28143365d7d6080c289d958b6ca5fca44e13129e..33be5e78daa39ff10b8271e0dc4b9d4522868a12 100755
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk200/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk200/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg
index 746b95e754a798341f3b9dfff9b4b07203952a97..bbf989101b933c210fd222a522ce201d19c4462a 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
index 7c21e1477b9237643e61283f08928b567d09fe19..07c26baa46c45c60a91f0175a612cd2d96defc68 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/pll_clk25/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/pll_clk25/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk25/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/pll_clk25/generate_ip.sh
index 5ba1c24f21ba0da3c648377c30f392d8b119ca75..1842975a9b1ac9d3cba5514d9a5700e55d1ab596 100755
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk25/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk25/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg
index d921f8ffc420e5162b586f88237f688baa7d80e1..faa801825150ed079cc169ab3b3db08499e694d9 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
index 3439eaac594d29a9d5c73e114cb9e0d1c849e050..4e80e996457cff9045c39bda82b3289463a7f2b4 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/generate_ip.sh
index f3999e92a4519d96dc46e776a85bb000c76edbee..bcd02e3ab6d73f76f3703c793484e00c88db8b2f 100755
--- a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg
index 163fd8ab186a0ac58977718a7d4ab3c11b9ebf2a..8ffd2a8b646883647ffd52b457e85edc3a8d0e26 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/README.txt b/libraries/technology/ip_arria10_e3sge3/ram/README.txt
index 334f704974a248b117cd90c5b6b1af9286c49322..a9fe41102a7d2cec63b7c2f3846b28447c1b4bc0 100755
--- a/libraries/technology/ip_arria10_e3sge3/ram/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/ram/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/ram
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ram
 
 Contents:
 
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/ram/generate_ip.sh
index eb179c877ce4aa9ca3d7a69f03f96c32be5f5d39..a823b95804bc7f9b47109513893b3276cb5f8993 100755
--- a/libraries/technology/ip_arria10_e3sge3/ram/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/ram/generate_ip.sh
@@ -39,7 +39,7 @@
 #   
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
index 7b28095bcc98a5c0ee71a5632869277bfa93a4a4..f863a700748005ed3d0c6bd1b2e35a50c6218ea6 100644
--- a/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/temp_sense/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/temp_sense/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/temp_sense/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/temp_sense/generate_ip.sh
index e80b08cebe78784b692e5080761225df949eb1b7..3bd136fa89eb3b48b286feb5eec158aa16616f19 100755
--- a/libraries/technology/ip_arria10_e3sge3/temp_sense/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/temp_sense/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg
index 0f2bea029fb8fbcc842f6f1d297459dd9995648a..eb2f3106631be81fef06ff3b6cbd18ae64eb6520 100644
--- a/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 #modelsim_compile_ip_files =
-#    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
+#    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
index b4e0ebc532f9354cf99a60b81a1ac432008423df..806454fac629ddce0a6a6e5ab1b83c5da33668f1 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/generate_ip.sh
index 5461170236c7cf97bd68ec950668bacdb9159111..7c0cf72bb60ab1f2d0ea45d4705c2e0db455dc95 100755
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg
index 24cb2c48dae12ac23d8b262b9ee6ded525114af5..351187d2433986c0d6a25fa443f6b481331dba9f 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
index 74ce7d36328249bc304dda6762668d08ad84911e..fd40ff872189f846f752dff7c7ea0bad54f3e731 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/generate_ip.sh
index be133092b06c103ebac45b486d7619fdc068a4a1..4aabb018df16412e00a2d00f36a02513608c2819 100755
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg
index 38e2dc944a833fb93a89d97d8df765991ba0730e..fd0ff98f514ec0bc741f9f368275b58596c4d54e 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
index 05054e25f56d15e5fac7c66f4d0d8f5faac554f2..dda89b41c6ab60ab2827dbe0662ecd4b728c5840 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/generate_ip.sh
index 2ee36221e7c7aaaa857a448f5de411d49b76722a..66527a06b5311243368bda193b6493a76adb37d0 100755
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg
index 491b15792b0284eb1e42a82634e76e797180e2a6..6d8544bec1c6d68b05e0315c3e8fda780d2882b8 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
index c6b6ace326bce5c38f8e2362498a9bf8e90fee6a..54f87c5f3fb95085a3c3793fa26e38645984998f 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/generate_ip.sh
index 87585ed5ebe85eeff6073d768c2f89d6bf0b3355..80b6a05bc184466acebd585af45907734b72a674 100755
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg
index 6eb1e1c0cab242ef642312c657d200c3a6e50656..3104cabeda2fe6ac2cfc27a53bab1460f07a0185 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
index 22fa35d5e50131d64ab4177aada181018d01f07c..8ad00f7882a4a925f24b4e62e67af3df85f5f6a7 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/generate_ip.sh
index 441da965c024314f16026d4524f8465549076ee3..bbebfcca430f26ecd0fc7e4f48d19ea28ed9531b 100755
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg
index 0d46dbf1cfdd24d57dcd56b9f1410cd63a4f0339..4c9fed66989dd30d67ed93545ce49129e2d06811 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
index c11c7f1b14b0d078ff3db10a233488f5b41dd3f0..e77af624de326e6b61ee397fdc319ae99028ca15 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/generate_ip.sh
index 6b0e35088a911424c9563647f976d42facc6fbdd..990f62ead1be870f4db7b756eb3c699e67def69b 100755
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg
index 2598b18af3ee9843c8bd3cbcf8d9cd54c67bdecd..86b474c736f4de53ca79b5e28598dcee241346a8 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/README.txt b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/README.txt
index 846e784f55181cb84a27903a7e897ac3d01fa383..fa105db173e0dc963f59b1e10b143cf5cc782167 100755
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/README.txt
@@ -1,8 +1,8 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_gx
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx
 
 The ip_arria10_tse_sgmii_gx IP was ported to Quartus 14.0a10 for Arria10 by creating it in Qsys using the same parameter settings as the ip_arria10_tse_sgmii_lvds, but with GX IO.
 
 The tb_ip_arria10_tse_sgmii_gx.vhd verifies the DUT and simulates OK.
 
-For more information see: $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
+For more information see: $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
 
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
index c1a22329757535c1900e1746c33573f56326b36e..38368d2110f7a50c08bf0838fc9f9342b8632d91 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
 # - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/generate_ip.sh
index bfb902fe770f96750024b316224b7cd139702af4..566ba013c1556efc63340287b2d634450f0b02b3 100755
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg
index 931957a3a1ab079a3cac8bf191c2405e1b859643..df60de6e51120144fddd74709380a81255bc7b10 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
     
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/README.txt b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/README.txt
index 0120d49c00e2d190883becf573ccc25eabdf798f..efe749e3a03ff7e95c29fd5bfc6bb62ae55040a2 100755
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
 
-See README.txt for $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds
+See README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds
   
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
index 2fa7b84ba76082abb1c9931564776e226a3436d0..41c63a1ae3f64dc03c936f740bba7141d8697c11 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
 # - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/generate_ip.sh
index 71ffbc46ed43b9191cc4a217d47688df698536e3..90ae85bfa7b1636ed3edf86596baf68480d7cb73 100755
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg
index 5961fb88818f498f2e9f30e4d117b16f7f8fd69e..8c175111ce2c16a43d76069b66236a22313b06c6 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
index acf293d5a9d23cf2c5e2ec6181fdb24d11262bb3..8b61b7eb886a3180747c704703db4924ce24cbba 100644
--- a/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/voltage_sense/generated/sim"
+set IP_DIR   "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/voltage_sense/generated/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/voltage_sense/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/voltage_sense/generate_ip.sh
index 584aa5894e5c5e7401ac56a792ac2411e30884c9..0f8e0f516ae99e8706266bc465c7d187117166c4 100755
--- a/libraries/technology/ip_arria10_e3sge3/voltage_sense/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/voltage_sense/generate_ip.sh
@@ -31,7 +31,7 @@
 #
 
 # Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
 
 #qsys-generate --help
 
diff --git a/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg
index 5c3a2a7bfe4b276f5f74182f7ef6f90a9617ef4b..b6529dfd36030ce4450c21ddd912fc14a2a7f76d 100644
--- a/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
 [modelsim_project_file]
 # There is no simulation model for the FPGA voltage sensor IP
 #modelsim_compile_ip_files =
-#    $RADIOHDL/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
+#    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
index 5a773b59154e28ce4d6f87b4d2788bb3972fa2e5..2690e54a37ceb50230ab713b05004c8517bf0b64 100644
--- a/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
@@ -23,7 +23,7 @@
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
 # Get the memory model fro the uphy_4g_* from the ip_stratixiv_ddr3_uphy_4g_800_master example design
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_example_design"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_example_design"
 
 # Assume library work already exists
 
diff --git a/libraries/technology/ip_stratixiv/ddr3_mem_model/generate_ip.sh b/libraries/technology/ip_stratixiv/ddr3_mem_model/generate_ip.sh
index 4ce79ca2619b70195495a26e0f09b7c2b87e1b29..2d1b37088bbba5ca89dd318bbda69325e9b8619d 100755
--- a/libraries/technology/ip_stratixiv/ddr3_mem_model/generate_ip.sh
+++ b/libraries/technology/ip_stratixiv/ddr3_mem_model/generate_ip.sh
@@ -37,7 +37,7 @@
 #
 
 # Tool settings for selected target "unb1" with stratixiv
-. ${RADIOHDL}/tools/quartus/set_quartus unb1
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb1
 
 # The ip_stratixiv_ddr3_uphy_4g_800_master.v IP must have been generated
 
diff --git a/libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg
index 54443d82bc8706cfabd8f161b798027f03eed36f..6e6d7706b892126442ef6e24b458aa3dc9049c46 100644
--- a/libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
index 0287e1c1f8a6268f67d2fb5d1edc10946ab4c8dc..ab5bd65220f15f21adbe98861bc7bfa9c9fc47a4 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
 
 # Assume library work already exists
 
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
index 140a87ea3a8911407ef9f48f8e6b16e6eae83e59..c14c1911ff87e21ff31dac52f3cd28f6e0351b9f 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generate_ip.sh b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generate_ip.sh
index 606a1e3bef94fd9f737b521a308dde83061061f0..8e4111eeae3cb5d8699376292db0444c381dac0e 100755
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generate_ip.sh
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generate_ip.sh
@@ -36,7 +36,7 @@
 #
 
 # Tool settings for selected target "unb1" with stratixiv
-. ${RADIOHDL}/tools/quartus/set_quartus unb1
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb1
 
 # Generate IP
 if ! [ -d "generated" ]; then
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg
index bd0c67d481a485039d38482e77af2999acff3191..1b5ee24b7e77456a62aad36f587c6d73d7ff5124 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg
@@ -11,8 +11,8 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
index a6c92d8db25bfd674784e4839cc8da0ee4a48485..1ad73c93b568eac6e25f860eca978619c0ed895b 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
 
 # Assume library work already exists
 
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
index 9fba13ceb40d4220f9fcd187bd301436298d76fa..7e5924ab3850a3721a4c8b5da9a548486d456007 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generate_ip.sh b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generate_ip.sh
index 9b5b31184b9d1dbde6d99087726053ac142c502f..891821bdd4aedf60a7f13a55caf44be84fd832f0 100755
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generate_ip.sh
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generate_ip.sh
@@ -36,7 +36,7 @@
 #
 
 # Tool settings for selected target "unb1" with stratixiv
-. ${RADIOHDL}/tools/quartus/set_quartus unb1
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb1
 
 # Generate IP
 if ! [ -d "generated" ]; then
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg
index 1b11fbe2fac1ba9fb6f176c1c70b0e1b4bba16e9..9644bb62bc05603811c733df9efbc37c864a7172 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg
@@ -11,8 +11,8 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
index 72572588f984f38b5b8a061f55ec790de53c1ba7..3cd4b206184270dfce95c54502b9766978f40d38 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
 
 # Assume library work already exists
 
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl
index c759a138e72c032a758aeb614e5f5e1a9577db38..6a6e8602957e96fb85f3b0f7cdcc3493b4bdda1e 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generate_ip.sh b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generate_ip.sh
index fb4f6af3958901a5647e4c4091f5b0d84153d011..c6c755d97785b7ba6c830a31e80c99ef61e5ec97 100755
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generate_ip.sh
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generate_ip.sh
@@ -36,7 +36,7 @@
 #
 
 # Tool settings for selected target "unb1" with stratixiv
-. ${RADIOHDL}/tools/quartus/set_quartus unb1
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb1
 
 # Generate IP
 if ! [ -d "generated" ]; then
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg
index 4d64d1ae14dc8c0c7025a745e7d9284fc46bccf2..f56145e6a6b4752dc528da4f03e740469a7d1bb3 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
index 9f01c99f531428445f1a0f04ac9331d41f862296..1d878a2a3c4154e12c4a98d5aa6a54887e084f95 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
 
 # Assume library work already exists
 
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
index 18e0b9869197784abccd1007909008d4be65134a..e0786cddebaef392d34fd6518e393c89acd548ba 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generate_ip.sh b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generate_ip.sh
index 0a4ca4b56ec887743216a3c38f312cee48ea3cc1..0ce4fa270e38489da728e8996a6ed7bd74d77af4 100755
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generate_ip.sh
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generate_ip.sh
@@ -36,7 +36,7 @@
 #
 
 # Tool settings for selected target "unb1" with stratixiv
-. ${RADIOHDL}/tools/quartus/set_quartus unb1
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb1
 
 # Generate IP
 if ! [ -d "generated" ]; then
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg
index 5b71690a3af4b72c6ed67cb395d65c66cca3f8cc..1f4f9200a4b878e8da4546ea4235dc48168b8024 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg
@@ -11,8 +11,8 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
index 6314a870e673621582b13ac807a65d31cd089163..962b26b7f9befa28591fcbfe5f315a9541d066d9 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
 
 # Assume library work already exists
 
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
index a65e8718ff1088e954f9f45ce6c962b2f4dae7fd..00f508ab3377462b115449814a18ad6bcab197c1 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generate_ip.sh b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generate_ip.sh
index d33ae63c3d7744c252049608d8d8dd40ef9089ca..b651c73760c0518a48411e9f8c1ed09ad87eacfb 100755
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generate_ip.sh
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generate_ip.sh
@@ -36,7 +36,7 @@
 #
 
 # Tool settings for selected target "unb1" with stratixiv
-. ${RADIOHDL}/tools/quartus/set_quartus unb1
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb1
 
 # Generate IP
 if ! [ -d "generated" ]; then
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg
index 09191b848f0cce35af586d655fcc8efd3ac75afe..bf801765f002cecc1000f0270982be57e991d06d 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg
@@ -11,8 +11,8 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/flash/hdllib.cfg b/libraries/technology/ip_stratixiv/flash/hdllib.cfg
index 47a0434734f95cdaf3bb9d688372171411c9b980..31d0dceb881b16597685cfac93c06272e8fe172e 100644
--- a/libraries/technology/ip_stratixiv/flash/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/flash/hdllib.cfg
@@ -13,7 +13,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_copy_files = 
-    $RADIOHDL/libraries/external/numonyx_m25p128/NU_M25P128_V10/sim/memory_file .
+    $RADIOHDL_WORK/libraries/external/numonyx_m25p128/NU_M25P128_V10/sim/memory_file .
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/generate-all-ip.sh b/libraries/technology/ip_stratixiv/generate-all-ip.sh
index ee0c0da47a6ba6099cf3568958bcc2576d4aa938..6377b91415bf8f4028ad3ecc6d74ac4886f9155a 100755
--- a/libraries/technology/ip_stratixiv/generate-all-ip.sh
+++ b/libraries/technology/ip_stratixiv/generate-all-ip.sh
@@ -1,6 +1,6 @@
 #!/bin/bash 
 
-files=`find $RADIOHDL/libraries/technology/ip_stratixiv -name 'generate_ip.sh' | sort -r `
+files=`find $RADIOHDL_WORK/libraries/technology/ip_stratixiv -name 'generate_ip.sh' | sort -r `
 # sort file list backward to generate ddr3_mem_model before ddr3_uphy_4g_800_* (required)
 
 echo -e "About to generate the following IP blocks:\n$files\n"
diff --git a/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl b/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
index 39345203c290326aba0e76c082eccd9a964372f7..33c1e12bf70ebeff95cdf9ea1d1b4816a377789c 100644
--- a/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
@@ -24,7 +24,7 @@
 # file msim_setup.tcl.
 # tr_xaui is the first module I did this for.
 
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim"
 
 #vlib ./work/         ;# Assume library work already exists
 #vmap work ./work/
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generate_ip.sh b/libraries/technology/ip_stratixiv/mac_10g/generate_ip.sh
index 50b6563809d753c9f41a8d6e94ca773fbc083162..4f7c890f8c52d1995ba54a40eee5f5eef23cccb0 100755
--- a/libraries/technology/ip_stratixiv/mac_10g/generate_ip.sh
+++ b/libraries/technology/ip_stratixiv/mac_10g/generate_ip.sh
@@ -41,7 +41,7 @@
 run_script=0
 if [ $run_script -gt 0 ]; then
     # Tool settings for selected target "unb1" with stratixiv
-    . ${RADIOHDL}/tools/quartus/set_quartus unb1
+    . ${RADIOHDL_GEAR}/quartus/set_quartus unb1
 
     if ! [ -d "generated" ]; then
         mkdir generated
diff --git a/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg b/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg
index c548304587aff440c8bbcc978e1f8ec27483e23c..0863274168b1f8edc4081bca40c4e18ac727d83c 100644
--- a/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg
@@ -13,7 +13,7 @@ test_bench_files =
 modelsim_copy_files =
     
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
index 2da2fedde24cb011c55d1e739c71d1001169b752..ed22b0d05263f7d885dbbfca94f1c97c5935f6bb 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
@@ -27,7 +27,7 @@
 # correct compile order).
 # EK: The model files in phy_xaui_0_sim/ are suitable for all hard xaui IP variants.
 
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim"
 
 #vlib ./work/       ;# EK: Assume library work already exists
 
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
index 42bd765382d23d53b49cc37e687053834ea95b73..7eae3900cf0b6ecfebcb69f1b03f06c2c34d892c 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
+++ b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
@@ -27,7 +27,7 @@
 # correct compile order). Bonus of this is also that there will be no errors
 # when making all_mod without having run the XAUI megawizard first.
 
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim"
 
 #vlib ./work/       ;# EK: Assume library work already exists
 
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generate_ip.sh b/libraries/technology/ip_stratixiv/phy_xaui/generate_ip.sh
index c6edadc7bcb0bdbb22141a3aede02ede414b165c..30ef911296dfc253fc35cc197d272ece80eb0c7a 100755
--- a/libraries/technology/ip_stratixiv/phy_xaui/generate_ip.sh
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generate_ip.sh
@@ -39,7 +39,7 @@
 #
 
 # Tool settings for selected target "unb1" with stratixiv
-. ${RADIOHDL}/tools/quartus/set_quartus unb1
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb1
 
 if ! [ -d "generated" ]; then
     mkdir generated
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg b/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
index 06cb12d45ed0de2a85911fe269d9b23379858345..260a93b452bef74ecbdba6591c49e8fb53500bcc 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
@@ -21,8 +21,8 @@ modelsim_copy_files =
     wave_tb_ip_stratixiv_phy_xaui_ppm.do .
     
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
-    $RADIOHDL/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
index 089a409ec2fe0c8ee5b8c3c0eb0a13ac70c17450..4f9aec44175fc9ad7bda11978a1b714ae20501d3 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
@@ -52,7 +52,7 @@ PACKAGE tech_mac_10g_component_pkg IS
   -- ip_stratixiv
   ------------------------------------------------------------------------------
   
-  -- Copied from entity $RADIOHDL/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g.vhd
+  -- Copied from entity $RADIOHDL_WORK/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g.vhd
   COMPONENT ip_stratixiv_mac_10g IS
   PORT (
     csr_clk_clk                     : in  std_logic                     := '0';             --                    csr_clk.clk
diff --git a/libraries/technology/tse/tech_tse_component_pkg.vhd b/libraries/technology/tse/tech_tse_component_pkg.vhd
index 9a92d12862dbec4d998bfb2434a87bc71efb30c2..6671ba6f7ee79bd419eb6221408a84224df5fe18 100644
--- a/libraries/technology/tse/tech_tse_component_pkg.vhd
+++ b/libraries/technology/tse/tech_tse_component_pkg.vhd
@@ -31,7 +31,7 @@ PACKAGE tech_tse_component_pkg IS
   -- ip_stratixiv
   ------------------------------------------------------------------------------
   
-  -- Copied from $RADIOHDL/libraries/technology/ip_stratixiv/tse_sgmii_lvds/ip_stratixiv_tse_sgmii_lvds.vhd
+  -- Copied from $RADIOHDL_WORK/libraries/technology/ip_stratixiv/tse_sgmii_lvds/ip_stratixiv_tse_sgmii_lvds.vhd
   COMPONENT ip_stratixiv_tse_sgmii_lvds IS 
   PORT ( 
      address  : IN  STD_LOGIC_VECTOR (7 DOWNTO 0);
@@ -78,7 +78,7 @@ PACKAGE tech_tse_component_pkg IS
   ); 
   END COMPONENT;
 
-  -- Copied from $RADIOHDL/libraries/technology/ip_stratixiv/tse_sgmii_gx/ip_stratixiv_tse_sgmii_gx.vhd
+  -- Copied from $RADIOHDL_WORK/libraries/technology/ip_stratixiv/tse_sgmii_gx/ip_stratixiv_tse_sgmii_gx.vhd
   COMPONENT ip_stratixiv_tse_sgmii_gx IS 
   PORT ( 
     address  : IN  STD_LOGIC_VECTOR (7 DOWNTO 0);
@@ -147,7 +147,7 @@ PACKAGE tech_tse_component_pkg IS
   -- ip_arria10
   ------------------------------------------------------------------------------
   
-  -- Copied from $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds/generated/sim/ip_arria10_tse_sgmii_lvds.vhd
+  -- Copied from $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/generated/sim/ip_arria10_tse_sgmii_lvds.vhd
   COMPONENT ip_arria10_tse_sgmii_lvds IS
   PORT (
     clk            : in  std_logic                     := '0';             -- control_port_clock_connection.clk
@@ -198,7 +198,7 @@ PACKAGE tech_tse_component_pkg IS
   END COMPONENT;
 
 
-  -- Copied from $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_gx/generated/sim/ip_arria10_tse_sgmii_gx.vhd
+  -- Copied from $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx/generated/sim/ip_arria10_tse_sgmii_gx.vhd
   COMPONENT ip_arria10_tse_sgmii_gx IS
   PORT (
     clk                : in  std_logic                     := '0';             -- control_port_clock_connection.clk
@@ -265,7 +265,7 @@ PACKAGE tech_tse_component_pkg IS
   -- ip_arria10_e3sge3
   ------------------------------------------------------------------------------
 
-  -- Copied from $RADIOHDL/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/generated/sim/ip_arria10_e3sge3_tse_sgmii_lvds.vhd
+  -- Copied from $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/generated/sim/ip_arria10_e3sge3_tse_sgmii_lvds.vhd
   COMPONENT ip_arria10_e3sge3_tse_sgmii_lvds IS
   PORT (
     reg_data_out   : out std_logic_vector(31 downto 0);                    --                  control_port.readdata
@@ -316,7 +316,7 @@ PACKAGE tech_tse_component_pkg IS
   END COMPONENT;
 
 
-  -- Copied from $RADIOHDL/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/generated/sim/ip_arria10_e3sge3_tse_sgmii_gx.vhd
+  -- Copied from $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/generated/sim/ip_arria10_e3sge3_tse_sgmii_gx.vhd
   COMPONENT ip_arria10_e3sge3_tse_sgmii_gx IS
   PORT (
     reg_data_out       : out std_logic_vector(31 downto 0);                    --                  control_port.readdata
@@ -383,7 +383,7 @@ PACKAGE tech_tse_component_pkg IS
   -- ip_arria10_e1sg
   ------------------------------------------------------------------------------
 
-  -- Copied from $RADIOHDL/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim/ip_arria10_e1sg_tse_sgmii_lvds.vhd
+  -- Copied from $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim/ip_arria10_e1sg_tse_sgmii_lvds.vhd
   COMPONENT ip_arria10_e1sg_tse_sgmii_lvds IS
   PORT (
     reg_data_out   : out std_logic_vector(31 downto 0);                    --                  control_port.readdata
@@ -434,7 +434,7 @@ PACKAGE tech_tse_component_pkg IS
   END COMPONENT;
 
 
-  -- Copied from $RADIOHDL/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim/ip_arria10_e1sg_tse_sgmii_gx.vhd
+  -- Copied from $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim/ip_arria10_e1sg_tse_sgmii_gx.vhd
   COMPONENT ip_arria10_e1sg_tse_sgmii_gx IS
   PORT (
     reg_data_out       : out std_logic_vector(31 downto 0);                    --                  control_port.readdata