From b0c776a4df120db853f8236c19a4a934d40232f0 Mon Sep 17 00:00:00 2001
From: donker <donker@astron.nl>
Date: Thu, 22 Aug 2019 08:18:40 +0200
Subject: [PATCH] backup last changes, build for unb2b not working
---
.gitignore | 4 +
.../designs/unb1_bn_capture/hdllib.cfg | 13 +-
.../quartus/unb1_bn_capture_pins.tcl | 10 +-
.../designs/unb1_bn_terminal_bg/hdllib.cfg | 9 +-
.../quartus/unb1_bn_terminal_bg_pins.tcl | 12 +-
boards/uniboard1/designs/unb1_ddr3/doc/README | 4 +-
boards/uniboard1/designs/unb1_ddr3/hdllib.cfg | 6 +-
.../unb1_ddr3/quartus/unb1_ddr3_pins.tcl | 4 +-
.../designs/unb1_ddr3_reorder/doc/README | 4 +-
.../quartus/unb1_ddr3_reorder_pins.tcl | 2 +-
.../unb1_ddr3_reorder_dual_rank/hdllib.cfg | 8 +-
.../unb1_ddr3_reorder_single_rank/hdllib.cfg | 8 +-
.../designs/unb1_ddr3_transpose/doc/README | 4 +-
.../designs/unb1_ddr3_transpose/hdllib.cfg | 6 +-
.../quartus/unb1_ddr3_transpose_pins.tcl | 2 +-
.../designs/unb1_fn_terminal_db/hdllib.cfg | 3 +-
.../uniboard1/designs/unb1_heater/doc/README | 4 +-
.../uniboard1/designs/unb1_heater/hdllib.cfg | 4 +-
.../unb1_heater/quartus/unb1_heater_pins.tcl | 8 +-
.../uniboard1/designs/unb1_minimal/doc/README | 10 +-
.../quartus/unb1_minimal_pins.tcl | 8 +-
.../unb1_minimal_mm_arbiter/hdllib.cfg | 4 +-
.../revisions/unb1_minimal_qsys/hdllib.cfg | 4 +-
.../unb1_minimal_qsys_wo_pll/hdllib.cfg | 4 +-
.../revisions/unb1_minimal_sopc/hdllib.cfg | 4 +-
.../unb1_terminal_bg_mesh_db/hdllib.cfg | 5 +-
boards/uniboard1/designs/unb1_test/doc/README | 14 +-
.../unb1_test/quartus/unb1_test_pins.tcl | 4 +-
.../revisions/unb1_test_10GbE/hdllib.cfg | 4 +-
.../unb1_test_10GbE_tx_only/hdllib.cfg | 4 +-
.../revisions/unb1_test_1GbE/hdllib.cfg | 4 +-
.../quartus/unb1_test_1GbE_pins.tcl | 4 +-
.../revisions/unb1_test_all/hdllib.cfg | 10 +-
.../revisions/unb1_test_ddr/hdllib.cfg | 10 +-
.../quartus/unb1_test_ddr_pins.tcl | 4 +-
.../unb1_test_ddr_16g_MB_I/hdllib.cfg | 8 +-
.../quartus/unb1_test_ddr_16g_MB_I_pins.tcl | 2 +-
.../unb1_test_ddr_16g_MB_II/hdllib.cfg | 8 +-
.../quartus/unb1_test_ddr_pins_16g_MB_II.tcl | 2 +-
.../unb1_test_ddr_16g_MB_I_II/hdllib.cfg | 8 +-
.../unb1_test_ddr_16g_MB_I_II_pins.tcl | 4 +-
.../revisions/unb1_test_ddr_MB_I/hdllib.cfg | 8 +-
.../revisions/unb1_test_ddr_MB_II/hdllib.cfg | 8 +-
.../unb1_test_ddr_MB_I_II/hdllib.cfg | 8 +-
.../quartus/unb1_test_ddr_pins.tcl | 4 +-
.../designs/unb1_tr_10GbE/hdllib.cfg | 4 +-
.../uniboard1/libraries/unb1_board/hdllib.cfg | 4 +-
.../quartus/pinning/BACK_NODE_allpins.tcl | 4 +-
.../quartus/pinning/BACK_NODE_pins.tcl | 6 +-
.../quartus/pinning/COMMON_NODE_pins.tcl | 16 +-
.../quartus/pinning/FRONT_NODE_allpins.tcl | 4 +-
.../quartus/pinning/FRONT_NODE_pins.tcl | 6 +-
.../quartus/pinning/pins_tr_back_pcs.tcl | 4 +-
.../quartus/pinning/pins_tr_front_pcs.tcl | 8 +-
.../quartus/pinning/pins_tr_front_pcs_clk.tcl | 2 +-
.../quartus/pinning/pins_tr_mesh_pcs.tcl | 4 +-
.../unb1_board/quartus/unb1_board.qsf | 6 +-
.../unb1_board/quartus/unb1_board_head.qsf | 8 +-
.../unb1_board/quartus/unb1_board_tail.qsf | 4 +-
boards/uniboard2/designs/unb2_led/hdllib.cfg | 4 +-
.../unb2_led/quartus/unb2_minimal_pins.tcl | 2 +-
.../uniboard2/designs/unb2_minimal/doc/README | 10 +-
.../uniboard2/designs/unb2_minimal/hdllib.cfg | 4 +-
.../quartus/unb2_minimal_pins.tcl | 2 +-
boards/uniboard2/designs/unb2_test/doc/README | 10 +-
.../unb2_test/quartus/unb2_test_pins.tcl | 6 +-
.../revisions/unb2_test_10GbE/hdllib.cfg | 4 +-
.../quartus/unb2_test_10GbE_pins.tcl | 4 +-
.../revisions/unb2_test_1GbE/hdllib.cfg | 4 +-
.../quartus/unb2_test_1GbE_pins.tcl | 2 +-
.../revisions/unb2_test_all/hdllib.cfg | 4 +-
.../quartus/unb2_test_all_pins.tcl | 6 +-
.../revisions/unb2_test_ddr_MB_I/hdllib.cfg | 6 +-
.../quartus/unb2_test_ddr_MB_I_pins.tcl | 4 +-
.../revisions/unb2_test_ddr_MB_II/hdllib.cfg | 6 +-
.../quartus/unb2_test_ddr_MB_II_pins.tcl | 4 +-
.../unb2_test_ddr_MB_I_II/hdllib.cfg | 6 +-
.../quartus/unb2_test_ddr_MB_I_II_pins.tcl | 4 +-
.../unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd | 2 +-
.../unb2_board/quartus/unb2_board.qsf | 6 +-
.../ddr4/doc/README_ddr4.txt | 2 +-
.../designs/unb2a_heater/doc/README.txt | 10 +-
.../designs/unb2a_heater/hdllib.cfg | 4 +-
.../quartus/unb2a_heater_pins.tcl | 2 +-
.../uniboard2a/designs/unb2a_led/hdllib.cfg | 4 +-
.../unb2a_led/quartus/unb2a_minimal_pins.tcl | 2 +-
.../designs/unb2a_minimal/doc/README.txt | 18 +-
.../designs/unb2a_minimal/hdllib.cfg | 4 +-
.../quartus/unb2a_minimal_pins.tcl | 2 +-
.../designs/unb2a_test/doc/README.txt | 16 +-
.../unb2a_test/quartus/unb2a_test_pins.tcl | 6 +-
.../revisions/unb2a_test_10GbE/hdllib.cfg | 6 +-
.../quartus/unb2a_test_10GbE_pins.tcl | 4 +-
.../revisions/unb2a_test_1GbE/hdllib.cfg | 4 +-
.../quartus/unb2a_test_1GbE_pins.tcl | 2 +-
.../revisions/unb2a_test_all/hdllib.cfg | 4 +-
.../quartus/unb2a_test_all_pins.tcl | 6 +-
.../revisions/unb2a_test_ddr_MB_I/hdllib.cfg | 6 +-
.../quartus/unb2a_test_ddr_MB_I_pins.tcl | 4 +-
.../revisions/unb2a_test_ddr_MB_II/hdllib.cfg | 6 +-
.../quartus/unb2a_test_ddr_MB_II_pins.tcl | 4 +-
.../unb2a_test_ddr_MB_I_II/hdllib.cfg | 6 +-
.../quartus/unb2a_test_ddr_MB_I_II_pins.tcl | 4 +-
.../src/vhdl/qsys_unb2a_test_pkg.vhd | 2 +-
boards/uniboard2a/doc/unb2a_release_notes.txt | 20 +-
.../unb2a_board/quartus/unb2a_board.qsf | 6 +-
.../designs/unb2b_heater/doc/README.txt | 10 +-
.../designs/unb2b_heater/hdllib.cfg | 4 +-
.../quartus/unb2b_heater_pins.tcl | 2 +-
.../designs/unb2b_minimal/doc/README | 10 +-
.../designs/unb2b_minimal/hdllib.cfg | 7 +-
.../quartus/unb2b_minimal_pins.tcl | 2 +-
.../designs/unb2b_test/doc/README.txt | 16 +-
.../unb2b_test/quartus/unb2b_test_pins.tcl | 6 +-
.../revisions/unb2b_test_10GbE/hdllib.cfg | 6 +-
.../quartus/unb2b_test_10GbE_pins.tcl | 4 +-
.../src/vhdl/qsys_unb2b_test_pkg.vhd | 2 +-
.../unb2b_board/quartus/unb2b_board.qsf | 6 +-
.../dp/designs/unb1_dp_offload/hdllib.cfg | 4 +-
libraries/base/reorder/hdllib.cfg | 2 +-
.../dsp/bf/designs/unb1_fn_bf/hdllib.cfg | 2 +-
.../designs/unb1_correlator/hdllib.cfg | 2 +-
.../dsp/correlator/tb/vhdl/tb_correlator.vhd | 2 +-
libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd | 2 +-
.../dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd | 2 +-
.../dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd | 2 +-
.../dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd | 4 +-
.../dsp/filter/src/python/diff_lofar_coefs | 404 +++++++++---------
.../dsp/filter/src/python/diff_pfir_coefs | 26 +-
.../filter/src/python/fil_ppf_create_mifs.py | 4 +-
.../dsp/filter/src/python/recreate_4wb_mifs | 4 +-
.../dsp/filter/src/python/recreate_pfir_mifs | 6 +-
.../dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd | 4 +-
.../tb/vhdl/tb_fil_ppf_wide_file_data.vhd | 4 +-
.../tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd | 2 +-
.../dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd | 4 +-
.../dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd | 4 +-
libraries/io/ddr/hdllib.cfg | 6 +-
libraries/io/ddr3/hdllib.cfg | 10 +-
libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd | 4 +-
.../io/eth/designs/unb1_eth_10g/hdllib.cfg | 5 +-
libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl | 10 +-
.../io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl | 10 +-
.../io/eth/src/vhdl/avs2_eth_coe_hw_unb2.tcl | 10 +-
.../io/eth/src/vhdl/avs2_eth_coe_hw_unb2a.tcl | 10 +-
.../technology/ddr/tech_ddr_component_pkg.vhd | 22 +-
.../ddr/tech_ddr_mem_model_component_pkg.vhd | 4 +-
libraries/technology/hdllib.cfg | 6 +-
.../ip_arria10/clkbuf_global/compile_ip.tcl | 2 +-
.../ip_arria10/clkbuf_global/generate_ip.sh | 2 +-
.../ip_arria10/clkbuf_global/hdllib.cfg | 2 +-
.../ip_arria10/complex_mult/README.txt | 2 +-
.../ip_arria10/complex_mult/compile_ip.tcl | 2 +-
.../ip_arria10/complex_mult/generate_ip.sh | 2 +-
.../ip_arria10/complex_mult/hdllib.cfg | 2 +-
.../technology/ip_arria10/ddio/README.txt | 2 +-
.../technology/ip_arria10/ddio/compile_ip.tcl | 4 +-
.../technology/ip_arria10/ddio/generate_ip.sh | 2 +-
.../technology/ip_arria10/ddio/hdllib.cfg | 2 +-
.../ip_arria10/ddr4_4g_1600/compile_ip.tcl | 2 +-
.../ddr4_4g_1600/copy_hex_files.tcl | 2 +-
.../ddr4_4g_1600/doc/README_ddr4.txt | 2 +-
.../ip_arria10/ddr4_4g_1600/generate_ip.sh | 2 +-
.../ip_arria10/ddr4_4g_1600/hdllib.cfg | 2 +-
.../ip_arria10/ddr4_4g_2000/compile_ip.tcl | 2 +-
.../ddr4_4g_2000/copy_hex_files.tcl | 2 +-
.../ip_arria10/ddr4_4g_2000/generate_ip.sh | 2 +-
.../ip_arria10/ddr4_4g_2000/hdllib.cfg | 2 +-
.../ip_arria10/ddr4_8g_2400/compile_ip.tcl | 2 +-
.../ddr4_8g_2400/copy_hex_files.tcl | 2 +-
.../ip_arria10/ddr4_8g_2400/generate_ip.sh | 2 +-
.../ip_arria10/ddr4_8g_2400/hdllib.cfg | 2 +-
.../ip_arria10/ddr4_mem_model_141/README.txt | 14 +-
.../ddr4_mem_model_141/compile_ip.tcl | 4 +-
.../ddr4_mem_model_141/diff_mem_model.sh | 2 +-
.../ddr4_mem_model_141/generate_mem_model.sh | 2 +-
.../ip_arria10/ddr4_mem_model_141/hdllib.cfg | 2 +-
.../technology/ip_arria10/fifo/README.txt | 2 +-
.../technology/ip_arria10/fifo/generate_ip.sh | 2 +-
.../flash/asmi_parallel/compile_ip.tcl | 2 +-
.../flash/asmi_parallel/generate_ip.sh | 2 +-
.../ip_arria10/flash/asmi_parallel/hdllib.cfg | 2 +-
.../flash/remote_update/compile_ip.tcl | 2 +-
.../flash/remote_update/generate_ip.sh | 2 +-
.../ip_arria10/flash/remote_update/hdllib.cfg | 2 +-
.../fractional_pll_clk125/compile_ip.tcl | 2 +-
.../fractional_pll_clk125/generate_ip.sh | 2 +-
.../fractional_pll_clk125/hdllib.cfg | 2 +-
.../fractional_pll_clk200/compile_ip.tcl | 2 +-
.../fractional_pll_clk200/generate_ip.sh | 2 +-
.../fractional_pll_clk200/hdllib.cfg | 2 +-
.../technology/ip_arria10/generate-all-ip.sh | 2 +-
.../technology/ip_arria10/mac_10g/README.txt | 2 +-
.../ip_arria10/mac_10g/compile_ip.tcl | 4 +-
.../ip_arria10/mac_10g/generate_ip.sh | 2 +-
.../technology/ip_arria10/mac_10g/hdllib.cfg | 4 +-
.../ip_arria10/phy_10gbase_r/README.txt | 2 +-
.../ip_arria10/phy_10gbase_r/compile_ip.tcl | 2 +-
.../ip_arria10/phy_10gbase_r/generate_ip.sh | 2 +-
.../ip_arria10/phy_10gbase_r/hdllib.cfg | 2 +-
.../phy_10gbase_r_12/compile_ip.tcl | 2 +-
.../phy_10gbase_r_12/generate_ip.sh | 2 +-
.../ip_arria10/phy_10gbase_r_12/hdllib.cfg | 2 +-
.../phy_10gbase_r_24/compile_ip.tcl | 2 +-
.../phy_10gbase_r_24/generate_ip.sh | 2 +-
.../ip_arria10/phy_10gbase_r_24/hdllib.cfg | 2 +-
.../ip_arria10/phy_10gbase_r_4/compile_ip.tcl | 2 +-
.../ip_arria10/phy_10gbase_r_4/generate_ip.sh | 2 +-
.../ip_arria10/phy_10gbase_r_4/hdllib.cfg | 2 +-
.../phy_10gbase_r_48/compile_ip.tcl | 2 +-
.../phy_10gbase_r_48/generate_ip.sh | 2 +-
.../ip_arria10/phy_10gbase_r_48/hdllib.cfg | 2 +-
.../ip_arria10/pll_clk125/compile_ip.tcl | 2 +-
.../ip_arria10/pll_clk125/generate_ip.sh | 2 +-
.../ip_arria10/pll_clk125/hdllib.cfg | 2 +-
.../ip_arria10/pll_clk200/compile_ip.tcl | 2 +-
.../ip_arria10/pll_clk200/generate_ip.sh | 2 +-
.../ip_arria10/pll_clk200/hdllib.cfg | 2 +-
.../ip_arria10/pll_clk25/compile_ip.tcl | 2 +-
.../ip_arria10/pll_clk25/generate_ip.sh | 2 +-
.../ip_arria10/pll_clk25/hdllib.cfg | 2 +-
.../pll_xgmii_mac_clocks/compile_ip.tcl | 2 +-
.../pll_xgmii_mac_clocks/generate_ip.sh | 2 +-
.../pll_xgmii_mac_clocks/hdllib.cfg | 2 +-
.../technology/ip_arria10/ram/README.txt | 2 +-
.../technology/ip_arria10/ram/generate_ip.sh | 2 +-
.../ip_arria10/temp_sense/compile_ip.tcl | 2 +-
.../ip_arria10/temp_sense/generate_ip.sh | 2 +-
.../ip_arria10/temp_sense/hdllib.cfg | 2 +-
.../transceiver_pll_10g/compile_ip.tcl | 2 +-
.../transceiver_pll_10g/generate_ip.sh | 2 +-
.../ip_arria10/transceiver_pll_10g/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../generate_ip.sh | 2 +-
.../transceiver_reset_controller_1/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../generate_ip.sh | 2 +-
.../hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../generate_ip.sh | 2 +-
.../hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../generate_ip.sh | 2 +-
.../transceiver_reset_controller_4/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../generate_ip.sh | 2 +-
.../hdllib.cfg | 2 +-
.../ip_arria10/tse_sgmii_gx/README.txt | 4 +-
.../ip_arria10/tse_sgmii_gx/compile_ip.tcl | 2 +-
.../ip_arria10/tse_sgmii_gx/generate_ip.sh | 2 +-
.../ip_arria10/tse_sgmii_gx/hdllib.cfg | 2 +-
.../ip_arria10/tse_sgmii_lvds/README.txt | 2 +-
.../ip_arria10/tse_sgmii_lvds/compile_ip.tcl | 2 +-
.../ip_arria10/tse_sgmii_lvds/generate_ip.sh | 2 +-
.../ip_arria10/tse_sgmii_lvds/hdllib.cfg | 2 +-
.../ip_arria10/voltage_sense/compile_ip.tcl | 2 +-
.../ip_arria10/voltage_sense/generate_ip.sh | 2 +-
.../ip_arria10/voltage_sense/hdllib.cfg | 2 +-
.../alt_em10g32_170/compile_ip.tcl | 2 +-
.../alt_em10g32_170/hdllib.cfg | 4 +-
.../alt_mem_if_jtag_master_170/compile_ip.tcl | 2 +-
.../alt_mem_if_jtag_master_170/hdllib.cfg | 2 +-
.../altclkctrl_170/compile_ip.tcl | 2 +-
.../altclkctrl_170/hdllib.cfg | 2 +-
.../altera_asmi_parallel_170/compile_ip.tcl | 2 +-
.../altera_asmi_parallel_170/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../altera_avalon_mm_bridge_170/hdllib.cfg | 4 +-
.../compile_ip.tcl | 8 +-
.../hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../hdllib.cfg | 2 +-
.../altera_avalon_sc_fifo_170/compile_ip.tcl | 2 +-
.../altera_avalon_sc_fifo_170/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../hdllib.cfg | 2 +-
.../altera_emif_170/compile_ip.tcl | 44 +-
.../altera_emif_170/hdllib.cfg | 2 +-
.../altera_emif_arch_nf_170/compile_ip.tcl | 8 +-
.../altera_emif_arch_nf_170/hdllib.cfg | 4 +-
.../compile_ip.tcl | 8 +-
.../altera_emif_cal_slave_nf_170/hdllib.cfg | 2 +-
.../altera_eth_tse_170/compile_ip.tcl | 4 +-
.../altera_eth_tse_170/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../hdllib.cfg | 2 +-
.../altera_eth_tse_mac_170/compile_ip.tcl | 2 +-
.../altera_eth_tse_mac_170/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../hdllib.cfg | 2 +-
.../altera_iopll_170/compile_ip.tcl | 6 +-
.../altera_iopll_170/hdllib.cfg | 2 +-
.../altera_ip_col_if_170/compile_ip.tcl | 2 +-
.../altera_ip_col_if_170/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../altera_jtag_dc_streaming_170/hdllib.cfg | 2 +-
.../altera_lvds_170/compile_ip.tcl | 2 +-
.../altera_lvds_170/hdllib.cfg | 2 +-
.../altera_lvds_core20_170/compile_ip.tcl | 2 +-
.../altera_lvds_core20_170/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../hdllib.cfg | 2 +-
.../altera_mm_interconnect_170/compile_ip.tcl | 8 +-
.../altera_mm_interconnect_170/hdllib.cfg | 2 +-
.../altera_remote_update_170/compile_ip.tcl | 2 +-
.../altera_remote_update_170/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../altera_remote_update_core_170/hdllib.cfg | 4 +-
.../compile_ip.tcl | 2 +-
.../altera_reset_controller_170/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../altera_xcvr_atx_pll_a10_170/hdllib.cfg | 2 +-
.../altera_xcvr_fpll_a10_170/compile_ip.tcl | 2 +-
.../altera_xcvr_fpll_a10_170/hdllib.cfg | 2 +-
.../altera_xcvr_native_a10_170/compile_ip.tcl | 14 +-
.../altera_xcvr_native_a10_170/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../altera_xcvr_reset_control_170/hdllib.cfg | 2 +-
.../channel_adapter_170/compile_ip.tcl | 2 +-
.../channel_adapter_170/hdllib.cfg | 2 +-
.../timing_adapter_170/compile_ip.tcl | 2 +-
.../timing_adapter_170/hdllib.cfg | 2 +-
.../clkbuf_global/compile_ip.tcl | 2 +-
.../clkbuf_global/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/clkbuf_global/hdllib.cfg | 2 +-
.../ip_arria10_e1sg/complex_mult/README.txt | 2 +-
.../complex_mult/compile_ip.tcl | 2 +-
.../complex_mult/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/complex_mult/hdllib.cfg | 2 +-
.../ip_arria10_e1sg/ddio/README.txt | 2 +-
.../ip_arria10_e1sg/ddio/compile_ip.tcl | 4 +-
.../ip_arria10_e1sg/ddio/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/ddio/hdllib.cfg | 2 +-
.../ddr4_4g_1600/compile_ip.tcl | 2 +-
.../ddr4_4g_1600/copy_hex_files.tcl | 2 +-
.../ddr4_4g_1600/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg | 2 +-
.../ddr4_4g_2000/compile_ip.tcl | 2 +-
.../ddr4_4g_2000/copy_hex_files.tcl | 2 +-
.../ddr4_4g_2000/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg | 2 +-
.../ddr4_8g_1600/compile_ip.tcl | 2 +-
.../ddr4_8g_1600/copy_hex_files.tcl | 2 +-
.../ddr4_8g_1600/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg | 2 +-
.../ddr4_8g_2400/compile_ip.tcl | 2 +-
.../ddr4_8g_2400/copy_hex_files.tcl | 2 +-
.../ddr4_8g_2400/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg | 2 +-
.../ip_arria10_e1sg/fifo/README.txt | 2 +-
.../ip_arria10_e1sg/fifo/generate_ip.sh | 2 +-
.../flash/asmi_parallel/compile_ip.tcl | 2 +-
.../flash/asmi_parallel/generate_ip.sh | 2 +-
.../flash/asmi_parallel/hdllib.cfg | 2 +-
.../flash/remote_update/compile_ip.tcl | 2 +-
.../flash/remote_update/generate_ip.sh | 2 +-
.../flash/remote_update/hdllib.cfg | 2 +-
.../fractional_pll_clk125/compile_ip.tcl | 2 +-
.../fractional_pll_clk125/generate_ip.sh | 2 +-
.../fractional_pll_clk125/hdllib.cfg | 2 +-
.../fractional_pll_clk200/compile_ip.tcl | 2 +-
.../fractional_pll_clk200/generate_ip.sh | 2 +-
.../fractional_pll_clk200/hdllib.cfg | 2 +-
.../ip_arria10_e1sg/generate-all-ip.sh | 2 +-
.../ip_arria10_e1sg/mac_10g/README.txt | 2 +-
.../ip_arria10_e1sg/mac_10g/compile_ip.tcl | 2 +-
.../ip_arria10_e1sg/mac_10g/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/mac_10g/hdllib.cfg | 4 +-
.../ip_arria10_e1sg/mult_add4/compile_ip.tcl | 2 +-
.../ip_arria10_e1sg/mult_add4/generate_ip.sh | 2 +-
.../phy_10gbase_r/compile_ip.tcl | 2 +-
.../phy_10gbase_r/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg | 2 +-
.../phy_10gbase_r_12/compile_ip.tcl | 2 +-
.../phy_10gbase_r_12/generate_ip.sh | 2 +-
.../phy_10gbase_r_12/hdllib.cfg | 2 +-
.../phy_10gbase_r_24/compile_ip.tcl | 2 +-
.../phy_10gbase_r_24/generate_ip.sh | 2 +-
.../phy_10gbase_r_24/hdllib.cfg | 2 +-
.../phy_10gbase_r_3/compile_ip.tcl | 2 +-
.../phy_10gbase_r_3/generate_ip.sh | 2 +-
.../phy_10gbase_r_3/hdllib.cfg | 2 +-
.../phy_10gbase_r_4/compile_ip.tcl | 2 +-
.../phy_10gbase_r_4/generate_ip.sh | 2 +-
.../phy_10gbase_r_4/hdllib.cfg | 2 +-
.../phy_10gbase_r_48/compile_ip.tcl | 2 +-
.../phy_10gbase_r_48/generate_ip.sh | 2 +-
.../phy_10gbase_r_48/hdllib.cfg | 2 +-
.../ip_arria10_e1sg/pll_clk125/compile_ip.tcl | 2 +-
.../ip_arria10_e1sg/pll_clk125/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/pll_clk125/hdllib.cfg | 2 +-
.../ip_arria10_e1sg/pll_clk200/compile_ip.tcl | 2 +-
.../ip_arria10_e1sg/pll_clk200/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/pll_clk200/hdllib.cfg | 2 +-
.../ip_arria10_e1sg/pll_clk25/compile_ip.tcl | 2 +-
.../ip_arria10_e1sg/pll_clk25/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/pll_clk25/hdllib.cfg | 2 +-
.../pll_xgmii_mac_clocks/compile_ip.tcl | 2 +-
.../pll_xgmii_mac_clocks/generate_ip.sh | 2 +-
.../pll_xgmii_mac_clocks/hdllib.cfg | 2 +-
.../technology/ip_arria10_e1sg/ram/README.txt | 2 +-
.../ip_arria10_e1sg/ram/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/temp_sense/compile_ip.tcl | 2 +-
.../ip_arria10_e1sg/temp_sense/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/temp_sense/hdllib.cfg | 2 +-
.../transceiver_pll_10g/compile_ip.tcl | 2 +-
.../transceiver_pll_10g/generate_ip.sh | 2 +-
.../transceiver_pll_10g/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../generate_ip.sh | 2 +-
.../transceiver_reset_controller_1/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../generate_ip.sh | 2 +-
.../hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../generate_ip.sh | 2 +-
.../hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../generate_ip.sh | 2 +-
.../transceiver_reset_controller_3/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../generate_ip.sh | 2 +-
.../transceiver_reset_controller_4/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../generate_ip.sh | 2 +-
.../hdllib.cfg | 2 +-
.../ip_arria10_e1sg/tse_sgmii_gx/README.txt | 4 +-
.../tse_sgmii_gx/compile_ip.tcl | 2 +-
.../tse_sgmii_gx/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg | 2 +-
.../ip_arria10_e1sg/tse_sgmii_lvds/README.txt | 4 +-
.../tse_sgmii_lvds/compile_ip.tcl | 2 +-
.../tse_sgmii_lvds/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg | 2 +-
.../voltage_sense/compile_ip.tcl | 2 +-
.../voltage_sense/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/voltage_sense/hdllib.cfg | 2 +-
.../clkbuf_global/compile_ip.tcl | 2 +-
.../clkbuf_global/generate_ip.sh | 2 +-
.../clkbuf_global/hdllib.cfg | 2 +-
.../ip_arria10_e3sge3/complex_mult/README.txt | 2 +-
.../complex_mult/compile_ip.tcl | 2 +-
.../complex_mult/generate_ip.sh | 2 +-
.../ip_arria10_e3sge3/complex_mult/hdllib.cfg | 2 +-
.../ip_arria10_e3sge3/ddio/README.txt | 2 +-
.../ip_arria10_e3sge3/ddio/compile_ip.tcl | 4 +-
.../ip_arria10_e3sge3/ddio/generate_ip.sh | 2 +-
.../ip_arria10_e3sge3/ddio/hdllib.cfg | 2 +-
.../ddr4_4g_1600/compile_ip.tcl | 2 +-
.../ddr4_4g_1600/copy_hex_files.tcl | 2 +-
.../ddr4_4g_1600/generate_ip.sh | 2 +-
.../ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg | 2 +-
.../ddr4_4g_2000/compile_ip.tcl | 2 +-
.../ddr4_4g_2000/copy_hex_files.tcl | 2 +-
.../ddr4_4g_2000/generate_ip.sh | 2 +-
.../ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg | 2 +-
.../ddr4_8g_1600/compile_ip.tcl | 2 +-
.../ddr4_8g_1600/copy_hex_files.tcl | 2 +-
.../ddr4_8g_1600/generate_ip.sh | 2 +-
.../ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg | 2 +-
.../ddr4_8g_2400/compile_ip.tcl | 2 +-
.../ddr4_8g_2400/copy_hex_files.tcl | 2 +-
.../ddr4_8g_2400/generate_ip.sh | 2 +-
.../ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg | 2 +-
.../ip_arria10_e3sge3/fifo/README.txt | 2 +-
.../ip_arria10_e3sge3/fifo/generate_ip.sh | 2 +-
.../flash/asmi_parallel/compile_ip.tcl | 2 +-
.../flash/asmi_parallel/generate_ip.sh | 2 +-
.../flash/asmi_parallel/hdllib.cfg | 2 +-
.../flash/remote_update/compile_ip.tcl | 2 +-
.../flash/remote_update/generate_ip.sh | 2 +-
.../flash/remote_update/hdllib.cfg | 2 +-
.../fractional_pll_clk125/compile_ip.tcl | 2 +-
.../fractional_pll_clk125/generate_ip.sh | 2 +-
.../fractional_pll_clk125/hdllib.cfg | 2 +-
.../fractional_pll_clk200/compile_ip.tcl | 2 +-
.../fractional_pll_clk200/generate_ip.sh | 2 +-
.../fractional_pll_clk200/hdllib.cfg | 2 +-
.../ip_arria10_e3sge3/generate-all-ip.sh | 2 +-
.../ip_arria10_e3sge3/mac_10g/README.txt | 2 +-
.../ip_arria10_e3sge3/mac_10g/compile_ip.tcl | 4 +-
.../ip_arria10_e3sge3/mac_10g/generate_ip.sh | 2 +-
.../ip_arria10_e3sge3/mac_10g/hdllib.cfg | 4 +-
.../mult_add4/compile_ip.tcl | 2 +-
.../mult_add4/generate_ip.sh | 2 +-
.../phy_10gbase_r/compile_ip.tcl | 2 +-
.../phy_10gbase_r/generate_ip.sh | 2 +-
.../phy_10gbase_r/hdllib.cfg | 2 +-
.../phy_10gbase_r_12/compile_ip.tcl | 2 +-
.../phy_10gbase_r_12/generate_ip.sh | 2 +-
.../phy_10gbase_r_12/hdllib.cfg | 2 +-
.../phy_10gbase_r_24/compile_ip.tcl | 2 +-
.../phy_10gbase_r_24/generate_ip.sh | 2 +-
.../phy_10gbase_r_24/hdllib.cfg | 2 +-
.../phy_10gbase_r_4/compile_ip.tcl | 2 +-
.../phy_10gbase_r_4/generate_ip.sh | 2 +-
.../phy_10gbase_r_4/hdllib.cfg | 2 +-
.../phy_10gbase_r_48/compile_ip.tcl | 2 +-
.../phy_10gbase_r_48/generate_ip.sh | 2 +-
.../phy_10gbase_r_48/hdllib.cfg | 2 +-
.../pll_clk125/compile_ip.tcl | 2 +-
.../pll_clk125/generate_ip.sh | 2 +-
.../ip_arria10_e3sge3/pll_clk125/hdllib.cfg | 2 +-
.../pll_clk200/compile_ip.tcl | 2 +-
.../pll_clk200/generate_ip.sh | 2 +-
.../ip_arria10_e3sge3/pll_clk200/hdllib.cfg | 2 +-
.../pll_clk25/compile_ip.tcl | 2 +-
.../pll_clk25/generate_ip.sh | 2 +-
.../ip_arria10_e3sge3/pll_clk25/hdllib.cfg | 2 +-
.../pll_xgmii_mac_clocks/compile_ip.tcl | 2 +-
.../pll_xgmii_mac_clocks/generate_ip.sh | 2 +-
.../pll_xgmii_mac_clocks/hdllib.cfg | 2 +-
.../ip_arria10_e3sge3/ram/README.txt | 2 +-
.../ip_arria10_e3sge3/ram/generate_ip.sh | 2 +-
.../temp_sense/compile_ip.tcl | 2 +-
.../temp_sense/generate_ip.sh | 2 +-
.../ip_arria10_e3sge3/temp_sense/hdllib.cfg | 2 +-
.../transceiver_pll_10g/compile_ip.tcl | 2 +-
.../transceiver_pll_10g/generate_ip.sh | 2 +-
.../transceiver_pll_10g/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../generate_ip.sh | 2 +-
.../transceiver_reset_controller_1/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../generate_ip.sh | 2 +-
.../hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../generate_ip.sh | 2 +-
.../hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../generate_ip.sh | 2 +-
.../transceiver_reset_controller_4/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../generate_ip.sh | 2 +-
.../hdllib.cfg | 2 +-
.../ip_arria10_e3sge3/tse_sgmii_gx/README.txt | 4 +-
.../tse_sgmii_gx/compile_ip.tcl | 2 +-
.../tse_sgmii_gx/generate_ip.sh | 2 +-
.../ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg | 2 +-
.../tse_sgmii_lvds/README.txt | 4 +-
.../tse_sgmii_lvds/compile_ip.tcl | 2 +-
.../tse_sgmii_lvds/generate_ip.sh | 2 +-
.../tse_sgmii_lvds/hdllib.cfg | 2 +-
.../voltage_sense/compile_ip.tcl | 2 +-
.../voltage_sense/generate_ip.sh | 2 +-
.../voltage_sense/hdllib.cfg | 2 +-
.../ddr3_mem_model/compile_ip.tcl | 2 +-
.../ddr3_mem_model/generate_ip.sh | 2 +-
.../ip_stratixiv/ddr3_mem_model/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../copy_hex_files.tcl | 2 +-
.../generate_ip.sh | 2 +-
.../ddr3_uphy_16g_dual_rank_800/hdllib.cfg | 4 +-
.../ddr3_uphy_4g_800_master/compile_ip.tcl | 2 +-
.../copy_hex_files.tcl | 2 +-
.../ddr3_uphy_4g_800_master/generate_ip.sh | 2 +-
.../ddr3_uphy_4g_800_master/hdllib.cfg | 4 +-
.../ddr3_uphy_4g_800_slave/compile_ip.tcl | 2 +-
.../ddr3_uphy_4g_800_slave/copy_hex_files.tcl | 2 +-
.../ddr3_uphy_4g_800_slave/generate_ip.sh | 2 +-
.../ddr3_uphy_4g_800_slave/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../copy_hex_files.tcl | 2 +-
.../generate_ip.sh | 2 +-
.../hdllib.cfg | 4 +-
.../compile_ip.tcl | 2 +-
.../copy_hex_files.tcl | 2 +-
.../generate_ip.sh | 2 +-
.../hdllib.cfg | 4 +-
.../technology/ip_stratixiv/flash/hdllib.cfg | 2 +-
.../ip_stratixiv/generate-all-ip.sh | 2 +-
.../ip_stratixiv/mac_10g/compile_ip.tcl | 2 +-
.../ip_stratixiv/mac_10g/generate_ip.sh | 2 +-
.../ip_stratixiv/mac_10g/hdllib.cfg | 2 +-
.../ip_stratixiv/phy_xaui/compile_ip.tcl | 2 +-
.../ip_stratixiv/phy_xaui/compile_ip_soft.tcl | 2 +-
.../ip_stratixiv/phy_xaui/generate_ip.sh | 2 +-
.../ip_stratixiv/phy_xaui/hdllib.cfg | 4 +-
.../mac_10g/tech_mac_10g_component_pkg.vhd | 2 +-
.../technology/tse/tech_tse_component_pkg.vhd | 16 +-
590 files changed, 1158 insertions(+), 1144 deletions(-)
create mode 100644 .gitignore
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000000..b1619157a9
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,4 @@
+*log
+build*
+*generated
+*pyc
diff --git a/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg b/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
index 68229b7b18..e970f79671 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
@@ -1,6 +1,7 @@
hdl_lib_name = unb1_bn_capture
hdl_library_clause_name = unb1_bn_capture_lib
hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag aduh
+hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
synth_files =
@@ -22,19 +23,19 @@ regression_test_vhdl =
tb/vhdl/tb_node_unb1_bn_capture.vhd
[modelsim_project_file]
-modelsim_copy_files = $RADIOHDL/libraries/io/i2c/tb/data data
- $RADIOHDL/libraries/base/diag/src/data data
+modelsim_copy_files = $RADIOHDL_WORK/libraries/io/i2c/tb/data data
+ $RADIOHDL_WORK/libraries/base/diag/src/data data
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files = quartus/sopc_unb1_bn_capture.sopc .
- $RADIOHDL/libraries/io/i2c/tb/data data
- $RADIOHDL/libraries/base/diag/src/data data
+ $RADIOHDL_WORK/libraries/io/i2c/tb/data data
+ $RADIOHDL_WORK/libraries/base/diag/src/data data
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_tcl_files =
quartus/unb1_bn_capture_pins.tcl
@@ -42,7 +43,7 @@ quartus_tcl_files =
quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.qip
quartus_sdc_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
diff --git a/boards/uniboard1/designs/unb1_bn_capture/quartus/unb1_bn_capture_pins.tcl b/boards/uniboard1/designs/unb1_bn_capture/quartus/unb1_bn_capture_pins.tcl
index 56d0bc7bac..f2cfef868f 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/quartus/unb1_bn_capture_pins.tcl
+++ b/boards/uniboard1/designs/unb1_bn_capture/quartus/unb1_bn_capture_pins.tcl
@@ -1,13 +1,13 @@
# Pin assignments
# -- GENERAL: clk, pps, wdi, inta, intb
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
# -- 1GbE Control Interface
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
# -- I2C Interface to Sensors
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
# -- Other: version[1:0], id[7:0], testio[7:0]
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
# -- BN_BI ADC pins
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_adc_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_adc_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg b/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
index 327cfda99a..e927886e07 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
@@ -1,6 +1,7 @@
hdl_lib_name = unb1_bn_terminal_bg
hdl_library_clause_name = unb1_bn_terminal_bg_lib
hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag bf
+hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
synth_files =
@@ -14,17 +15,17 @@ test_bench_files =
[modelsim_project_file]
-modelsim_copy_files = $RADIOHDL/libraries/base/diag/src/data data
+modelsim_copy_files = $RADIOHDL_WORK/libraries/base/diag/src/data data
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files = quartus/sopc_unb1_bn_terminal_bg.sopc .
- $RADIOHDL/libraries/base/diag/src/data data
+ $RADIOHDL_WORK/libraries/base/diag/src/data data
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_tcl_files =
quartus/unb1_bn_terminal_bg_pins.tcl
@@ -32,4 +33,4 @@ quartus_tcl_files =
quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.qip
quartus_sdc_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/quartus/unb1_bn_terminal_bg_pins.tcl b/boards/uniboard1/designs/unb1_bn_terminal_bg/quartus/unb1_bn_terminal_bg_pins.tcl
index 41f447693a..0a38a91c5b 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/quartus/unb1_bn_terminal_bg_pins.tcl
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/quartus/unb1_bn_terminal_bg_pins.tcl
@@ -1,14 +1,14 @@
# Pin assignments
# -- GENERAL: clk, pps, wdi, inta, intb
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
# -- 1GbE Control Interface
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
# -- I2C Interface to Sensors
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
# -- Other: version[1:0], id[7:0], testio[7:0]
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
# -- Mesh pins.
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_mesh_tr_clk_pin.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_mesh_nocmu_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_mesh_tr_clk_pin.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_mesh_nocmu_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_ddr3/doc/README b/boards/uniboard1/designs/unb1_ddr3/doc/README
index a6b8f853c3..4134e5df31 100644
--- a/boards/uniboard1/designs/unb1_ddr3/doc/README
+++ b/boards/uniboard1/designs/unb1_ddr3/doc/README
@@ -2,8 +2,8 @@ Quick steps to compile and use design [unb1_ddr3] in RadionHDL
--------------------------------------------------------------
Start with the Oneclick Commands:
- python $RADIOHDL/tools/oneclick/base/modelsim_config.py
- python $RADIOHDL/tools/oneclick/base/quartus_config.py
+ python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py
+ python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py
Generate MMM for SOPC:
run_sopc unb1 unb1_ddr3
diff --git a/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
index b24fe5c0be..d3453f987c 100644
--- a/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
@@ -16,7 +16,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
[quartus_project_file]
@@ -26,7 +26,7 @@ quartus_copy_files =
quartus/sopc_unb1_ddr3.sopc .
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.qip
@@ -36,5 +36,5 @@ quartus_tcl_files =
quartus/unb1_ddr3_pins_constraints.tcl
quartus_sdc_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
diff --git a/boards/uniboard1/designs/unb1_ddr3/quartus/unb1_ddr3_pins.tcl b/boards/uniboard1/designs/unb1_ddr3/quartus/unb1_ddr3_pins.tcl
index 8c1eadf575..caedfb746e 100644
--- a/boards/uniboard1/designs/unb1_ddr3/quartus/unb1_ddr3_pins.tcl
+++ b/boards/uniboard1/designs/unb1_ddr3/quartus/unb1_ddr3_pins.tcl
@@ -20,8 +20,8 @@
###############################################################################
# -- include ddr3 pins
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
-#source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+#source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
# -- include the clock pin
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/doc/README b/boards/uniboard1/designs/unb1_ddr3_reorder/doc/README
index f52ac9c7e5..489688ec45 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/doc/README
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/doc/README
@@ -2,8 +2,8 @@ Quick steps to compile and use design [unb1_ddr3_reorder] in RadioHDL
--------------------------------------------------------------
Start with the Oneclick Commands:
- python $RADIOHDL/tools/oneclick/base/modelsim_config.py
- python $RADIOHDL/tools/oneclick/base/quartus_config.py
+ python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py
+ python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py
Generate MMM for SOPC:
run_sopc unb1 unb1_ddr3_reorder
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/quartus/unb1_ddr3_reorder_pins.tcl b/boards/uniboard1/designs/unb1_ddr3_reorder/quartus/unb1_ddr3_reorder_pins.tcl
index 66c2161ff4..9834de8f9a 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/quartus/unb1_ddr3_reorder_pins.tcl
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/quartus/unb1_ddr3_reorder_pins.tcl
@@ -20,7 +20,7 @@
###############################################################################
# -- include ddr3 pins
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
# -- include the clock pin
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
index 8be0a5b4fb..4bded51236 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
@@ -22,7 +22,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
[quartus_project_file]
@@ -33,7 +33,7 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_tcl_files =
../../quartus/unb1_ddr3_reorder_pins.tcl
@@ -42,6 +42,6 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
- $RADIOHDL/build/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.qip
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+ $RADIOHDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.qip
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
index 104d038b62..d9e3a8cd86 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
@@ -22,7 +22,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
[quartus_project_file]
@@ -33,7 +33,7 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_tcl_files =
../../quartus/unb1_ddr3_reorder_pins.tcl
@@ -42,6 +42,6 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
- $RADIOHDL/build/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.qip
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+ $RADIOHDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.qip
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/doc/README b/boards/uniboard1/designs/unb1_ddr3_transpose/doc/README
index b3475d0f6b..d2fd86f43c 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/doc/README
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/doc/README
@@ -4,8 +4,8 @@ Quick steps to compile and use design [unb1_ddr3_transpose] in RadionHDL
Start with the Oneclick Commands:
- python $RADIOHDL/tools/oneclick/base/modelsim_config.py
- python $RADIOHDL/tools/oneclick/base/quartus_config.py
+ python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py
+ python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py
Generate MMM for SOPC and QSYS:
run_sopc unb1 unb1_ddr3_transpose
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
index 97059fae53..6c541b4951 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
@@ -16,7 +16,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
[quartus_project_file]
@@ -26,7 +26,7 @@ quartus_copy_files =
quartus/sopc_unb_ddr3_transpose.sopc .
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_tcl_files =
quartus/unb1_ddr3_transpose_pins.tcl
@@ -36,5 +36,5 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.qip
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb1_ddr3_transpose_pins.tcl b/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb1_ddr3_transpose_pins.tcl
index 644fc9a105..1f162d6353 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb1_ddr3_transpose_pins.tcl
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb1_ddr3_transpose_pins.tcl
@@ -3,5 +3,5 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tc
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg b/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
index fb01a093b4..d956258b51 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
@@ -1,6 +1,7 @@
hdl_lib_name = unb1_fn_terminal_db
hdl_library_clause_name = unb1_fn_terminal_db_lib
hdl_lib_uses_synth = common technology mm i2c unb1_board diag
+hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
synth_files =
@@ -22,7 +23,7 @@ synth_top_level_entity =
quartus_copy_files = quartus/sopc_unb1_fn_terminal_db.sopc .
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_tcl_files =
quartus/unb1_fn_terminal_db_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_heater/doc/README b/boards/uniboard1/designs/unb1_heater/doc/README
index 4919dd1d76..a907cf2b91 100644
--- a/boards/uniboard1/designs/unb1_heater/doc/README
+++ b/boards/uniboard1/designs/unb1_heater/doc/README
@@ -4,8 +4,8 @@ Quick steps to compile and use design [unb1_heater] in RadionHDL
Start with the Oneclick Commands:
- python $RADIOHDL/tools/oneclick/base/modelsim_config.py
- python $RADIOHDL/tools/oneclick/base/quartus_config.py
+ python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py
+ python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py
Generate MMM for SOPC and QSYS:
run_qsys unb1 unb1_heater
diff --git a/boards/uniboard1/designs/unb1_heater/hdllib.cfg b/boards/uniboard1/designs/unb1_heater/hdllib.cfg
index 19c04e7f3c..84640d28b1 100644
--- a/boards/uniboard1/designs/unb1_heater/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_heater/hdllib.cfg
@@ -23,10 +23,10 @@ quartus_copy_files =
quartus/qsys_unb1_heater.qsys .
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
quartus/unb1_heater_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_heater/quartus/unb1_heater_pins.tcl b/boards/uniboard1/designs/unb1_heater/quartus/unb1_heater_pins.tcl
index dfd44294b3..ff00994603 100644
--- a/boards/uniboard1/designs/unb1_heater/quartus/unb1_heater_pins.tcl
+++ b/boards/uniboard1/designs/unb1_heater/quartus/unb1_heater_pins.tcl
@@ -19,8 +19,8 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_minimal/doc/README b/boards/uniboard1/designs/unb1_minimal/doc/README
index ec32e31ac2..d85df74cd1 100644
--- a/boards/uniboard1/designs/unb1_minimal/doc/README
+++ b/boards/uniboard1/designs/unb1_minimal/doc/README
@@ -4,8 +4,8 @@ Quick steps to compile and use design [unb1_minimal] in RadionHDL
Start with the Oneclick Commands:
- python $RADIOHDL/tools/oneclick/base/modelsim_config.py
- python $RADIOHDL/tools/oneclick/base/quartus_config.py
+ python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py
+ python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py
Generate MMM for SOPC and QSYS:
run_sopc unb1 unb1_minimal_sopc
@@ -58,12 +58,12 @@ Convert .sof to .rbf:
Send to LCU capture5:
- scp $RADIOHDL/build/quartus/unb1_minimal_qsys/unb1_minimal_qsys.rbf capture5:~/rbf/ # QSYS
+ scp $RADIOHDL_WORK/build/quartus/unb1_minimal_qsys/unb1_minimal_qsys.rbf capture5:~/rbf/ # QSYS
or:
- scp $RADIOHDL/build/quartus/unb1_minimal_qsys/unb1_minimal_sopc.rbf capture5:~/rbf/ # SOPC
+ scp $RADIOHDL_WORK/build/quartus/unb1_minimal_qsys/unb1_minimal_sopc.rbf capture5:~/rbf/ # SOPC
# Now login on capture5 and use pythonscript to program flash:
- cd $RADIOHDL/boards/uniboard1/designs/unb1_minimal/tb/python
+ cd $RADIOHDL_WORK/boards/uniboard1/designs/unb1_minimal/tb/python
# for example use frontnode 0 on uniboard 0:
python tc_unb1_minimal.py --gn 0 --seq REGMAP,FLASH -s ~/rbf/unb1_minimal_qsys.rbf # QSYS
diff --git a/boards/uniboard1/designs/unb1_minimal/quartus/unb1_minimal_pins.tcl b/boards/uniboard1/designs/unb1_minimal/quartus/unb1_minimal_pins.tcl
index dfd44294b3..ff00994603 100644
--- a/boards/uniboard1/designs/unb1_minimal/quartus/unb1_minimal_pins.tcl
+++ b/boards/uniboard1/designs/unb1_minimal/quartus/unb1_minimal_pins.tcl
@@ -19,8 +19,8 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg
index 573fbd31de..46135b9788 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg
@@ -21,10 +21,10 @@ quartus_copy_files =
qsys_unb1_minimal_mm_arbiter.qsys .
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
../../quartus/unb1_minimal_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg
index 2909ebe510..30e64fde99 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
../../quartus/qsys_unb1_minimal.qsys .
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
../../quartus/unb1_minimal_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg
index 47ab642c83..8feddd68dc 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg
@@ -23,10 +23,10 @@ quartus_copy_files =
../../quartus/qsys_wo_pll_unb1_minimal.qsys .
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
../../quartus/unb1_minimal_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg
index b533e42f36..2724f918e6 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg
@@ -21,10 +21,10 @@ quartus_copy_files =
../../quartus/sopc_unb1_minimal.sopc .
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
../../quartus/unb1_minimal_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
index f687fcbc73..f34d0b341d 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
@@ -1,6 +1,7 @@
hdl_lib_name = unb1_terminal_bg_mesh_db
hdl_library_clause_name = unb1_terminal_bg_mesh_db_lib
hdl_lib_uses_synth = common technology mm i2c unb1_board diag eth tech_tse
+hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
synth_files =
@@ -23,7 +24,7 @@ synth_top_level_entity =
quartus_copy_files = quartus/qsys_unb1_terminal_bg_mesh_db.qsys .
src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_tcl_files =
quartus/unb1_terminal_bg_mesh_db_pins.tcl
@@ -32,4 +33,4 @@ quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.qip
quartus_sdc_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
diff --git a/boards/uniboard1/designs/unb1_test/doc/README b/boards/uniboard1/designs/unb1_test/doc/README
index 6aca7ca007..bb6725a13e 100644
--- a/boards/uniboard1/designs/unb1_test/doc/README
+++ b/boards/uniboard1/designs/unb1_test/doc/README
@@ -16,16 +16,16 @@ The following revisions are available for unb1_test (see the directories in ../r
-> In case of a new installation, the IP's have to be generated for Stratix IV.
- In the: $RADIOHDL/libraries/technology/ip_stratixiv
+ In the: $RADIOHDL_WORK/libraries/technology/ip_stratixiv
directory; run the bash script: ./generate-all-ip.sh
-> For compilation it might be necessary to check the .vhd file:
- $RADIOHDL/libraries/technology/technology_select_pkg.vhd
+ $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
1. Start with the Oneclick Commands:
- python $RADIOHDL/tools/oneclick/base/modelsim_config.py -t unb1
- python $RADIOHDL/tools/oneclick/base/quartus_config.py -t unb1
+ python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb1
+ python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb1
2. Generate MMM for QSYS (select one of these revisions):
@@ -91,7 +91,7 @@ Convert .sof to .rbf:
Send to LCU (capture5):
# for example the unb1_test_10GbE revision:
- scp $RADIOHDL/build/quartus/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.rbf capture5:~/rbf/
+ scp $RADIOHDL_WORK/build/quartus/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.rbf capture5:~/rbf/
# Now login on capture5 and use pythonscript to program flash:
cd unb1_test/tb/python
@@ -118,10 +118,10 @@ defining the pinning:
2. unb1_test_ddr_MB_I_II_pins_constraints.tcl (pin attributes like termination etc..)
The 2nd tcl file can be created with Quartus. Here are the steps:
-- generate the IP's by running: $RADIOHDL/libraries/technology/ip_stratixiv/generate-all-ip.sh
+- generate the IP's by running: $RADIOHDL_WORK/libraries/technology/ip_stratixiv/generate-all-ip.sh
- Start synthesis in the Quartus GUI. Only the Analysis step!!
- Then in Quartus click: Tools/TclScripts.
- Open the Tcl file: $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0_pin_assignments.tcl
+ Open the Tcl file: $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0_pin_assignments.tcl
Click Run.
- Then Continue synthesis with Fitter, or restart with Analysis.
- Copy the generated build/unb1_test_ddr_MB_I_II.qsf file to ./designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/quartus/unb1_test_ddr_MB_I_II_pins_constraints.tcl
diff --git a/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins.tcl b/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins.tcl
index 06974891a2..27ecdf6551 100644
--- a/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins.tcl
+++ b/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins.tcl
@@ -85,6 +85,6 @@ set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_RX[3]
# -- include ddr3 pins
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
index c608a07b37..790c2fcb41 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
quartus/unb1_test_10GbE_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg
index 27587a6b03..fc2febb454 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
quartus/unb1_test_10GbE_tx_only_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg
index 68110374db..78f41d558f 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
quartus/unb1_test_1GbE_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/quartus/unb1_test_1GbE_pins.tcl b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/quartus/unb1_test_1GbE_pins.tcl
index 06974891a2..27ecdf6551 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/quartus/unb1_test_1GbE_pins.tcl
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/quartus/unb1_test_1GbE_pins.tcl
@@ -85,6 +85,6 @@ set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_RX[3]
# -- include ddr3 pins
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
index 18894362a5..f5dcccf80c 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
[quartus_project_file]
@@ -28,10 +28,10 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
../../quartus/unb1_test_pins.tcl
@@ -41,6 +41,6 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_all/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
- #$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+ #$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
index f37c913aa1..8363cba5b7 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
[quartus_project_file]
@@ -28,10 +28,10 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
quartus/unb1_test_ddr_pins.tcl
@@ -41,6 +41,6 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
- #$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+ #$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/quartus/unb1_test_ddr_pins.tcl b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/quartus/unb1_test_ddr_pins.tcl
index 65282d0ba6..bac6c86884 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/quartus/unb1_test_ddr_pins.tcl
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/quartus/unb1_test_ddr_pins.tcl
@@ -25,6 +25,6 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
# -- include ddr3 pins
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
index 1454028e66..f768ee780f 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
@@ -18,7 +18,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
[quartus_project_file]
@@ -29,10 +29,10 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
quartus/unb1_test_ddr_16g_MB_I_pins.tcl
@@ -42,5 +42,5 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/quartus/unb1_test_ddr_16g_MB_I_pins.tcl b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/quartus/unb1_test_ddr_16g_MB_I_pins.tcl
index 850f27204a..e6c6cd90d5 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/quartus/unb1_test_ddr_16g_MB_I_pins.tcl
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/quartus/unb1_test_ddr_16g_MB_I_pins.tcl
@@ -25,5 +25,5 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
# -- include ddr3 pins
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
index 0976da6a26..131abe1162 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
[quartus_project_file]
@@ -28,10 +28,10 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
quartus/unb1_test_ddr_pins_16g_MB_II.tcl
@@ -41,5 +41,5 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/quartus/unb1_test_ddr_pins_16g_MB_II.tcl b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/quartus/unb1_test_ddr_pins_16g_MB_II.tcl
index e6d56bb522..f4fac0a19d 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/quartus/unb1_test_ddr_pins_16g_MB_II.tcl
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/quartus/unb1_test_ddr_pins_16g_MB_II.tcl
@@ -25,5 +25,5 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
# -- include ddr3 pins
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
index 02b71ffe27..3c9364d69e 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
[quartus_project_file]
@@ -28,10 +28,10 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
quartus/unb1_test_ddr_16g_MB_I_II_pins.tcl
@@ -41,5 +41,5 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/quartus/unb1_test_ddr_16g_MB_I_II_pins.tcl b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/quartus/unb1_test_ddr_16g_MB_I_II_pins.tcl
index 65282d0ba6..bac6c86884 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/quartus/unb1_test_ddr_16g_MB_I_II_pins.tcl
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/quartus/unb1_test_ddr_16g_MB_I_II_pins.tcl
@@ -25,6 +25,6 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
# -- include ddr3 pins
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
index d6d700acef..2f10f4fbe8 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
[quartus_project_file]
@@ -28,10 +28,10 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
quartus/unb1_test_ddr_MB_I_pins.tcl
@@ -41,5 +41,5 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
index b1569dd161..7fe0acbd0a 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
[quartus_project_file]
@@ -28,10 +28,10 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
quartus/unb1_test_ddr_MB_I_pins.tcl
@@ -41,5 +41,5 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
index 69d6bb04c8..b0b65d1327 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
[quartus_project_file]
@@ -27,10 +27,10 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
quartus/unb1_test_ddr_MB_I_II_pins.tcl
@@ -40,5 +40,5 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/quartus/unb1_test_ddr_pins.tcl b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/quartus/unb1_test_ddr_pins.tcl
index 65282d0ba6..bac6c86884 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/quartus/unb1_test_ddr_pins.tcl
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/quartus/unb1_test_ddr_pins.tcl
@@ -25,6 +25,6 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
# -- include ddr3 pins
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
index 3ef8d196d4..0e0b26f797 100644
--- a/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
@@ -26,7 +26,7 @@ quartus_copy_files =
# src/hex/ hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_tcl_files =
quartus/unb1_tr_10GbE_pins.tcl
@@ -37,4 +37,4 @@ quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_tr_10GbE/qsys_unb1_tr_10GbE/synthesis/qsys_unb1_tr_10GbE.qip
quartus_sdc_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
diff --git a/boards/uniboard1/libraries/unb1_board/hdllib.cfg b/boards/uniboard1/libraries/unb1_board/hdllib.cfg
index 3c0c0332a0..f9b219ceaa 100644
--- a/boards/uniboard1/libraries/unb1_board/hdllib.cfg
+++ b/boards/uniboard1/libraries/unb1_board/hdllib.cfg
@@ -43,9 +43,9 @@ synth_files =
src/vhdl/unb1_board_peripherals_pkg.vhd
- # For BN the $RADIOHDL/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd is
+ # For BN the $RADIOHDL_WORK/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd is
# referred to directly in the apertif_unb1_bn_filterbank library.
- # For FN a copy of $RADIOHDL/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
+ # For FN a copy of $RADIOHDL_WORK/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
# is taken via this unb1_board library:
src/vhdl/node_unb1_fn_terminal_db.vhd
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_allpins.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_allpins.tcl
index e9a0020eca..b18c31a46b 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_allpins.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_allpins.tcl
@@ -23,7 +23,7 @@
# Pin assignments
# -- Common
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
# -- Back Node specific
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_pins.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_pins.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_pins.tcl
index 01b6b0ee2d..c023237cd6 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_pins.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_pins.tcl
@@ -23,10 +23,10 @@
# Back node specific pin assignments
# -- Backplane Interface
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_tr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_tr_pins.tcl
# -- FN to BN Interface added 08-01-2010
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_mesh_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_mesh_pins.tcl
# -- ADC Interface
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_adc_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_adc_pins.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
index 07a96e3039..fa264372aa 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
@@ -23,22 +23,22 @@
# Common pin assignments for front_node and back_node
# -- General: clk, pps, wdi, inta, intb
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
# -- FPGA Interconnects Front-Node Back-Node
# Clocks only as transceiver pins are now different (08-01-2010)
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_tr_clk_pins.tcl
-#source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_tr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_tr_clk_pins.tcl
+#source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_tr_pins.tcl
# -- 1GbE Control Interface
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
# -- SO-DIMM Memory Banks I and II
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_ddr_I_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_ddr_II_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_ddr_I_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_ddr_II_pins.tcl
# -- I2C Interface to Sensors
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
# -- Other: version[1:0], id[7:0], testio[7:0]
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_allpins.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_allpins.tcl
index f2bc1b735d..ba55f0e9e5 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_allpins.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_allpins.tcl
@@ -23,7 +23,7 @@
# Pin assignments
# -- Common
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
# -- Front Node specific
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_pins.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_pins.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_pins.tcl
index 47b4a220ec..afbd717cd6 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_pins.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_pins.tcl
@@ -23,9 +23,9 @@
# Front node specific pin assignments
# -- Front Interface (10GbE)
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_cntrl_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_cntrl_pins.tcl
# -- FN to BN Mesh Interface added 08-01-2010
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_mesh_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_mesh_pins.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_back_pcs.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_back_pcs.tcl
index 0f53630b3a..d2a233a471 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_back_pcs.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_back_pcs.tcl
@@ -20,6 +20,6 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tx_back_pcs.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_rx_back_pcs.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tx_back_pcs.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_rx_back_pcs.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs.tcl
index 994c291362..856ec42e60 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs.tcl
@@ -20,7 +20,7 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_clk.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_0.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_1.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_2.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_clk.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_0.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_1.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_2.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_clk.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_clk.tcl
index 4bd3291064..22f4d234b2 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_clk.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_clk.tcl
@@ -20,7 +20,7 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_cntrl_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_cntrl_pins.tcl
set_location_assignment PIN_AA2 -to SA_CLK
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SA_CLK
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_mesh_pcs.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_mesh_pcs.tcl
index ab9c957cf8..926e243c89 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_mesh_pcs.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_mesh_pcs.tcl
@@ -20,5 +20,5 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tx_mesh_pcs.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_rx_mesh_pcs.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tx_mesh_pcs.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_rx_mesh_pcs.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
index 4e2396ba38..35e67d8844 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+++ b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
@@ -22,7 +22,7 @@
# This QSF is sourced by other design QSF files.
# ==============================================
# Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
# Device:
set_global_assignment -name FAMILY "Stratix IV"
@@ -49,7 +49,7 @@ set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCS128
if { [info exists ::env(UNB_COMPILE_STAMPS) ] } {
set_parameter -name g_stamp_date [clock format [clock seconds] -format {%Y%m%d}]
set_parameter -name g_stamp_time [clock format [clock seconds] -format {%H%M%S}]
- post_message -type info "RADIOHDL: using SVN revision $::env(RADIOHDL_SVN_REVISION)"
- set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_SVN_REVISION)] ""]
+ post_message -type info "RADIOHDL: using SVN revision $::env(RADIOHDL_GIT_REVISION)"
+ set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_GIT_REVISION)] ""]
}
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf
index 47fbc4afdc..4d46b5409c 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf
+++ b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf
@@ -22,7 +22,7 @@
# This QSF is sourced by other design QSF files.
# ==============================================
# Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
# This file contains includes that should be added to another project QSF before
# user contraints and/or QIPs are added.
@@ -48,13 +48,13 @@ set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCS128
# Timing constraints
-set_global_assignment -name SDC_FILE $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.sdc
+set_global_assignment -name SDC_FILE $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.sdc
# Pass compile stamps as generics (passed to top-level when $UNB_COMPILE_STAMPS is set)
if { [info exists ::env(UNB_COMPILE_STAMPS) ] } {
set_parameter -name g_stamp_date [clock format [clock seconds] -format {%Y%m%d}]
set_parameter -name g_stamp_time [clock format [clock seconds] -format {%H%M%S}]
- post_message -type info "RADIOHDL: using SVN revision $::env(RADIOHDL_SVN_REVISION)"
- set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_SVN_REVISION)] ""]
+ post_message -type info "RADIOHDL: using SVN revision $::env(RADIOHDL_GIT_REVISION)"
+ set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_GIT_REVISION)] ""]
}
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.qsf b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.qsf
index 5504518635..821a28fa2d 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.qsf
+++ b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.qsf
@@ -22,12 +22,12 @@
# This QSF is sourced by other design QSF files.
# ==============================================
# Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
#
# This file contains includes that should be added to another project QSF after certain
# user contraints (DDR3 timing constraints for instance) have been included.
# Post Timing constraints
-set_global_assignment -name SDC_FILE $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.sdc
+set_global_assignment -name SDC_FILE $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.sdc
diff --git a/boards/uniboard2/designs/unb2_led/hdllib.cfg b/boards/uniboard2/designs/unb2_led/hdllib.cfg
index b827bc6b80..31c102a23c 100644
--- a/boards/uniboard2/designs/unb2_led/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_led/hdllib.cfg
@@ -20,10 +20,10 @@ synth_top_level_entity =
quartus_copy_files =
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
quartus_tcl_files =
quartus/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_led/quartus/unb2_minimal_pins.tcl b/boards/uniboard2/designs/unb2_led/quartus/unb2_minimal_pins.tcl
index ac10dfbc4c..23bcf027b1 100644
--- a/boards/uniboard2/designs/unb2_led/quartus/unb2_minimal_pins.tcl
+++ b/boards/uniboard2/designs/unb2_led/quartus/unb2_minimal_pins.tcl
@@ -19,4 +19,4 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_minimal/doc/README b/boards/uniboard2/designs/unb2_minimal/doc/README
index 215cf4e673..d4c4b3ef19 100644
--- a/boards/uniboard2/designs/unb2_minimal/doc/README
+++ b/boards/uniboard2/designs/unb2_minimal/doc/README
@@ -2,17 +2,17 @@ Quick steps to compile and use design [unb2_minimal] in RadionHDL
-----------------------------------------------------------------
-> In case of a new installation, the IP's have to be generated for Arria10.
- In the: $RADIOHDL/libraries/technology/ip_arria10
+ In the: $RADIOHDL_WORK/libraries/technology/ip_arria10
directory; run the bash script: ./generate-all-ip.sh
-> For compilation it might be necessary to check the .vhd file:
- $RADIOHDL/libraries/technology/technology_select_pkg.vhd
+ $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
1. Start with the Oneclick Commands:
- python $RADIOHDL/tools/oneclick/base/modelsim_config.py -t unb2
- python $RADIOHDL/tools/oneclick/base/quartus_config.py -t unb2
+ python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2
+ python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2
2. Generate MMM for QSYS:
@@ -105,7 +105,7 @@ Then program the .JIC file (output_file.jic) to EPCS flash:
- make sure the 4 fpga icons have the device 10AX115U4F45ES
- right-click each fpga icon and attach flash device EPCQL1024
- right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
- (in $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus)
+ (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus)
- right-click each EPCQL1024 and change file from <none> to output_file.jic
- select click each Program/Configure radiobutton
- click start and wait for 'Successful'
diff --git a/boards/uniboard2/designs/unb2_minimal/hdllib.cfg b/boards/uniboard2/designs/unb2_minimal/hdllib.cfg
index 438f691f82..3c8171266d 100644
--- a/boards/uniboard2/designs/unb2_minimal/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_minimal/hdllib.cfg
@@ -23,10 +23,10 @@ quartus_copy_files =
quartus/qsys_unb2_minimal.qsys .
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
quartus_tcl_files =
quartus/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_minimal/quartus/unb2_minimal_pins.tcl b/boards/uniboard2/designs/unb2_minimal/quartus/unb2_minimal_pins.tcl
index ac10dfbc4c..23bcf027b1 100644
--- a/boards/uniboard2/designs/unb2_minimal/quartus/unb2_minimal_pins.tcl
+++ b/boards/uniboard2/designs/unb2_minimal/quartus/unb2_minimal_pins.tcl
@@ -19,4 +19,4 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/doc/README b/boards/uniboard2/designs/unb2_test/doc/README
index 2b843fa451..5c311198c8 100644
--- a/boards/uniboard2/designs/unb2_test/doc/README
+++ b/boards/uniboard2/designs/unb2_test/doc/README
@@ -25,18 +25,18 @@ The following revisions are available for unb2_test (see the directories in ../r
-> In case of a new installation, the IP's have to be generated for Arria10.
- In the: $RADIOHDL/libraries/technology/ip_arria10
+ In the: $RADIOHDL_WORK/libraries/technology/ip_arria10
directory; run the bash script: ./generate-all-ip.sh
-> For compilation it might be necessary to check the .vhd file:
- $RADIOHDL/libraries/technology/technology_select_pkg.vhd
+ $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
1. Start with the Oneclick Commands:
- python $RADIOHDL/tools/oneclick/base/modelsim_config.py -t unb2
- python $RADIOHDL/tools/oneclick/base/quartus_config.py -t unb2
+ python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2
+ python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2
2. Generate MMM for QSYS (select one of these revisions):
@@ -117,7 +117,7 @@ Then program the .JIC file (output_file.jic) to EPCS flash:
- make sure the 4 fpga icons have the device 10AX115U4F45ES
- right-click each fpga icon and attach flash device EPCQL1024
- right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
- (in $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus)
+ (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus)
- right-click each EPCQL1024 and change file from <none> to output_file.jic
- select click each Program/Configure radiobutton
- click start and wait for 'Successful'
diff --git a/boards/uniboard2/designs/unb2_test/quartus/unb2_test_pins.tcl b/boards/uniboard2/designs/unb2_test/quartus/unb2_test_pins.tcl
index a28b05005c..7df88096be 100644
--- a/boards/uniboard2/designs/unb2_test/quartus/unb2_test_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/quartus/unb2_test_pins.tcl
@@ -19,7 +19,7 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_10GbE_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
index 593d274985..2835bf9b43 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
@@ -44,11 +44,11 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
quartus_sdc_files =
quartus/unb2_test_10GbE.sdc
- $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
quartus_tcl_files =
quartus/unb2_test_10GbE_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/quartus/unb2_test_10GbE_pins.tcl b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/quartus/unb2_test_10GbE_pins.tcl
index 1e0d2cdc83..e14bd851bb 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/quartus/unb2_test_10GbE_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/quartus/unb2_test_10GbE_pins.tcl
@@ -19,5 +19,5 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_10GbE_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
index b8c824fe26..a5ce4f51a9 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
quartus_tcl_files =
quartus/unb2_test_1GbE_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/quartus/unb2_test_1GbE_pins.tcl b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/quartus/unb2_test_1GbE_pins.tcl
index ac10dfbc4c..23bcf027b1 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/quartus/unb2_test_1GbE_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/quartus/unb2_test_1GbE_pins.tcl
@@ -19,4 +19,4 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
index ac49ea9924..00625f07eb 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
@@ -49,11 +49,11 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
quartus_sdc_files =
quartus/unb2_test_10GbE.sdc
- $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
quartus_tcl_files =
quartus/unb2_test_all_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/quartus/unb2_test_all_pins.tcl b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/quartus/unb2_test_all_pins.tcl
index e2c6e6d7ae..f979adc2ee 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/quartus/unb2_test_all_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/quartus/unb2_test_all_pins.tcl
@@ -19,6 +19,6 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_10GbE_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
index 1dfd462682..67f20d9e4f 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
@@ -22,7 +22,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
[quartus_project_file]
@@ -33,7 +33,7 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
quartus_qip_files =
$HDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_I/qsys_unb2_test/synthesis/qsys_unb2_test.qip
@@ -42,5 +42,5 @@ quartus_tcl_files =
quartus/unb2_test_ddr_MB_I_pins.tcl
quartus_sdc_files =
- $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/quartus/unb2_test_ddr_MB_I_pins.tcl b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/quartus/unb2_test_ddr_MB_I_pins.tcl
index 83eeedee0b..1830b7b880 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/quartus/unb2_test_ddr_MB_I_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/quartus/unb2_test_ddr_MB_I_pins.tcl
@@ -19,5 +19,5 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
index 328ae2de92..34036c3461 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
@@ -22,7 +22,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
[quartus_project_file]
@@ -33,7 +33,7 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
quartus_qip_files =
$HDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_II/qsys_unb2_test/synthesis/qsys_unb2_test.qip
@@ -42,5 +42,5 @@ quartus_tcl_files =
quartus/unb2_test_ddr_MB_II_pins.tcl
quartus_sdc_files =
- $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/quartus/unb2_test_ddr_MB_II_pins.tcl b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/quartus/unb2_test_ddr_MB_II_pins.tcl
index 83eeedee0b..1830b7b880 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/quartus/unb2_test_ddr_MB_II_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/quartus/unb2_test_ddr_MB_II_pins.tcl
@@ -19,5 +19,5 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
index 302047e4f4..a42629b841 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
@@ -22,7 +22,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
[quartus_project_file]
@@ -33,7 +33,7 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
quartus_qip_files =
$HDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_I_II/qsys_unb2_test/synthesis/qsys_unb2_test.qip
@@ -42,5 +42,5 @@ quartus_tcl_files =
quartus/unb2_test_ddr_MB_I_II_pins.tcl
quartus_sdc_files =
- $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/quartus/unb2_test_ddr_MB_I_II_pins.tcl b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/quartus/unb2_test_ddr_MB_I_II_pins.tcl
index 83eeedee0b..1830b7b880 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/quartus/unb2_test_ddr_MB_I_II_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/quartus/unb2_test_ddr_MB_I_II_pins.tcl
@@ -19,5 +19,5 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
index 0af0858dce..94e14c4340 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
@@ -26,7 +26,7 @@ PACKAGE qsys_unb2_test_pkg IS
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus QSYS builder generated file:
- -- $RADIOHDL/build/unb2/quartus/unb2_test_ddr/qsys_unb2_test/sim/qsys_unb2_test.vhd
+ -- $RADIOHDL_WORK/build/unb2/quartus/unb2_test_ddr/qsys_unb2_test/sim/qsys_unb2_test.vhd
-----------------------------------------------------------------------------
component qsys_unb2_test is
diff --git a/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf b/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
index 577051cd04..072fd6fb68 100644
--- a/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+++ b/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
@@ -22,7 +22,7 @@
# This QSF is sourced by other design QSF files.
# ==============================================
# Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
# Device:
set_global_assignment -name FAMILY "Arria 10"
@@ -107,7 +107,7 @@ set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_1
if { [info exists ::env(UNB_COMPILE_STAMPS) ] } {
set_parameter -name g_stamp_date [clock format [clock seconds] -format {%Y%m%d}]
set_parameter -name g_stamp_time [clock format [clock seconds] -format {%H%M%S}]
- post_message -type info "RADIOHDL: using SVN $::env(RADIOHDL_SVN_REVISION)"
- set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_SVN_REVISION)] ""]
+ post_message -type info "RADIOHDL: using SVN $::env(RADIOHDL_GIT_REVISION)"
+ set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_GIT_REVISION)] ""]
}
diff --git a/boards/uniboard2a/designs/altera_ref_designs/ddr4/doc/README_ddr4.txt b/boards/uniboard2a/designs/altera_ref_designs/ddr4/doc/README_ddr4.txt
index 4a32ab051e..7fd2f086e5 100644
--- a/boards/uniboard2a/designs/altera_ref_designs/ddr4/doc/README_ddr4.txt
+++ b/boards/uniboard2a/designs/altera_ref_designs/ddr4/doc/README_ddr4.txt
@@ -143,7 +143,7 @@ Quartus IP catalog "Arria10 External Memory Interface" fill in:
run:
cd emif_0_example_design
- . ${RADIOHDL}/tools/quartus/set_quartus unb2 && quartus_sh -t make_qii_design.tcl
+ . ${RADIOHDL_GEAR}/quartus/set_quartus unb2 && quartus_sh -t make_qii_design.tcl
add to qii/ed_synth.qsf:
source ../../unb2_pins_ed_synth.tcl
diff --git a/boards/uniboard2a/designs/unb2a_heater/doc/README.txt b/boards/uniboard2a/designs/unb2a_heater/doc/README.txt
index 99553f4ac7..45d88bd21b 100644
--- a/boards/uniboard2a/designs/unb2a_heater/doc/README.txt
+++ b/boards/uniboard2a/designs/unb2a_heater/doc/README.txt
@@ -2,17 +2,17 @@ Quick steps to compile and use design [unb2a_heater] in RadionHDL
------------------------------------------------------------------
-> In case of a new installation, the IP's have to be generated for Arria10.
- In the: $RADIOHDL/libraries/technology/ip_arria10_e3sge3
+ In the: $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3
directory; run the bash script: ./generate-all-ip.sh
-> For compilation it might be necessary to check the .vhd file:
- $RADIOHDL/libraries/technology/technology_select_pkg.vhd
+ $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
1. Start with the Oneclick Commands:
- python $RADIOHDL/tools/oneclick/base/modelsim_config.py -t unb2a
- python $RADIOHDL/tools/oneclick/base/quartus_config.py -t unb2a
+ python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2a
+ python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2a
2. Generate MMM for QSYS:
@@ -107,7 +107,7 @@ Then program the .JIC file (output_file.jic) to EPCS flash:
- make sure the 4 fpga icons have the device 10AX115U4F45ES
- right-click each fpga icon and attach flash device EPCQL1024
- right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
- (in $RADIOHDL/boards/uniboard2/libraries/unb2a_board/quartus)
+ (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2a_board/quartus)
- right-click each EPCQL1024 and change file from <none> to output_file.jic
- select click each Program/Configure radiobutton
- click start and wait for 'Successful'
diff --git a/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg b/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg
index 3a56f16b72..2c8fffa256 100644
--- a/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg
@@ -23,10 +23,10 @@ quartus_copy_files =
quartus/qsys_unb2a_heater.qsys .
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
quartus_tcl_files =
quartus/unb2a_heater_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_heater/quartus/unb2a_heater_pins.tcl b/boards/uniboard2a/designs/unb2a_heater/quartus/unb2a_heater_pins.tcl
index f0e1fcbcc2..3374b678b9 100644
--- a/boards/uniboard2a/designs/unb2a_heater/quartus/unb2a_heater_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_heater/quartus/unb2a_heater_pins.tcl
@@ -19,4 +19,4 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_led/hdllib.cfg b/boards/uniboard2a/designs/unb2a_led/hdllib.cfg
index b02941d9d7..9060d3ba02 100644
--- a/boards/uniboard2a/designs/unb2a_led/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_led/hdllib.cfg
@@ -20,10 +20,10 @@ synth_top_level_entity =
quartus_copy_files =
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
quartus_tcl_files =
quartus/unb2a_minimal_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_led/quartus/unb2a_minimal_pins.tcl b/boards/uniboard2a/designs/unb2a_led/quartus/unb2a_minimal_pins.tcl
index f0e1fcbcc2..3374b678b9 100644
--- a/boards/uniboard2a/designs/unb2a_led/quartus/unb2a_minimal_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_led/quartus/unb2a_minimal_pins.tcl
@@ -19,4 +19,4 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt b/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
index 76b19ccab7..552ed433c5 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
+++ b/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
@@ -2,19 +2,19 @@ Quick steps to compile and use design [unb2a_minimal] in RadionHDL
------------------------------------------------------------------
-> In case of a new installation, the IP's have to be generated for Arria10.
- In the: $RADIOHDL/libraries/technology/ip_arria10_e3sge3
+ In the: $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3
directory; run the bash script: ./generate-all-ip.sh
-> The TSE IP gives a lot of critical warnings. To fix them, run this patch:
- cd $RADIOHDL/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
+ cd $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
./run_patch.sh
-> In case of a fresh compilation, delete the build directory.
- rm -r $RADIOHDL/build
+ rm -r $RADIOHDL_WORK/build
1. Start with the Oneclick Commands:
- python $RADIOHDL/tools/oneclick/base/modelsim_config.py -t unb2a
- python $RADIOHDL/tools/oneclick/base/quartus_config.py -t unb2a
+ python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2a
+ python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2a
2. Generate MMM for QSYS:
@@ -63,7 +63,7 @@ In case of needing the Quartus GUI for inspection (this starts the Quartus 15.1
----------------
Using JTAG: Start the Quartus GUI and open: tools->programmer.
Then click auto-detect; (click 4x ok)
- Use 'change file' to select the correct .sof file (in $RADIOHDL/build/unb2a/quartus/unb2a_minimal) for each FPGA
+ Use 'change file' to select the correct .sof file (in $RADIOHDL_WORK/build/unb2a/quartus/unb2a_minimal) for each FPGA
Select the FPGA(s) which has to be programmed
Click 'start'
Using EPCS: See step 6 below.
@@ -98,7 +98,7 @@ For generating a Factory image .RBF file:
run_rbf unb2a --unb2_factory unb2a_minimal
-The .RBF file is now in $RADIOHDL/build/unb2a/quartus/unb2a_minimal
+The .RBF file is now in $RADIOHDL_WORK/build/unb2a/quartus/unb2a_minimal
Now copy the .RBF file to the LCU host with 'scp'
(b)
@@ -109,7 +109,7 @@ Program User image:
Program Factory image:
python util_epcs.py --unb 1 --fn 0 -n 3 -s unb2a_minimal.rbf
--> For extra info on RBF files on Uniboard2, see: $RADIOHDL/libraries/io/epcs/doc/README.txt
+-> For extra info on RBF files on Uniboard2, see: $RADIOHDL_WORK/libraries/io/epcs/doc/README.txt
To start the User image:
python util_remu.py --unb 1 --fn 0 -n 6 # ignore timeout error
@@ -146,7 +146,7 @@ Then program the .JIC file (unb2a_minimal.jic) to EPCS flash:
(*1) When error select correct SFL (serial flash loader) from Altera service request for each FPGA:
right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
- (in $RADIOHDL/boards/uniboard2/libraries/unb2a_board/quartus)
+ (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2a_board/quartus)
7.
diff --git a/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg b/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg
index ddecca0dea..c569e3b684 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg
@@ -23,10 +23,10 @@ quartus_copy_files =
quartus/qsys_unb2a_minimal.qsys .
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
quartus_tcl_files =
quartus/unb2a_minimal_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_minimal/quartus/unb2a_minimal_pins.tcl b/boards/uniboard2a/designs/unb2a_minimal/quartus/unb2a_minimal_pins.tcl
index f0e1fcbcc2..3374b678b9 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/quartus/unb2a_minimal_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_minimal/quartus/unb2a_minimal_pins.tcl
@@ -19,4 +19,4 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/doc/README.txt b/boards/uniboard2a/designs/unb2a_test/doc/README.txt
index 316b8f22bb..4d8244dfcf 100644
--- a/boards/uniboard2a/designs/unb2a_test/doc/README.txt
+++ b/boards/uniboard2a/designs/unb2a_test/doc/README.txt
@@ -25,17 +25,17 @@ The following revisions are available for unb2a_test (see the directories in ../
-> In case of a new installation, the IP's have to be generated for Arria10.
- In the: $RADIOHDL/libraries/technology/ip_arria10_e3sge3
+ In the: $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3
directory; run the bash script: ./generate-all-ip.sh
-> The TSE IP gives a lot of critical warnings. To fix them, run this patch:
- cd $RADIOHDL/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
+ cd $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
./run_patch.sh
1. Start with the Oneclick Commands:
- python $RADIOHDL/tools/oneclick/base/modelsim_config.py -t unb2a
- python $RADIOHDL/tools/oneclick/base/quartus_config.py -t unb2a
+ python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2a
+ python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2a
2. Generate MMM for QSYS (select one of these revisions):
@@ -80,7 +80,7 @@ load the project now from the build directory.
----------------
Using JTAG: Start the Quartus GUI and open: tools->programmer.
Then click auto-detect; (click 4x ok)
- Use 'change file' to select the correct .sof file (in $RADIOHDL/build/unb2a/quartus/unb2a_test_...) for each FPGA
+ Use 'change file' to select the correct .sof file (in $RADIOHDL_WORK/build/unb2a/quartus/unb2a_test_...) for each FPGA
Select the FPGA(s) which has to be programmed
Click 'start'
Using EPCS: See step 6 below.
@@ -106,7 +106,7 @@ For generating a Factory image .RBF file:
run_rbf unb2a --unb2_factory unb2a_test_[revision]
-The .RBF file is now in $RADIOHDL/build/unb2a/quartus/unb2a_test_[revision]
+The .RBF file is now in $RADIOHDL_WORK/build/unb2a/quartus/unb2a_test_[revision]
Now copy the .RBF file to the LCU host with 'scp'
(b)
@@ -117,7 +117,7 @@ Program User image:
Program Factory image:
python util_epcs.py --unb 1 --fn 0 -n 3 -s unb2a_test_[revision].rbf
--> For extra info on RBF files on Uniboard2, see: $RADIOHDL/libraries/io/epcs/doc/README.txt
+-> For extra info on RBF files on Uniboard2, see: $RADIOHDL_WORK/libraries/io/epcs/doc/README.txt
To start the User image:
python util_remu.py --unb 1 --fn 0 -n 6 # ignore timeout error
@@ -151,7 +151,7 @@ Then program the .JIC file (output_file.jic) to EPCS flash:
(*1) When error select correct SFL (serial flash loader) from Altera service request for each FPGA:
right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
- (in $RADIOHDL/boards/uniboard2/libraries/unb2a_board/quartus)
+ (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2a_board/quartus)
7.
diff --git a/boards/uniboard2a/designs/unb2a_test/quartus/unb2a_test_pins.tcl b/boards/uniboard2a/designs/unb2a_test/quartus/unb2a_test_pins.tcl
index 553162a115..c0483d1585 100644
--- a/boards/uniboard2a/designs/unb2a_test/quartus/unb2a_test_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/quartus/unb2a_test_pins.tcl
@@ -19,7 +19,7 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
index 51f4a2012d..f9c0677edd 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
@@ -44,14 +44,14 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
quartus_sdc_pre_files =
quartus/unb2a_test_10GbE.sdc
- $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board_pre.sdc
+ $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board_pre.sdc
quartus_sdc_files =
- $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
quartus_tcl_files =
quartus/unb2a_test_10GbE_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/quartus/unb2a_test_10GbE_pins.tcl b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/quartus/unb2a_test_10GbE_pins.tcl
index 9f0f3d463e..7e83e4b07c 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/quartus/unb2a_test_10GbE_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/quartus/unb2a_test_10GbE_pins.tcl
@@ -19,5 +19,5 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
index 088553ae79..cbc5c0292e 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
quartus_tcl_files =
quartus/unb2a_test_1GbE_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/quartus/unb2a_test_1GbE_pins.tcl b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/quartus/unb2a_test_1GbE_pins.tcl
index f0e1fcbcc2..3374b678b9 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/quartus/unb2a_test_1GbE_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/quartus/unb2a_test_1GbE_pins.tcl
@@ -19,4 +19,4 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
index 7e6963de8f..68466090d0 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
@@ -50,11 +50,11 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
quartus_sdc_files =
quartus/unb2a_test_10GbE.sdc
- $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
quartus_tcl_files =
quartus/unb2a_test_all_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/quartus/unb2a_test_all_pins.tcl b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/quartus/unb2a_test_all_pins.tcl
index e49fd3d11a..91f930b06b 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/quartus/unb2a_test_all_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/quartus/unb2a_test_all_pins.tcl
@@ -19,6 +19,6 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
index fc2357bf49..a7a4643277 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
@@ -23,7 +23,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
[quartus_project_file]
@@ -34,7 +34,7 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
quartus_qip_files =
$HDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_I/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
@@ -43,5 +43,5 @@ quartus_tcl_files =
quartus/unb2a_test_ddr_MB_I_pins.tcl
quartus_sdc_files =
- $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/quartus/unb2a_test_ddr_MB_I_pins.tcl b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/quartus/unb2a_test_ddr_MB_I_pins.tcl
index c95abcfa28..edf1e7422d 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/quartus/unb2a_test_ddr_MB_I_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/quartus/unb2a_test_ddr_MB_I_pins.tcl
@@ -19,5 +19,5 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
index 2859b2ec94..4030938bac 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
@@ -23,7 +23,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
[quartus_project_file]
@@ -34,7 +34,7 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
quartus_qip_files =
$HDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_II/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
@@ -43,5 +43,5 @@ quartus_tcl_files =
quartus/unb2a_test_ddr_MB_II_pins.tcl
quartus_sdc_files =
- $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/quartus/unb2a_test_ddr_MB_II_pins.tcl b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/quartus/unb2a_test_ddr_MB_II_pins.tcl
index c95abcfa28..edf1e7422d 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/quartus/unb2a_test_ddr_MB_II_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/quartus/unb2a_test_ddr_MB_II_pins.tcl
@@ -19,5 +19,5 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
index b80f43f075..8b25ef236f 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
@@ -23,7 +23,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
[quartus_project_file]
@@ -34,7 +34,7 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
quartus_qip_files =
$HDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_I_II/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
@@ -43,5 +43,5 @@ quartus_tcl_files =
quartus/unb2a_test_ddr_MB_I_II_pins.tcl
quartus_sdc_files =
- $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/quartus/unb2a_test_ddr_MB_I_II_pins.tcl b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/quartus/unb2a_test_ddr_MB_I_II_pins.tcl
index c95abcfa28..edf1e7422d 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/quartus/unb2a_test_ddr_MB_I_II_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/quartus/unb2a_test_ddr_MB_I_II_pins.tcl
@@ -19,5 +19,5 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
index f154ef668e..2f6c0284ea 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
@@ -26,7 +26,7 @@ PACKAGE qsys_unb2a_test_pkg IS
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus QSYS builder generated file:
- -- $RADIOHDL/build/unb2a/quartus/unb2a_test_ddr/qsys_unb2a_test/sim/qsys_unb2a_test.vhd
+ -- $RADIOHDL_WORK/build/unb2a/quartus/unb2a_test_ddr/qsys_unb2a_test/sim/qsys_unb2a_test.vhd
-----------------------------------------------------------------------------
component qsys_unb2a_test is
diff --git a/boards/uniboard2a/doc/unb2a_release_notes.txt b/boards/uniboard2a/doc/unb2a_release_notes.txt
index d2b4fc4198..18a1851942 100644
--- a/boards/uniboard2a/doc/unb2a_release_notes.txt
+++ b/boards/uniboard2a/doc/unb2a_release_notes.txt
@@ -10,15 +10,15 @@ Date: Tue Apr 26 11:25:24 CEST 2016
This means that the firmware already flashed still shows a Uniboard 1 version in the python scripts.
-> So it will be good to re-flash unb2a_minimal.
The new .rbf file (factory image) is added in the build directory and the excisting .jic file is removed.
- Look at $RADIOHDL/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt Section 6b how to flash
- Also see $RADIOHDL/boards/uniboard2a/designs/unb2a_minimal/build/README.txt
+ Look at $RADIOHDL_WORK/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt Section 6b how to flash
+ Also see $RADIOHDL_WORK/boards/uniboard2a/designs/unb2a_minimal/build/README.txt
Date: Mon Apr 25 11:29:31 CEST 2016
- Added functionality to write to EPCQ flash.
Now it is possible to write a Factory- and User image
- See $RADIOHDL/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
+ See $RADIOHDL_WORK/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
for instructions how to prepare images and how to write them in the flash
- Added functionality to perform Load from Flash with the REMU (remote update)
@@ -32,15 +32,15 @@ In this directory the following designs can be found:
- unb2a_minimal
a minimal design which is also programmed in the onboard EPCS flash.
- See: $RADIOHDL/boards/uniboard2a/designs/unb2a_minimal/doc/ASTRON_unb2a_minimal.pdf
- $RADIOHDL/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
+ See: $RADIOHDL_WORK/boards/uniboard2a/designs/unb2a_minimal/doc/ASTRON_unb2a_minimal.pdf
+ $RADIOHDL_WORK/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
- unb2_test
a test design with revisions testing each subsystem. Currently only the DDR4.
- See: $RADIOHDL/boards/uniboard2a/designs/unb2a_test/doc/README.txt
+ See: $RADIOHDL_WORK/boards/uniboard2a/designs/unb2a_test/doc/README.txt
@@ -49,7 +49,7 @@ In this directory the following designs can be found:
an Altera reference design originally downloaded from
www.alterawiki.com/wiki/High_Speed_Transceiver_Demo_Designs_For_Current_and_Older_Families
- See: $RADIOHDL/boards/uniboard2a/designs/altera_ref_designs/Arria10_SIBoard_24Ch_3_Phy_TTK_ES3/doc/*
+ See: $RADIOHDL_WORK/boards/uniboard2a/designs/altera_ref_designs/Arria10_SIBoard_24Ch_3_Phy_TTK_ES3/doc/*
@@ -58,9 +58,9 @@ In this directory the following designs can be found:
ddr4_micron46_mbIIskew
based on Altera's reference design, autogenerated from the QSYS IP-catalog in Quartus
- See: $RADIOHDL/boards/uniboard2a/designs/altera_ref_designs/ddr4/doc/*
- $RADIOHDL/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/README.txt
- $RADIOHDL/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/README.txt
+ See: $RADIOHDL_WORK/boards/uniboard2a/designs/altera_ref_designs/ddr4/doc/*
+ $RADIOHDL_WORK/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/README.txt
+ $RADIOHDL_WORK/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/README.txt
diff --git a/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf b/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
index bef3dcdee8..422aa619aa 100644
--- a/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+++ b/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
@@ -22,7 +22,7 @@
# This QSF is sourced by other design QSF files.
# ==============================================
# Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
# new in Quartus 16.0:
set_global_assignment -name NUM_PARALLEL_PROCESSORS 6
@@ -311,8 +311,8 @@ set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_1
if { [info exists ::env(UNB_COMPILE_STAMPS) ] } {
set_parameter -name g_stamp_date [clock format [clock seconds] -format {%Y%m%d}]
set_parameter -name g_stamp_time [clock format [clock seconds] -format {%H%M%S}]
- post_message -type info "RADIOHDL: using SVN $::env(RADIOHDL_SVN_REVISION)"
- set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_SVN_REVISION)] ""]
+ post_message -type info "RADIOHDL: using SVN $::env(RADIOHDL_GIT_REVISION)"
+ set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_GIT_REVISION)] ""]
}
#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "ctrl_unb2_board:u_ctrl|eth:\\gen_eth:u_eth|tech_tse:u_tech_tse|tech_tse_arria10_e3sge3:\\gen_ip_arria10_e3sge3:u0|ip_arria10_e3sge3_tse_sgmii_lvds:\\u_LVDS_tse:u_tse|ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_151_6kz2wlq:eth_tse_0|altera_eth_tse_pcs_pma_nf_lvds:i_tse_pcs_0|tbi_tx_d"
diff --git a/boards/uniboard2b/designs/unb2b_heater/doc/README.txt b/boards/uniboard2b/designs/unb2b_heater/doc/README.txt
index f61d49015e..4958c61efd 100644
--- a/boards/uniboard2b/designs/unb2b_heater/doc/README.txt
+++ b/boards/uniboard2b/designs/unb2b_heater/doc/README.txt
@@ -2,17 +2,17 @@ Quick steps to compile and use design [unb2a_heater] in RadionHDL
------------------------------------------------------------------
-> In case of a new installation, the IP's have to be generated for Arria10.
- In the: $RADIOHDL/libraries/technology/ip_arria10_e1sg
+ In the: $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg
directory; run the bash script: ./generate-all-ip.sh
-> For compilation it might be necessary to check the .vhd file:
- $RADIOHDL/libraries/technology/technology_select_pkg.vhd
+ $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
1. Start with the Oneclick Commands:
- python $RADIOHDL/tools/oneclick/base/modelsim_config.py -t unb2b
- python $RADIOHDL/tools/oneclick/base/quartus_config.py -t unb2b
+ python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2b
+ python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2b
2. Generate MMM for QSYS:
@@ -107,7 +107,7 @@ Then program the .JIC file (output_file.jic) to EPCS flash:
- make sure the 4 fpga icons have the device 10AX115U4F45ES
- right-click each fpga icon and attach flash device EPCQL1024
- right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
- (in $RADIOHDL/boards/uniboard2/libraries/unb2a_board/quartus)
+ (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2a_board/quartus)
- right-click each EPCQL1024 and change file from <none> to output_file.jic
- select click each Program/Configure radiobutton
- click start and wait for 'Successful'
diff --git a/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg b/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg
index 3d95d14a8b..73def4af46 100644
--- a/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg
@@ -23,10 +23,10 @@ quartus_copy_files =
quartus .
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
quartus/unb2b_heater_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_heater/quartus/unb2b_heater_pins.tcl b/boards/uniboard2b/designs/unb2b_heater/quartus/unb2b_heater_pins.tcl
index c2fd8f90e4..ba69570cfa 100644
--- a/boards/uniboard2b/designs/unb2b_heater/quartus/unb2b_heater_pins.tcl
+++ b/boards/uniboard2b/designs/unb2b_heater/quartus/unb2b_heater_pins.tcl
@@ -18,4 +18,4 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_minimal/doc/README b/boards/uniboard2b/designs/unb2b_minimal/doc/README
index 7b4783fb2a..1c12d1247f 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/doc/README
+++ b/boards/uniboard2b/designs/unb2b_minimal/doc/README
@@ -5,19 +5,19 @@ On uni-boards 26287-001..26287-005 (unb2b) the used FPGA is '10AX115U2F45E1SG'
-> In case of a new installation, the IP's have to be generated for Arria10.
- In the: $RADIOHDL/libraries/technology/ip_arria10
+ In the: $RADIOHDL_WORK/libraries/technology/ip_arria10
directory; run the bash script: ./generate-all-ip.sh
-> For compilation it might be necessary to check the .vhd file:
- $RADIOHDL/libraries/technology/technology_select_pkg.vhd
+ $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
-> Make sure you have set up the RadioHDL/trunk/tools/quartus/set_quartus script correctly to use quartus 17 for unb2b.
-> Make sure you use the modified avs2_eth_coe_hw.tcl (see attachment of this e-mail), this file is placed in RadioHDL/trunk/libraries/io/eth/src/vhdl.
1. Start with the Oneclick Commands:
- python $RADIOHDL/tools/oneclick/base/modelsim_config.py -t unb2b
- python $RADIOHDL/tools/oneclick/base/quartus_config.py -t unb2b
+ python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2b
+ python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2b
# 2. Generate MMM for QSYS:
# run_qsys unb2b unb2b_minimal
@@ -59,7 +59,7 @@ Synthesis
- Open the unb2b_minumal quartus project from the build directory.
- Open the qsys_unb2b_minimal.qsys file from the build directory.
- Generate the HDL files for the qsys using the GUI.
-- "cd $RADIOHDL/build/unb2b/quartus/unb2b_minimal"
+- "cd $RADIOHDL_WORK/build/unb2b/quartus/unb2b_minimal"
- "cp qsys_unb2b_minimal/qsys_unb2b_minimal* ."
- "run_app unb2b unb2b_minimal use=gen2"
- In Quartus, click the play button to compile the design.
diff --git a/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg b/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
index 68528b77d7..213b715445 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
quartus .
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
quartus/unb2b_minimal_pins.tcl
@@ -37,3 +37,6 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/qsys_unb2b_minimal/qsys_unb2b_minimal.qip
+nios2_app_userflags =
+ "use=gen2"
+
diff --git a/boards/uniboard2b/designs/unb2b_minimal/quartus/unb2b_minimal_pins.tcl b/boards/uniboard2b/designs/unb2b_minimal/quartus/unb2b_minimal_pins.tcl
index f0e1fcbcc2..3374b678b9 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/quartus/unb2b_minimal_pins.tcl
+++ b/boards/uniboard2b/designs/unb2b_minimal/quartus/unb2b_minimal_pins.tcl
@@ -19,4 +19,4 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_test/doc/README.txt b/boards/uniboard2b/designs/unb2b_test/doc/README.txt
index 8c667b071b..7dbf819843 100644
--- a/boards/uniboard2b/designs/unb2b_test/doc/README.txt
+++ b/boards/uniboard2b/designs/unb2b_test/doc/README.txt
@@ -25,17 +25,17 @@ The following revisions are available for unb2b_test (see the directories in ../
-> In case of a new installation, the IP's have to be generated for Arria10.
- In the: $RADIOHDL/libraries/technology/ip_arria10_e1sg
+ In the: $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg
directory; run the bash script: ./generate-all-ip.sh
-> The TSE IP gives a lot of critical warnings. To fix them, run this patch:
- cd $RADIOHDL/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds
+ cd $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds
./run_patch.sh
1. Start with the Oneclick Commands:
- python $RADIOHDL/tools/oneclick/base/modelsim_config.py -t unb2b
- python $RADIOHDL/tools/oneclick/base/quartus_config.py -t unb2b
+ python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2b
+ python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2b
2. Generate MMM for QSYS (select one of these revisions):
@@ -80,7 +80,7 @@ load the project now from the build directory.
----------------
Using JTAG: Start the Quartus GUI and open: tools->programmer.
Then click auto-detect; (click 4x ok)
- Use 'change file' to select the correct .sof file (in $RADIOHDL/build/unb2b/quartus/unb2b_test_...) for each FPGA
+ Use 'change file' to select the correct .sof file (in $RADIOHDL_WORK/build/unb2b/quartus/unb2b_test_...) for each FPGA
Select the FPGA(s) which has to be programmed
Click 'start'
Using EPCS: See step 6 below.
@@ -106,7 +106,7 @@ For generating a Factory image .RBF file:
run_rbf unb2b --unb2_factory unb2b_test_[revision]
-The .RBF file is now in $RADIOHDL/build/unb2b/quartus/unb2b_test_[revision]
+The .RBF file is now in $RADIOHDL_WORK/build/unb2b/quartus/unb2b_test_[revision]
Now copy the .RBF file to the LCU host with 'scp'
(b)
@@ -117,7 +117,7 @@ Program User image:
Program Factory image:
python util_epcs.py --unb 1 --fn 0 -n 3 -s unb2b_test_[revision].rbf
--> For extra info on RBF files on Uniboard2, see: $RADIOHDL/libraries/io/epcs/doc/README.txt
+-> For extra info on RBF files on Uniboard2, see: $RADIOHDL_WORK/libraries/io/epcs/doc/README.txt
To start the User image:
python util_remu.py --unb 1 --fn 0 -n 6 # ignore timeout error
@@ -151,7 +151,7 @@ Then program the .JIC file (output_file.jic) to EPCS flash:
(*1) When error select correct SFL (serial flash loader) from Altera service request for each FPGA:
right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
- (in $RADIOHDL/boards/uniboard2/libraries/unb2b_board/quartus)
+ (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2b_board/quartus)
7.
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/unb2b_test_pins.tcl b/boards/uniboard2b/designs/unb2b_test/quartus/unb2b_test_pins.tcl
index 553162a115..c0483d1585 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/unb2b_test_pins.tcl
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/unb2b_test_pins.tcl
@@ -19,7 +19,7 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg
index 33ad1deec5..8d7faee81b 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg
@@ -45,14 +45,14 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
quartus_sdc_pre_files =
quartus/unb2b_test_10GbE.sdc
- $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board_pre.sdc
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board_pre.sdc
quartus_sdc_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
quartus/unb2b_test_10GbE_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/quartus/unb2b_test_10GbE_pins.tcl b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/quartus/unb2b_test_10GbE_pins.tcl
index 9f0f3d463e..7e83e4b07c 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/quartus/unb2b_test_10GbE_pins.tcl
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/quartus/unb2b_test_10GbE_pins.tcl
@@ -19,5 +19,5 @@
#
###############################################################################
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
index e9c7328a33..d6154e79bb 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
@@ -26,7 +26,7 @@ PACKAGE qsys_unb2b_test_pkg IS
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus QSYS builder generated file:
- -- $RADIOHDL/build/unb2b/quartus/unb2b_test_ddr/qsys_unb2b_test/sim/qsys_unb2b_test.vhd
+ -- $RADIOHDL_WORK/build/unb2b/quartus/unb2b_test_ddr/qsys_unb2b_test/sim/qsys_unb2b_test.vhd
-----------------------------------------------------------------------------
component qsys_unb2b_test is
diff --git a/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf b/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
index 7a372076f5..3b4085e313 100644
--- a/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+++ b/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
@@ -22,7 +22,7 @@
# This QSF is sourced by other design QSF files.
# ==============================================
# Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
# new in Quartus 16.0:
set_global_assignment -name NUM_PARALLEL_PROCESSORS 6
@@ -311,8 +311,8 @@ set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_1
if { [info exists ::env(UNB_COMPILE_STAMPS) ] } {
set_parameter -name g_stamp_date [clock format [clock seconds] -format {%Y%m%d}]
set_parameter -name g_stamp_time [clock format [clock seconds] -format {%H%M%S}]
- post_message -type info "RADIOHDL: using SVN $::env(RADIOHDL_SVN_REVISION)"
- set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_SVN_REVISION)] ""]
+ post_message -type info "RADIOHDL: using GIT $::env(RADIOHDL_GIT_REVISION)"
+ set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_GIT_REVISION)] ""]
}
#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "ctrl_unb2_board:u_ctrl|eth:\\gen_eth:u_eth|tech_tse:u_tech_tse|tech_tse_arria10_e1sg:\\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_tse_sgmii_lvds:\\u_LVDS_tse:u_tse|ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_151_6kz2wlq:eth_tse_0|altera_eth_tse_pcs_pma_nf_lvds:i_tse_pcs_0|tbi_tx_d"
diff --git a/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg b/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg
index 4e1c6925ab..94b17e0841 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg
+++ b/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg
@@ -26,8 +26,8 @@ quartus_copy_files =
src/hex hex
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.qsf
quartus_tcl_files =
quartus/unb1_dp_offload_pins.tcl
diff --git a/libraries/base/reorder/hdllib.cfg b/libraries/base/reorder/hdllib.cfg
index c1357b093d..445fd783dd 100644
--- a/libraries/base/reorder/hdllib.cfg
+++ b/libraries/base/reorder/hdllib.cfg
@@ -41,7 +41,7 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
[quartus_project_file]
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg b/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg
index 3e3089912f..b7626df359 100644
--- a/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg
@@ -24,7 +24,7 @@ synth_top_level_entity =
quartus_copy_files = quartus/sopc_unb1_fn_bf.sopc .
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_tcl_files =
quartus/unb1_fn_bf_constraints.tcl
diff --git a/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg b/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg
index b59f6067a5..be1afe4a89 100644
--- a/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg
+++ b/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg
@@ -23,7 +23,7 @@ quartus_copy_files =
quartus/qsys_unb1_correlator.qsys .
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_tcl_files =
quartus/unb1_correlator_pins.tcl
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd b/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd
index ec43153207..896a25a6ad 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd
@@ -266,7 +266,7 @@ BEGIN
g_sim => TRUE,
g_pass_through => FALSE,
g_rec_not_play => TRUE,
- g_rec_play_file => "$RADIOHDL/libraries/dsp/correlator/tb/rec/correlator_src_out_arr0.rec",
+ g_rec_play_file => "$RADIOHDL_WORK/libraries/dsp/correlator/tb/rec/correlator_src_out_arr0.rec",
g_record_invalid => FALSE
)
PORT MAP (
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd
index 7d07ce044c..35a6684bc3 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd
@@ -26,7 +26,7 @@
-- The g_data_file with input and expected output data is created by the
-- Matlab script:
--
--- $RADIOHDL/applications/apertif/matlab/run_pfft.m
+-- $RADIOHDL_WORK/applications/apertif/matlab/run_pfft.m
--
-- yields:
--
diff --git a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd
index 7f36136eea..6c155ee41d 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd
@@ -22,7 +22,7 @@
-- Purpose: Multi-testbench for fft_r2_par using file data
-- Description:
-- Verify fft_r2_par using and data generated by Matlab
--- $RADIOHDL/applications/apertif/matlab/run_pfft.m
+-- $RADIOHDL_WORK/applications/apertif/matlab/run_pfft.m
--
-- Usage:
-- > as 4
diff --git a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd
index 485c3d11fe..3efd0d0917 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd
@@ -22,7 +22,7 @@
-- Purpose: Multi-testbench for fft_r2_pipe using file data
-- Description:
-- Verify fft_r2_pipe using and data generated by Matlab
--- $RADIOHDL/applications/apertif/matlab/run_pfft.m
+-- $RADIOHDL_WORK/applications/apertif/matlab/run_pfft.m
--
-- Usage:
-- > as 4
diff --git a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd
index ab34ea103d..9c2132abc6 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd
@@ -23,8 +23,8 @@
-- Description:
-- Verify fft_r2_wide using and data generated by Matlab scripts:
--
--- - $RADIOHDL/applications/apertif/matlab/run_pfft.m
--- - $RADIOHDL/applications/apertif/matlab/run_pfft_complex.m
+-- - $RADIOHDL_WORK/applications/apertif/matlab/run_pfft.m
+-- - $RADIOHDL_WORK/applications/apertif/matlab/run_pfft_complex.m
--
-- Usage:
-- > as 4
diff --git a/libraries/dsp/filter/src/python/diff_lofar_coefs b/libraries/dsp/filter/src/python/diff_lofar_coefs
index 1a0a6070fe..529bf5381f 100755
--- a/libraries/dsp/filter/src/python/diff_lofar_coefs
+++ b/libraries/dsp/filter/src/python/diff_lofar_coefs
@@ -31,81 +31,81 @@
# the subband statistics will not peak low to 0 dB.
echo "1) Check that copies of LOFAR FIR coefficient reference files are equal"
-diff $RADIOHDL/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $UPE_GEAR/apps/commissioning_apertif_beamformer/coeffs16384Kaiser-quant.dat
-diff $RADIOHDL/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $UNB/Firmware/modules/Lofar/pfs/src/data/Coeffs16384Kaiser-quant.dat
-diff $RADIOHDL/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $RADIOHDL/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-withdc.dat
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $UPE_GEAR/apps/commissioning_apertif_beamformer/coeffs16384Kaiser-quant.dat
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $UNB/Firmware/modules/Lofar/pfs/src/data/Coeffs16384Kaiser-quant.dat
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-withdc.dat
-diff $RADIOHDL/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-nodc.dat $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_no_dc_lofar_subband_16taps_1024points_16b.dat
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-nodc.dat $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_no_dc_lofar_subband_16taps_1024points_16b.dat
echo "2) Check that the local stored LOFAR FIR coefficients mif files are the same as in apertif_unb1_bn_filterbank"
-cd $RADIOHDL/libraries/dsp/filter/src/hex
-diff coefs_wide4_p1024_t16_0.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_0.mif
-diff coefs_wide4_p1024_t16_1.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_1.mif
-diff coefs_wide4_p1024_t16_2.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_2.mif
-diff coefs_wide4_p1024_t16_3.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_3.mif
-diff coefs_wide4_p1024_t16_4.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_4.mif
-diff coefs_wide4_p1024_t16_5.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_5.mif
-diff coefs_wide4_p1024_t16_6.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_6.mif
-diff coefs_wide4_p1024_t16_7.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_7.mif
-diff coefs_wide4_p1024_t16_8.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_8.mif
-diff coefs_wide4_p1024_t16_9.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_9.mif
-diff coefs_wide4_p1024_t16_10.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_10.mif
-diff coefs_wide4_p1024_t16_11.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_11.mif
-diff coefs_wide4_p1024_t16_12.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_12.mif
-diff coefs_wide4_p1024_t16_13.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_13.mif
-diff coefs_wide4_p1024_t16_14.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_14.mif
-diff coefs_wide4_p1024_t16_15.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_15.mif
-diff coefs_wide4_p1024_t16_16.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_16.mif
-diff coefs_wide4_p1024_t16_17.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_17.mif
-diff coefs_wide4_p1024_t16_18.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_18.mif
-diff coefs_wide4_p1024_t16_19.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_19.mif
-diff coefs_wide4_p1024_t16_20.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_20.mif
-diff coefs_wide4_p1024_t16_21.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_21.mif
-diff coefs_wide4_p1024_t16_22.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_22.mif
-diff coefs_wide4_p1024_t16_23.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_23.mif
-diff coefs_wide4_p1024_t16_24.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_24.mif
-diff coefs_wide4_p1024_t16_25.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_25.mif
-diff coefs_wide4_p1024_t16_26.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_26.mif
-diff coefs_wide4_p1024_t16_27.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_27.mif
-diff coefs_wide4_p1024_t16_28.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_28.mif
-diff coefs_wide4_p1024_t16_29.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_29.mif
-diff coefs_wide4_p1024_t16_30.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_30.mif
-diff coefs_wide4_p1024_t16_31.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_31.mif
-diff coefs_wide4_p1024_t16_32.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_32.mif
-diff coefs_wide4_p1024_t16_33.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_33.mif
-diff coefs_wide4_p1024_t16_34.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_34.mif
-diff coefs_wide4_p1024_t16_35.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_35.mif
-diff coefs_wide4_p1024_t16_36.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_36.mif
-diff coefs_wide4_p1024_t16_37.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_37.mif
-diff coefs_wide4_p1024_t16_38.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_38.mif
-diff coefs_wide4_p1024_t16_39.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_39.mif
-diff coefs_wide4_p1024_t16_40.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_40.mif
-diff coefs_wide4_p1024_t16_41.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_41.mif
-diff coefs_wide4_p1024_t16_42.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_42.mif
-diff coefs_wide4_p1024_t16_43.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_43.mif
-diff coefs_wide4_p1024_t16_44.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_44.mif
-diff coefs_wide4_p1024_t16_45.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_45.mif
-diff coefs_wide4_p1024_t16_46.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_46.mif
-diff coefs_wide4_p1024_t16_47.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_47.mif
-diff coefs_wide4_p1024_t16_48.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_48.mif
-diff coefs_wide4_p1024_t16_49.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_49.mif
-diff coefs_wide4_p1024_t16_50.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_50.mif
-diff coefs_wide4_p1024_t16_51.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_51.mif
-diff coefs_wide4_p1024_t16_52.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_52.mif
-diff coefs_wide4_p1024_t16_53.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_53.mif
-diff coefs_wide4_p1024_t16_54.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_54.mif
-diff coefs_wide4_p1024_t16_55.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_55.mif
-diff coefs_wide4_p1024_t16_56.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_56.mif
-diff coefs_wide4_p1024_t16_57.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_57.mif
-diff coefs_wide4_p1024_t16_58.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_58.mif
-diff coefs_wide4_p1024_t16_59.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_59.mif
-diff coefs_wide4_p1024_t16_60.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_60.mif
-diff coefs_wide4_p1024_t16_61.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_61.mif
-diff coefs_wide4_p1024_t16_62.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_62.mif
-diff coefs_wide4_p1024_t16_63.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_63.mif
+cd $RADIOHDL_WORK/libraries/dsp/filter/src/hex
+diff coefs_wide4_p1024_t16_0.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_0.mif
+diff coefs_wide4_p1024_t16_1.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_1.mif
+diff coefs_wide4_p1024_t16_2.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_2.mif
+diff coefs_wide4_p1024_t16_3.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_3.mif
+diff coefs_wide4_p1024_t16_4.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_4.mif
+diff coefs_wide4_p1024_t16_5.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_5.mif
+diff coefs_wide4_p1024_t16_6.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_6.mif
+diff coefs_wide4_p1024_t16_7.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_7.mif
+diff coefs_wide4_p1024_t16_8.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_8.mif
+diff coefs_wide4_p1024_t16_9.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_9.mif
+diff coefs_wide4_p1024_t16_10.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_10.mif
+diff coefs_wide4_p1024_t16_11.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_11.mif
+diff coefs_wide4_p1024_t16_12.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_12.mif
+diff coefs_wide4_p1024_t16_13.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_13.mif
+diff coefs_wide4_p1024_t16_14.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_14.mif
+diff coefs_wide4_p1024_t16_15.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_15.mif
+diff coefs_wide4_p1024_t16_16.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_16.mif
+diff coefs_wide4_p1024_t16_17.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_17.mif
+diff coefs_wide4_p1024_t16_18.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_18.mif
+diff coefs_wide4_p1024_t16_19.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_19.mif
+diff coefs_wide4_p1024_t16_20.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_20.mif
+diff coefs_wide4_p1024_t16_21.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_21.mif
+diff coefs_wide4_p1024_t16_22.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_22.mif
+diff coefs_wide4_p1024_t16_23.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_23.mif
+diff coefs_wide4_p1024_t16_24.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_24.mif
+diff coefs_wide4_p1024_t16_25.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_25.mif
+diff coefs_wide4_p1024_t16_26.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_26.mif
+diff coefs_wide4_p1024_t16_27.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_27.mif
+diff coefs_wide4_p1024_t16_28.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_28.mif
+diff coefs_wide4_p1024_t16_29.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_29.mif
+diff coefs_wide4_p1024_t16_30.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_30.mif
+diff coefs_wide4_p1024_t16_31.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_31.mif
+diff coefs_wide4_p1024_t16_32.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_32.mif
+diff coefs_wide4_p1024_t16_33.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_33.mif
+diff coefs_wide4_p1024_t16_34.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_34.mif
+diff coefs_wide4_p1024_t16_35.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_35.mif
+diff coefs_wide4_p1024_t16_36.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_36.mif
+diff coefs_wide4_p1024_t16_37.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_37.mif
+diff coefs_wide4_p1024_t16_38.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_38.mif
+diff coefs_wide4_p1024_t16_39.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_39.mif
+diff coefs_wide4_p1024_t16_40.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_40.mif
+diff coefs_wide4_p1024_t16_41.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_41.mif
+diff coefs_wide4_p1024_t16_42.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_42.mif
+diff coefs_wide4_p1024_t16_43.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_43.mif
+diff coefs_wide4_p1024_t16_44.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_44.mif
+diff coefs_wide4_p1024_t16_45.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_45.mif
+diff coefs_wide4_p1024_t16_46.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_46.mif
+diff coefs_wide4_p1024_t16_47.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_47.mif
+diff coefs_wide4_p1024_t16_48.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_48.mif
+diff coefs_wide4_p1024_t16_49.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_49.mif
+diff coefs_wide4_p1024_t16_50.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_50.mif
+diff coefs_wide4_p1024_t16_51.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_51.mif
+diff coefs_wide4_p1024_t16_52.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_52.mif
+diff coefs_wide4_p1024_t16_53.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_53.mif
+diff coefs_wide4_p1024_t16_54.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_54.mif
+diff coefs_wide4_p1024_t16_55.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_55.mif
+diff coefs_wide4_p1024_t16_56.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_56.mif
+diff coefs_wide4_p1024_t16_57.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_57.mif
+diff coefs_wide4_p1024_t16_58.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_58.mif
+diff coefs_wide4_p1024_t16_59.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_59.mif
+diff coefs_wide4_p1024_t16_60.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_60.mif
+diff coefs_wide4_p1024_t16_61.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_61.mif
+diff coefs_wide4_p1024_t16_62.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_62.mif
+diff coefs_wide4_p1024_t16_63.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_63.mif
echo "3) Verify that the created reference LOFAR FIR coefficients mif files are equal to the local stored mif files"
-cd $RADIOHDL/libraries/dsp/filter/src/hex
+cd $RADIOHDL_WORK/libraries/dsp/filter/src/hex
diff Coeffs16384Kaiser-quant_4wb_0.mif coefs_wide4_p1024_t16_0.mif
diff Coeffs16384Kaiser-quant_4wb_1.mif coefs_wide4_p1024_t16_1.mif
diff Coeffs16384Kaiser-quant_4wb_2.mif coefs_wide4_p1024_t16_2.mif
@@ -172,142 +172,142 @@ diff Coeffs16384Kaiser-quant_4wb_62.mif coefs_wide4_p1024_t16_62.mif
diff Coeffs16384Kaiser-quant_4wb_63.mif coefs_wide4_p1024_t16_63.mif
echo "4) Verify that the created reference LOFAR FIR coefficients mif files are equal to the mif files stored at apertif_unb1_bn_filterbank"
-cd $RADIOHDL/libraries/dsp/filter/src/hex
-diff Coeffs16384Kaiser-quant_4wb_0.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_0.mif
-diff Coeffs16384Kaiser-quant_4wb_1.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_1.mif
-diff Coeffs16384Kaiser-quant_4wb_2.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_2.mif
-diff Coeffs16384Kaiser-quant_4wb_3.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_3.mif
-diff Coeffs16384Kaiser-quant_4wb_4.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_4.mif
-diff Coeffs16384Kaiser-quant_4wb_5.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_5.mif
-diff Coeffs16384Kaiser-quant_4wb_6.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_6.mif
-diff Coeffs16384Kaiser-quant_4wb_7.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_7.mif
-diff Coeffs16384Kaiser-quant_4wb_8.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_8.mif
-diff Coeffs16384Kaiser-quant_4wb_9.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_9.mif
-diff Coeffs16384Kaiser-quant_4wb_10.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_10.mif
-diff Coeffs16384Kaiser-quant_4wb_11.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_11.mif
-diff Coeffs16384Kaiser-quant_4wb_12.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_12.mif
-diff Coeffs16384Kaiser-quant_4wb_13.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_13.mif
-diff Coeffs16384Kaiser-quant_4wb_14.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_14.mif
-diff Coeffs16384Kaiser-quant_4wb_15.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_15.mif
-diff Coeffs16384Kaiser-quant_4wb_16.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_16.mif
-diff Coeffs16384Kaiser-quant_4wb_17.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_17.mif
-diff Coeffs16384Kaiser-quant_4wb_18.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_18.mif
-diff Coeffs16384Kaiser-quant_4wb_19.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_19.mif
-diff Coeffs16384Kaiser-quant_4wb_20.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_20.mif
-diff Coeffs16384Kaiser-quant_4wb_21.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_21.mif
-diff Coeffs16384Kaiser-quant_4wb_22.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_22.mif
-diff Coeffs16384Kaiser-quant_4wb_23.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_23.mif
-diff Coeffs16384Kaiser-quant_4wb_24.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_24.mif
-diff Coeffs16384Kaiser-quant_4wb_25.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_25.mif
-diff Coeffs16384Kaiser-quant_4wb_26.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_26.mif
-diff Coeffs16384Kaiser-quant_4wb_27.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_27.mif
-diff Coeffs16384Kaiser-quant_4wb_28.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_28.mif
-diff Coeffs16384Kaiser-quant_4wb_29.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_29.mif
-diff Coeffs16384Kaiser-quant_4wb_30.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_30.mif
-diff Coeffs16384Kaiser-quant_4wb_31.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_31.mif
-diff Coeffs16384Kaiser-quant_4wb_32.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_32.mif
-diff Coeffs16384Kaiser-quant_4wb_33.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_33.mif
-diff Coeffs16384Kaiser-quant_4wb_34.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_34.mif
-diff Coeffs16384Kaiser-quant_4wb_35.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_35.mif
-diff Coeffs16384Kaiser-quant_4wb_36.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_36.mif
-diff Coeffs16384Kaiser-quant_4wb_37.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_37.mif
-diff Coeffs16384Kaiser-quant_4wb_38.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_38.mif
-diff Coeffs16384Kaiser-quant_4wb_39.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_39.mif
-diff Coeffs16384Kaiser-quant_4wb_40.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_40.mif
-diff Coeffs16384Kaiser-quant_4wb_41.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_41.mif
-diff Coeffs16384Kaiser-quant_4wb_42.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_42.mif
-diff Coeffs16384Kaiser-quant_4wb_43.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_43.mif
-diff Coeffs16384Kaiser-quant_4wb_44.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_44.mif
-diff Coeffs16384Kaiser-quant_4wb_45.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_45.mif
-diff Coeffs16384Kaiser-quant_4wb_46.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_46.mif
-diff Coeffs16384Kaiser-quant_4wb_47.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_47.mif
-diff Coeffs16384Kaiser-quant_4wb_48.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_48.mif
-diff Coeffs16384Kaiser-quant_4wb_49.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_49.mif
-diff Coeffs16384Kaiser-quant_4wb_50.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_50.mif
-diff Coeffs16384Kaiser-quant_4wb_51.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_51.mif
-diff Coeffs16384Kaiser-quant_4wb_52.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_52.mif
-diff Coeffs16384Kaiser-quant_4wb_53.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_53.mif
-diff Coeffs16384Kaiser-quant_4wb_54.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_54.mif
-diff Coeffs16384Kaiser-quant_4wb_55.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_55.mif
-diff Coeffs16384Kaiser-quant_4wb_56.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_56.mif
-diff Coeffs16384Kaiser-quant_4wb_57.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_57.mif
-diff Coeffs16384Kaiser-quant_4wb_58.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_58.mif
-diff Coeffs16384Kaiser-quant_4wb_59.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_59.mif
-diff Coeffs16384Kaiser-quant_4wb_60.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_60.mif
-diff Coeffs16384Kaiser-quant_4wb_61.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_61.mif
-diff Coeffs16384Kaiser-quant_4wb_62.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_62.mif
-diff Coeffs16384Kaiser-quant_4wb_63.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_63.mif
+cd $RADIOHDL_WORK/libraries/dsp/filter/src/hex
+diff Coeffs16384Kaiser-quant_4wb_0.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_0.mif
+diff Coeffs16384Kaiser-quant_4wb_1.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_1.mif
+diff Coeffs16384Kaiser-quant_4wb_2.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_2.mif
+diff Coeffs16384Kaiser-quant_4wb_3.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_3.mif
+diff Coeffs16384Kaiser-quant_4wb_4.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_4.mif
+diff Coeffs16384Kaiser-quant_4wb_5.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_5.mif
+diff Coeffs16384Kaiser-quant_4wb_6.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_6.mif
+diff Coeffs16384Kaiser-quant_4wb_7.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_7.mif
+diff Coeffs16384Kaiser-quant_4wb_8.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_8.mif
+diff Coeffs16384Kaiser-quant_4wb_9.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_9.mif
+diff Coeffs16384Kaiser-quant_4wb_10.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_10.mif
+diff Coeffs16384Kaiser-quant_4wb_11.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_11.mif
+diff Coeffs16384Kaiser-quant_4wb_12.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_12.mif
+diff Coeffs16384Kaiser-quant_4wb_13.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_13.mif
+diff Coeffs16384Kaiser-quant_4wb_14.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_14.mif
+diff Coeffs16384Kaiser-quant_4wb_15.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_15.mif
+diff Coeffs16384Kaiser-quant_4wb_16.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_16.mif
+diff Coeffs16384Kaiser-quant_4wb_17.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_17.mif
+diff Coeffs16384Kaiser-quant_4wb_18.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_18.mif
+diff Coeffs16384Kaiser-quant_4wb_19.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_19.mif
+diff Coeffs16384Kaiser-quant_4wb_20.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_20.mif
+diff Coeffs16384Kaiser-quant_4wb_21.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_21.mif
+diff Coeffs16384Kaiser-quant_4wb_22.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_22.mif
+diff Coeffs16384Kaiser-quant_4wb_23.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_23.mif
+diff Coeffs16384Kaiser-quant_4wb_24.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_24.mif
+diff Coeffs16384Kaiser-quant_4wb_25.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_25.mif
+diff Coeffs16384Kaiser-quant_4wb_26.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_26.mif
+diff Coeffs16384Kaiser-quant_4wb_27.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_27.mif
+diff Coeffs16384Kaiser-quant_4wb_28.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_28.mif
+diff Coeffs16384Kaiser-quant_4wb_29.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_29.mif
+diff Coeffs16384Kaiser-quant_4wb_30.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_30.mif
+diff Coeffs16384Kaiser-quant_4wb_31.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_31.mif
+diff Coeffs16384Kaiser-quant_4wb_32.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_32.mif
+diff Coeffs16384Kaiser-quant_4wb_33.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_33.mif
+diff Coeffs16384Kaiser-quant_4wb_34.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_34.mif
+diff Coeffs16384Kaiser-quant_4wb_35.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_35.mif
+diff Coeffs16384Kaiser-quant_4wb_36.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_36.mif
+diff Coeffs16384Kaiser-quant_4wb_37.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_37.mif
+diff Coeffs16384Kaiser-quant_4wb_38.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_38.mif
+diff Coeffs16384Kaiser-quant_4wb_39.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_39.mif
+diff Coeffs16384Kaiser-quant_4wb_40.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_40.mif
+diff Coeffs16384Kaiser-quant_4wb_41.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_41.mif
+diff Coeffs16384Kaiser-quant_4wb_42.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_42.mif
+diff Coeffs16384Kaiser-quant_4wb_43.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_43.mif
+diff Coeffs16384Kaiser-quant_4wb_44.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_44.mif
+diff Coeffs16384Kaiser-quant_4wb_45.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_45.mif
+diff Coeffs16384Kaiser-quant_4wb_46.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_46.mif
+diff Coeffs16384Kaiser-quant_4wb_47.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_47.mif
+diff Coeffs16384Kaiser-quant_4wb_48.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_48.mif
+diff Coeffs16384Kaiser-quant_4wb_49.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_49.mif
+diff Coeffs16384Kaiser-quant_4wb_50.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_50.mif
+diff Coeffs16384Kaiser-quant_4wb_51.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_51.mif
+diff Coeffs16384Kaiser-quant_4wb_52.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_52.mif
+diff Coeffs16384Kaiser-quant_4wb_53.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_53.mif
+diff Coeffs16384Kaiser-quant_4wb_54.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_54.mif
+diff Coeffs16384Kaiser-quant_4wb_55.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_55.mif
+diff Coeffs16384Kaiser-quant_4wb_56.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_56.mif
+diff Coeffs16384Kaiser-quant_4wb_57.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_57.mif
+diff Coeffs16384Kaiser-quant_4wb_58.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_58.mif
+diff Coeffs16384Kaiser-quant_4wb_59.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_59.mif
+diff Coeffs16384Kaiser-quant_4wb_60.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_60.mif
+diff Coeffs16384Kaiser-quant_4wb_61.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_61.mif
+diff Coeffs16384Kaiser-quant_4wb_62.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_62.mif
+diff Coeffs16384Kaiser-quant_4wb_63.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_63.mif
echo "5) Verify that the created reference LOFAR No DC FIR coefficients mif files are equal to the mif files stored at apertif_unb1_bn_filterbank"
# To create the *.mif use recreate_pfir_mifs or directly use:
-# python $RADIOHDL/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py -f $RADIOHDL/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-nodc.dat -t 16 -p 1024 -w 4 -c 16
-cd $RADIOHDL/libraries/dsp/filter/src/hex
-diff Coeffs16384Kaiser-quant-nodc_4wb_0.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_0.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_1.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_1.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_2.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_2.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_3.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_3.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_4.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_4.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_5.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_5.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_6.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_6.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_7.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_7.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_8.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_8.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_9.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_9.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_10.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_10.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_11.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_11.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_12.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_12.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_13.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_13.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_14.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_14.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_15.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_15.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_16.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_16.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_17.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_17.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_18.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_18.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_19.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_19.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_20.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_20.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_21.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_21.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_22.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_22.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_23.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_23.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_24.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_24.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_25.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_25.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_26.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_26.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_27.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_27.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_28.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_28.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_29.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_29.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_30.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_30.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_31.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_31.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_32.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_32.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_33.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_33.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_34.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_34.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_35.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_35.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_36.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_36.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_37.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_37.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_38.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_38.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_39.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_39.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_40.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_40.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_41.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_41.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_42.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_42.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_43.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_43.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_44.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_44.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_45.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_45.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_46.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_46.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_47.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_47.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_48.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_48.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_49.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_49.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_50.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_50.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_51.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_51.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_52.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_52.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_53.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_53.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_54.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_54.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_55.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_55.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_56.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_56.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_57.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_57.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_58.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_58.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_59.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_59.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_60.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_60.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_61.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_61.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_62.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_62.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_63.mif $RADIOHDL/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_63.mif
+# python $RADIOHDL_WORK/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py -f $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-nodc.dat -t 16 -p 1024 -w 4 -c 16
+cd $RADIOHDL_WORK/libraries/dsp/filter/src/hex
+diff Coeffs16384Kaiser-quant-nodc_4wb_0.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_0.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_1.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_1.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_2.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_2.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_3.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_3.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_4.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_4.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_5.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_5.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_6.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_6.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_7.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_7.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_8.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_8.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_9.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_9.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_10.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_10.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_11.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_11.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_12.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_12.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_13.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_13.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_14.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_14.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_15.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_15.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_16.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_16.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_17.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_17.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_18.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_18.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_19.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_19.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_20.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_20.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_21.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_21.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_22.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_22.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_23.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_23.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_24.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_24.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_25.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_25.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_26.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_26.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_27.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_27.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_28.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_28.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_29.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_29.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_30.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_30.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_31.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_31.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_32.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_32.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_33.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_33.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_34.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_34.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_35.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_35.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_36.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_36.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_37.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_37.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_38.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_38.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_39.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_39.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_40.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_40.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_41.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_41.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_42.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_42.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_43.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_43.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_44.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_44.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_45.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_45.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_46.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_46.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_47.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_47.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_48.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_48.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_49.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_49.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_50.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_50.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_51.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_51.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_52.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_52.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_53.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_53.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_54.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_54.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_55.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_55.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_56.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_56.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_57.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_57.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_58.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_58.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_59.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_59.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_60.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_60.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_61.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_61.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_62.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_62.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_63.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_63.mif
echo "6) Set script exit directory"
-cd $RADIOHDL/libraries/dsp/filter/src/python
+cd $RADIOHDL_WORK/libraries/dsp/filter/src/python
diff --git a/libraries/dsp/filter/src/python/diff_pfir_coefs b/libraries/dsp/filter/src/python/diff_pfir_coefs
index de8b6834af..84b0765968 100755
--- a/libraries/dsp/filter/src/python/diff_pfir_coefs
+++ b/libraries/dsp/filter/src/python/diff_pfir_coefs
@@ -9,16 +9,16 @@
#
# Expected result is that this diff_pfir_coefs script does not report diff's
-diff $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_bypass_8taps_64points_16b.dat ../hex/run_pfir_coeff_m_bypass_8taps_64points_16b.dat
-diff $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_bypass_8taps_64points_9b.dat ../hex/run_pfir_coeff_m_bypass_8taps_64points_9b.dat
-diff $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_fircls1_16taps_1024points_16b.dat ../hex/run_pfir_coeff_m_fircls1_16taps_1024points_16b.dat
-diff $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_fircls1_8taps_32points_9b.dat ../hex/run_pfir_coeff_m_fircls1_8taps_32points_9b.dat
-diff $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_fircls1_8taps_64points_9b.dat ../hex/run_pfir_coeff_m_fircls1_8taps_64points_9b.dat
-diff $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_fircls1_8taps_32points_9b.dat ../hex/run_pfir_coeff_m_flat_hp_fircls1_8taps_32points_9b.dat
-diff $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_fircls1_8taps_64points_9b.dat ../hex/run_pfir_coeff_m_flat_hp_fircls1_8taps_64points_9b.dat
-diff $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_32points_9b.dat ../hex/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_32points_9b.dat
-diff $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_64points_9b.dat ../hex/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_64points_9b.dat
-diff $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_incrementing_8taps_64points_16b.dat ../hex/run_pfir_coeff_m_incrementing_8taps_64points_16b.dat
-diff $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_incrementing_8taps_64points_9b.dat ../hex/run_pfir_coeff_m_incrementing_8taps_64points_9b.dat
-diff $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_lofar_subband_16taps_1024points_16b.dat ../hex/run_pfir_coeff_m_lofar_subband_16taps_1024points_16b.dat
-diff $RADIOHDL/applications/apertif/matlab/data/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_16b.dat ../hex/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_16b.dat
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_bypass_8taps_64points_16b.dat ../hex/run_pfir_coeff_m_bypass_8taps_64points_16b.dat
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_bypass_8taps_64points_9b.dat ../hex/run_pfir_coeff_m_bypass_8taps_64points_9b.dat
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_fircls1_16taps_1024points_16b.dat ../hex/run_pfir_coeff_m_fircls1_16taps_1024points_16b.dat
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_fircls1_8taps_32points_9b.dat ../hex/run_pfir_coeff_m_fircls1_8taps_32points_9b.dat
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_fircls1_8taps_64points_9b.dat ../hex/run_pfir_coeff_m_fircls1_8taps_64points_9b.dat
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_fircls1_8taps_32points_9b.dat ../hex/run_pfir_coeff_m_flat_hp_fircls1_8taps_32points_9b.dat
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_fircls1_8taps_64points_9b.dat ../hex/run_pfir_coeff_m_flat_hp_fircls1_8taps_64points_9b.dat
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_32points_9b.dat ../hex/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_32points_9b.dat
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_64points_9b.dat ../hex/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_64points_9b.dat
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_incrementing_8taps_64points_16b.dat ../hex/run_pfir_coeff_m_incrementing_8taps_64points_16b.dat
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_incrementing_8taps_64points_9b.dat ../hex/run_pfir_coeff_m_incrementing_8taps_64points_9b.dat
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_lofar_subband_16taps_1024points_16b.dat ../hex/run_pfir_coeff_m_lofar_subband_16taps_1024points_16b.dat
+diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_16b.dat ../hex/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_16b.dat
diff --git a/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py b/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py
index 70023b84c7..2b18c920e5 100644
--- a/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py
+++ b/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py
@@ -43,10 +43,10 @@
line argument and is only used to identify the input dat file.
A pfir_coeff_*.dat file can be created using Matlab:
- > $RADIOHDL/applications/apertif/matlab/run_pfir_coef.m
+ > $RADIOHDL_WORK/applications/apertif/matlab/run_pfir_coef.m
The result is then (dependend on the actual settings in run_pfir_coef.m):
- > $RADIOHDL/applications/apertif/matlab/data/pfir_coeff_incrementing_8taps_64points_16b.dat
+ > $RADIOHDL_WORK/applications/apertif/matlab/data/pfir_coeff_incrementing_8taps_64points_16b.dat
This coefficients dat file needs to be copied to the local ../hex directory,
because both the dat and the MIF files sare used in the VHDL testbenches.
diff --git a/libraries/dsp/filter/src/python/recreate_4wb_mifs b/libraries/dsp/filter/src/python/recreate_4wb_mifs
index 67dcca54d0..f285a59c2b 100755
--- a/libraries/dsp/filter/src/python/recreate_4wb_mifs
+++ b/libraries/dsp/filter/src/python/recreate_4wb_mifs
@@ -2,7 +2,7 @@
#find . -name "*4wb_0.mif" - print
# It appears they only are created in the filter library:
-#cd $RADIOHDL/libraries/dsp/filter/src/hex/
+#cd $RADIOHDL_WORK/libraries/dsp/filter/src/hex/
#ll *4wb_0.mif
# yields:
# run_pfb_m_pfir_coeff_fircls1_16taps_32points_16b_4wb_0.mif
@@ -23,7 +23,7 @@
# any Python scripts that Hajee made to access the FIR coefficients in apertif_unb1_bn_filterbank
# will still also work for wpfb_unit_dev.
-cd $RADIOHDL/libraries/dsp/filter/src/python
+cd $RADIOHDL_WORK/libraries/dsp/filter/src/python
python fil_ppf_create_mifs.py -f ../hex/run_pfb_m_pfir_coeff_fircls1_16taps_32points_16b.dat -t 16 -p 32 -w 4 -c 16
python fil_ppf_create_mifs.py -f ../hex/run_pfir_m_pfir_coeff_fircls1_15taps_128points_16b.dat -t 15 -p 128 -w 4 -c 16
diff --git a/libraries/dsp/filter/src/python/recreate_pfir_mifs b/libraries/dsp/filter/src/python/recreate_pfir_mifs
index ee493f3b17..05bcc11aa0 100755
--- a/libraries/dsp/filter/src/python/recreate_pfir_mifs
+++ b/libraries/dsp/filter/src/python/recreate_pfir_mifs
@@ -17,7 +17,7 @@
# > svn status -q ../hex
#
-cd $RADIOHDL/libraries/dsp/filter/src/python
+cd $RADIOHDL_WORK/libraries/dsp/filter/src/python
# run_pfir.m
python fil_ppf_create_mifs.py -f ../hex/run_pfir_m_pfir_coeff_fircls1_15taps_128points_16b.dat -t 15 -p 128 -w 4 -c 16
@@ -37,9 +37,9 @@ python fil_ppf_create_mifs.py -f ../hex/run_pfb_complex_m_pfir_coeff_fircls1_16t
python fil_ppf_create_mifs.py -f ../hex/run_pfir_coeff_m_fircls1_16taps_1024points_16b.dat -t 16 -p 1024 -w 4 -c 16
python fil_ppf_create_mifs.py -f ../hex/run_pfir_coeff_m_lofar_subband_16taps_1024points_16b.dat -t 16 -p 1024 -w 4 -c 16
python fil_ppf_create_mifs.py -f ../hex/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_16b.dat -t 16 -p 1024 -w 4 -c 16
-python fil_ppf_create_mifs.py -f $RADIOHDL/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat -t 16 -p 1024 -w 4 -c 16
+python fil_ppf_create_mifs.py -f $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat -t 16 -p 1024 -w 4 -c 16
-python fil_ppf_create_mifs.py -f $RADIOHDL/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-nodc.dat -t 16 -p 1024 -w 4 -c 16
+python fil_ppf_create_mifs.py -f $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-nodc.dat -t 16 -p 1024 -w 4 -c 16
# run_pfir_coeff.m : channel filterbank (wb = 1)
python fil_ppf_create_mifs.py -f ../hex/run_pfir_coeff_m_bypass_8taps_64points_16b.dat -t 8 -p 64 -w 1 -c 16
diff --git a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd
index 2cb9e0ed76..11a108d75c 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd
@@ -68,11 +68,11 @@
--
-- The reference dat file is generated by the Matlab program:
--
--- $RADIOHDL/applications/apertif/matlab/run_pfir_coeff.m
+-- $RADIOHDL_WORK/applications/apertif/matlab/run_pfir_coeff.m
--
-- The MIF files are generated by the Python script:
--
--- $RADIOHDL/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py
+-- $RADIOHDL_WORK/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py
--
-- The reference dat file and the MIF files use the same g_coefs_file_prefix.
-- For the reference dat file this prefix is expanded by nof_taps, nof_bands
diff --git a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd
index 3e99ad78a3..103f01b592 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd
@@ -29,7 +29,7 @@
-- The g_coefs_file_prefix dat-file and g_data_file dat-file are created by
-- the Matlab script:
--
--- $RADIOHDL/applications/apertif/matlab/run_pfir.m
+-- $RADIOHDL_WORK/applications/apertif/matlab/run_pfir.m
--
-- yields:
--
@@ -51,7 +51,7 @@
-- The MIF files are generated from the g_coefs_file_prefix dat-file by
-- the Python script:
--
--- $RADIOHDL/libraries/dsp/filter/src/python/
+-- $RADIOHDL_WORK/libraries/dsp/filter/src/python/
-- python fil_ppf_create_mifs.py -f ../hex/run_pfir_m_pfir_coeff_fircls1_16taps_128points_16b.dat -t 16 -p 128 -w 1 -c 16
-- python fil_ppf_create_mifs.py -f ../hex/run_pfir_m_pfir_coeff_fircls1_16taps_128points_16b.dat -t 16 -p 128 -w 4 -c 16
--
diff --git a/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd b/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd
index 033699fc04..68d1322523 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd
@@ -22,7 +22,7 @@
-- Purpose: Multi-testbench for fil_ppf_wide using file data
-- Description:
-- Verify fil_ppf_wide using coefficients and data generated by
--- Matlab $RADIOHDL/applications/apertif/matlab/run_pfir.m
+-- Matlab $RADIOHDL_WORK/applications/apertif/matlab/run_pfir.m
--
-- Usage:
-- > as 4
diff --git a/libraries/dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd b/libraries/dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd
index 176c202950..c76e25a5c8 100644
--- a/libraries/dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd
+++ b/libraries/dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd
@@ -23,8 +23,8 @@
-- Description:
-- Verify wpfb_unit_wide using and data generated by Matlab scripts:
--
--- - $RADIOHDL/applications/apertif/matlab/run_pfb.m
--- - $RADIOHDL/applications/apertif/matlab/run_pfb_complex.m
+-- - $RADIOHDL_WORK/applications/apertif/matlab/run_pfb.m
+-- - $RADIOHDL_WORK/applications/apertif/matlab/run_pfb_complex.m
--
-- Usage:
-- > as 4
diff --git a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
index 87ef454477..cc5285d65f 100644
--- a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
+++ b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
@@ -25,8 +25,8 @@
-- Description:
-- This tb uses the Matlab stimuli and expected results obtained with:
--
--- $RADIOHDL/applications/apertif/matlab/run_pfb.m
--- $RADIOHDL/applications/apertif/matlab/run_pfb_complex.m
+-- $RADIOHDL_WORK/applications/apertif/matlab/run_pfb.m
+-- $RADIOHDL_WORK/applications/apertif/matlab/run_pfb_complex.m
--
-- For more description see:
-- . tb_fil_ppf_wide_file_data.vhd
diff --git a/libraries/io/ddr/hdllib.cfg b/libraries/io/ddr/hdllib.cfg
index 260e7b16a3..e095989542 100644
--- a/libraries/io/ddr/hdllib.cfg
+++ b/libraries/io/ddr/hdllib.cfg
@@ -23,9 +23,9 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
- $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
[quartus_project_file]
diff --git a/libraries/io/ddr3/hdllib.cfg b/libraries/io/ddr3/hdllib.cfg
index 31551a6fba..fe384d7392 100644
--- a/libraries/io/ddr3/hdllib.cfg
+++ b/libraries/io/ddr3/hdllib.cfg
@@ -28,13 +28,13 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_AC_ROM.hex .
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_inst_ROM.hex .
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_sequencer_mem.hex .
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_AC_ROM.hex .
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_inst_ROM.hex .
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_sequencer_mem.hex .
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
- #$RADIOHDL/libraries/io/ddr3/src/tcl/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+ #$RADIOHDL_WORK/libraries/io/ddr3/src/tcl/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd b/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
index 924b2dfd30..c5353b2262 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
@@ -121,7 +121,7 @@ PACKAGE ddr3_pkg IS
CONSTANT c_ddr3_seq : t_ddr3_seq := (64, 1, 16, 4, 0, 5);
- -- Manually derived VHDL entity from Verilog module $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.v
+ -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.v
COMPONENT ip_stratixiv_ddr3_uphy_4g_800_master IS
PORT (
pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
@@ -173,7 +173,7 @@ PACKAGE ddr3_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from Verilog module $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.v
+ -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.v
-- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
COMPONENT ip_stratixiv_ddr3_uphy_4g_800_slave IS
PORT (
diff --git a/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg b/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg
index de4897048d..062af006fc 100644
--- a/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg
+++ b/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg
@@ -1,6 +1,7 @@
hdl_lib_name = unb1_eth_10g
hdl_library_clause_name = unb1_eth_10g_lib
hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag tr_10GbE
+hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
synth_files =
@@ -20,7 +21,7 @@ synth_top_level_entity =
quartus_copy_files = quartus/qsys_unb1_eth_10g.qsys .
quartus_qsf_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_tcl_files =
quartus/unb1_eth_10g_pins.tcl
@@ -28,4 +29,4 @@ quartus_tcl_files =
quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_eth_10g/qsys_unb1_eth_10g/synthesis/qsys_unb1_eth_10g.qip
quartus_sdc_files =
- $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
index f10bba2ef5..1d9473211b 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
@@ -9,14 +9,14 @@
# | ASTRON 2014.07.23.09:36:00
# | MM slave port to conduit for the ETH module
# |
-# | $RADIOHDL/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
+# | $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
# |
# | ./avs2_eth_coe.vhd syn, sim
-# | $RADIOHDL/libraries/base/common/src/vhdl/common_pkg.vhd syn, sim
-# | $RADIOHDL/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
-# | $RADIOHDL/libraries/technology/tse/tech_tse_pkg.vhd syn, sim
+# | $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_pkg.vhd syn, sim
+# | $RADIOHDL_WORK/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
+# | $RADIOHDL_WORK/libraries/technology/tse/tech_tse_pkg.vhd syn, sim
# | ./eth_pkg.vhd syn, sim
-# | $RADIOHDL/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
+# | $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
# |
# +-----------------------------------
diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl
index f10bba2ef5..1d9473211b 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl
@@ -9,14 +9,14 @@
# | ASTRON 2014.07.23.09:36:00
# | MM slave port to conduit for the ETH module
# |
-# | $RADIOHDL/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
+# | $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
# |
# | ./avs2_eth_coe.vhd syn, sim
-# | $RADIOHDL/libraries/base/common/src/vhdl/common_pkg.vhd syn, sim
-# | $RADIOHDL/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
-# | $RADIOHDL/libraries/technology/tse/tech_tse_pkg.vhd syn, sim
+# | $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_pkg.vhd syn, sim
+# | $RADIOHDL_WORK/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
+# | $RADIOHDL_WORK/libraries/technology/tse/tech_tse_pkg.vhd syn, sim
# | ./eth_pkg.vhd syn, sim
-# | $RADIOHDL/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
+# | $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
# |
# +-----------------------------------
diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2.tcl b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2.tcl
index f10bba2ef5..1d9473211b 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2.tcl
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2.tcl
@@ -9,14 +9,14 @@
# | ASTRON 2014.07.23.09:36:00
# | MM slave port to conduit for the ETH module
# |
-# | $RADIOHDL/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
+# | $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
# |
# | ./avs2_eth_coe.vhd syn, sim
-# | $RADIOHDL/libraries/base/common/src/vhdl/common_pkg.vhd syn, sim
-# | $RADIOHDL/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
-# | $RADIOHDL/libraries/technology/tse/tech_tse_pkg.vhd syn, sim
+# | $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_pkg.vhd syn, sim
+# | $RADIOHDL_WORK/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
+# | $RADIOHDL_WORK/libraries/technology/tse/tech_tse_pkg.vhd syn, sim
# | ./eth_pkg.vhd syn, sim
-# | $RADIOHDL/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
+# | $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
# |
# +-----------------------------------
diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2a.tcl b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2a.tcl
index f10bba2ef5..1d9473211b 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2a.tcl
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2a.tcl
@@ -9,14 +9,14 @@
# | ASTRON 2014.07.23.09:36:00
# | MM slave port to conduit for the ETH module
# |
-# | $RADIOHDL/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
+# | $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
# |
# | ./avs2_eth_coe.vhd syn, sim
-# | $RADIOHDL/libraries/base/common/src/vhdl/common_pkg.vhd syn, sim
-# | $RADIOHDL/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
-# | $RADIOHDL/libraries/technology/tse/tech_tse_pkg.vhd syn, sim
+# | $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_pkg.vhd syn, sim
+# | $RADIOHDL_WORK/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
+# | $RADIOHDL_WORK/libraries/technology/tse/tech_tse_pkg.vhd syn, sim
# | ./eth_pkg.vhd syn, sim
-# | $RADIOHDL/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
+# | $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
# |
# +-----------------------------------
diff --git a/libraries/technology/ddr/tech_ddr_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
index 2c34cc0b1d..64314ddc33 100644
--- a/libraries/technology/ddr/tech_ddr_component_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
@@ -31,7 +31,7 @@ PACKAGE tech_ddr_component_pkg IS
-- ip_stratixiv
------------------------------------------------------------------------------
- -- Manually derived VHDL entity from Verilog module $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.v
+ -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.v
COMPONENT ip_stratixiv_ddr3_uphy_4g_800_master IS
PORT (
pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
@@ -83,7 +83,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from Verilog module $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.v
+ -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.v
-- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
COMPONENT ip_stratixiv_ddr3_uphy_4g_800_slave IS
PORT (
@@ -134,7 +134,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from Verilog module $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.v
+ -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.v
COMPONENT ip_stratixiv_ddr3_uphy_4g_single_rank_800_master IS
PORT (
pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
@@ -186,7 +186,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from Verilog module $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
+ -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
-- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
COMPONENT ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave IS
PORT (
@@ -237,7 +237,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from Verilog module $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.v
+ -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.v
COMPONENT ip_stratixiv_ddr3_uphy_16g_dual_rank_800 IS
PORT (
pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
@@ -293,7 +293,7 @@ PACKAGE tech_ddr_component_pkg IS
-- ip_arria10
------------------------------------------------------------------------------
- -- Manually derived VHDL entity from VHDL file $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/generated/sim/ip_arria10_ddr4_4g_1600.vhd
+ -- Manually derived VHDL entity from VHDL file $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/generated/sim/ip_arria10_ddr4_4g_1600.vhd
COMPONENT ip_arria10_ddr4_4g_1600 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -331,7 +331,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from VHDL file $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_2000/generated/sim/ip_arria10_ddr4_4g_2000.vhd
+ -- Manually derived VHDL entity from VHDL file $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_2000/generated/sim/ip_arria10_ddr4_4g_2000.vhd
COMPONENT ip_arria10_ddr4_4g_2000 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -373,7 +373,7 @@ PACKAGE tech_ddr_component_pkg IS
-- ip_arria10_e3sge3
------------------------------------------------------------------------------
- -- Manually derived VHDL entity from VHDL file $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/generated/sim/ip_arria10_e3sge3_ddr4_4g_1600.vhd
+ -- Manually derived VHDL entity from VHDL file $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/generated/sim/ip_arria10_e3sge3_ddr4_4g_1600.vhd
COMPONENT ip_arria10_e3sge3_ddr4_4g_1600 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -449,7 +449,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from VHDL file $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/generated/sim/ip_arria10_e3sge3_ddr4_4g_2000.vhd
+ -- Manually derived VHDL entity from VHDL file $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/generated/sim/ip_arria10_e3sge3_ddr4_4g_2000.vhd
COMPONENT ip_arria10_e3sge3_ddr4_4g_2000 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -491,7 +491,7 @@ PACKAGE tech_ddr_component_pkg IS
-- ip_arria10_e1sg
------------------------------------------------------------------------------
- -- Manually derived VHDL entity from VHDL file $RADIOHDL/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim/ip_arria10_e1sg_ddr4_4g_1600.vhd
+ -- Manually derived VHDL entity from VHDL file $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim/ip_arria10_e1sg_ddr4_4g_1600.vhd
COMPONENT ip_arria10_e1sg_ddr4_4g_1600 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -567,7 +567,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from VHDL file $RADIOHDL/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim/ip_arria10_e1sg_ddr4_4g_2000.vhd
+ -- Manually derived VHDL entity from VHDL file $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim/ip_arria10_e1sg_ddr4_4g_2000.vhd
COMPONENT ip_arria10_e1sg_ddr4_4g_2000 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
diff --git a/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
index a715eed9a5..229a8e1824 100644
--- a/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
@@ -32,7 +32,7 @@ PACKAGE tech_ddr_mem_model_component_pkg IS
------------------------------------------------------------------------------
-- Manually derived VHDL entity from Verilog module alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en.sv in:
- -- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_example_design/simulation/vhdl/submodules/
+ -- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_example_design/simulation/vhdl/submodules/
COMPONENT alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en IS
GENERIC (
@@ -86,7 +86,7 @@ PACKAGE tech_ddr_mem_model_component_pkg IS
------------------------------------------------------------------------------
-- Manually derived VHDL entity from ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd in:
- -- $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_141/sim
+ -- $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_141/sim
COMPONENT ed_sim_altera_emif_mem_model_141_z3tvrmq IS
PORT (
mem_ck : in std_logic_vector(0 downto 0) := (others => '0'); -- mem_conduit_end.mem_ck
diff --git a/libraries/technology/hdllib.cfg b/libraries/technology/hdllib.cfg
index cba939b37b..4286581aac 100644
--- a/libraries/technology/hdllib.cfg
+++ b/libraries/technology/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology =
synth_files =
technology_pkg.vhd
- $HDL_BUILD_DIR/<toolset_name>/technology_select_pkg.vhd
+ $HDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
test_bench_files =
regression_test_vhdl =
@@ -15,10 +15,10 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
- technology_select_pkg_<toolset_name>.vhd $HDL_BUILD_DIR/<toolset_name>/technology_select_pkg.vhd
+ technology_select_pkg_<buildset_name>.vhd $HDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
[quartus_project_file]
quartus_copy_files =
- technology_select_pkg_<toolset_name>.vhd $HDL_BUILD_DIR/<toolset_name>/technology_select_pkg.vhd
+ technology_select_pkg_<buildset_name>.vhd $HDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
diff --git a/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
index a33a106553..ae2df593eb 100644
--- a/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/clkbuf_global/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/clkbuf_global/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/clkbuf_global/generate_ip.sh b/libraries/technology/ip_arria10/clkbuf_global/generate_ip.sh
index f587c230c0..2a0e27bb2b 100755
--- a/libraries/technology/ip_arria10/clkbuf_global/generate_ip.sh
+++ b/libraries/technology/ip_arria10/clkbuf_global/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg
index dab29a0357..e38e606ee6 100644
--- a/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/complex_mult/README.txt b/libraries/technology/ip_arria10/complex_mult/README.txt
index 6884ec9c59..3e33649f60 100644
--- a/libraries/technology/ip_arria10/complex_mult/README.txt
+++ b/libraries/technology/ip_arria10/complex_mult/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/complex_mult
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/complex_mult
1) Porting
2) IP component
diff --git a/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
index 3605025500..6827e85513 100644
--- a/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/complex_mult/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/complex_mult/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/complex_mult/generate_ip.sh b/libraries/technology/ip_arria10/complex_mult/generate_ip.sh
index 32f0f2c098..ae842eb1c4 100755
--- a/libraries/technology/ip_arria10/complex_mult/generate_ip.sh
+++ b/libraries/technology/ip_arria10/complex_mult/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10/complex_mult/hdllib.cfg
index 8e7b0c0c0b..09e6c2196d 100644
--- a/libraries/technology/ip_arria10/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10/complex_mult/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/ddio/README.txt b/libraries/technology/ip_arria10/ddio/README.txt
index 6ba19729bb..1823e822ff 100755
--- a/libraries/technology/ip_arria10/ddio/README.txt
+++ b/libraries/technology/ip_arria10/ddio/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/ddio
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ddio
Contents:
diff --git a/libraries/technology/ip_arria10/ddio/compile_ip.tcl b/libraries/technology/ip_arria10/ddio/compile_ip.tcl
index 701077b07f..430497004b 100644
--- a/libraries/technology/ip_arria10/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddio/compile_ip.tcl
@@ -26,7 +26,7 @@ set IPMODEL "SIM";
if {$IPMODEL=="PHY"} {
# This file is based on Qsys-generated file msim_setup.tcl.
- set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/ddio/generated/"
+ set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddio/generated/"
#vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_ddio_in_1_altera_gpio_core_150 ./work/
@@ -52,7 +52,7 @@ if {$IPMODEL=="PHY"} {
} else {
# This file uses a behavioral model because the PHY model does not compile OK, see README.txt.
- set SIM_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/ddio/sim/"
+ set SIM_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddio/sim/"
vcom "$SIM_DIR/ip_arria10_ddio_in_1.vhd"
vcom "$SIM_DIR/ip_arria10_ddio_out_1.vhd"
diff --git a/libraries/technology/ip_arria10/ddio/generate_ip.sh b/libraries/technology/ip_arria10/ddio/generate_ip.sh
index 0f136b9599..a3eae3c680 100755
--- a/libraries/technology/ip_arria10/ddio/generate_ip.sh
+++ b/libraries/technology/ip_arria10/ddio/generate_ip.sh
@@ -34,7 +34,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/ddio/hdllib.cfg b/libraries/technology/ip_arria10/ddio/hdllib.cfg
index f3881529ba..b3a726e9aa 100644
--- a/libraries/technology/ip_arria10/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddio/hdllib.cfg
@@ -13,7 +13,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/ddio/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/ddio/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
index 2fce210025..5dd0355376 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_1600/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
index 933716aae3..ffbd501ac2 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_1600/generated/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/doc/README_ddr4.txt b/libraries/technology/ip_arria10/ddr4_4g_1600/doc/README_ddr4.txt
index b2efc7da1d..6799054f2c 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/doc/README_ddr4.txt
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/doc/README_ddr4.txt
@@ -142,7 +142,7 @@ Quartus IP catalog "Arria10 External Memory Interface" fill in:
run:
cd emif_0_example_design
- . ${RADIOHDL}/tools/quartus/set_quartus unb2 && quartus_sh -t make_qii_design.tcl
+ . ${RADIOHDL_GEAR}/quartus/set_quartus unb2 && quartus_sh -t make_qii_design.tcl
add to qii/ed_synth.qsf:
source ../../unb2_pins_ed_synth.tcl
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/generate_ip.sh b/libraries/technology/ip_arria10/ddr4_4g_1600/generate_ip.sh
index e1b94a498f..9300771833 100755
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/generate_ip.sh
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg
index df28a123cd..bf24013508 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
index f95c590f22..3bd52fc027 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_2000/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl b/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl
index 562340ef4a..91add01c14 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_2000/generated/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10/ddr4_4g_2000/generate_ip.sh b/libraries/technology/ip_arria10/ddr4_4g_2000/generate_ip.sh
index ee4f6f3fb1..edad8d1cf7 100755
--- a/libraries/technology/ip_arria10/ddr4_4g_2000/generate_ip.sh
+++ b/libraries/technology/ip_arria10/ddr4_4g_2000/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg
index b11af9b217..6b605ee02f 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
index b68632f744..24bb783efe 100644
--- a/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_8g_2400/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl
index 8aef634019..e1301d8ab0 100644
--- a/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_8g_2400/generated/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10/ddr4_8g_2400/generate_ip.sh b/libraries/technology/ip_arria10/ddr4_8g_2400/generate_ip.sh
index a6c63a8a24..0eed84da4b 100755
--- a/libraries/technology/ip_arria10/ddr4_8g_2400/generate_ip.sh
+++ b/libraries/technology/ip_arria10/ddr4_8g_2400/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg
index 9a802df0ee..7272be213a 100644
--- a/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/README.txt b/libraries/technology/ip_arria10/ddr4_mem_model_141/README.txt
index 59bbb65023..4921c9d617 100644
--- a/libraries/technology/ip_arria10/ddr4_mem_model_141/README.txt
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/ddr4_mem_model
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_mem_model
1) DDR4 memory simulation model
2) Automated scripts and one time manual actions
@@ -11,7 +11,7 @@ README.txt for $RADIOHDL/libraries/technology/ip_arria10/ddr4_mem_model
The DDR memory model is obtained from the example design that can be generated with Qsys when a DDR IP component is defined.
The first DDR4 component that was created is available via:
- $env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_4g_1600/ip_arria10_ddr4_4g_1600.qsys
+ $env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_1600/ip_arria10_ddr4_4g_1600.qsys
Unfortunately the example design needs to be created via the GUI by pressing the 'Example Design...' button, because the qsys-generate command
that is used in ddr4_4g_1600/generate_ip.sh to create the component does not have an option to also create the example design. After that the
@@ -21,20 +21,20 @@ memory model have been copied to a fixed location in SVN. In this way it is no l
In the example design for ddr4_4g_1600 the generic core files of the DDR model are located at:
- $env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_core_ddr4_141
+ $env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_core_ddr4_141
The size specific entity of the DDR model is created in:
- $env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_141/ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd
+ $env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_141/ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd
The generic core files of the DDR memory model are the same for every DDR size. These files only depend on the Quartus tool version as indicated by 141
(Quartus 14.1) in their name. Therefore the generic core files have been copied to:
- $env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core
+ $env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core
The size specific DDR component file is copied to:
- $env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_4g_1600/ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd
+ $env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_4g_1600/ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd
and other size DDR component files can be store there as well.
@@ -49,7 +49,7 @@ but it is good to manually check with Linux 'diff' as in diff_mem_model.sh that
2) Automated scripts and one time manual actions
-Relative to $RADIOHDL/libraries/technology/ip_arria10/:
+Relative to $RADIOHDL_WORK/libraries/technology/ip_arria10/:
- ddr4_4g_1600/ip_arria10_ddr4_4g_1600.qsys : Qsys definition file for size and speed specific DDR4 controller
- ddr4_4g_1600/generate_ip.sh : Use qsys-generate to create the size and speed specific DDR4 controller
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl
index ff31689fcc..94d8e8d0c5 100644
--- a/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl
@@ -20,9 +20,9 @@
#
#------------------------------------------------------------------------------
-# This file is based on Qsys-generated file $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/mentor/msim_setup.tcl.
+# This file is based on Qsys-generated file $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/mentor/msim_setup.tcl.
#
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/ddr4_mem_model_141"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_mem_model_141"
# Assume library work already exists
vmap ed_sim_altera_emif_mem_model_core_ddr4_141 ./work/
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/diff_mem_model.sh b/libraries/technology/ip_arria10/ddr4_mem_model_141/diff_mem_model.sh
index 32f282b561..bd39700d7f 100755
--- a/libraries/technology/ip_arria10/ddr4_mem_model_141/diff_mem_model.sh
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/diff_mem_model.sh
@@ -31,7 +31,7 @@
#
# eg:
#
-# ./diff_mem_model.sh $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design
+# ./diff_mem_model.sh $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design
#
EXAMPLE_DESIGN_DIR=${1}
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/generate_mem_model.sh b/libraries/technology/ip_arria10/ddr4_mem_model_141/generate_mem_model.sh
index d001ff86d3..631fcbba98 100755
--- a/libraries/technology/ip_arria10/ddr4_mem_model_141/generate_mem_model.sh
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/generate_mem_model.sh
@@ -43,7 +43,7 @@
# ./generate_mem_model.sh ../ddr4_8g_2400/ddr4_inst_example_design
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_mem_model_141/hdllib.cfg
index c574aeda56..bdd0226b24 100644
--- a/libraries/technology/ip_arria10/ddr4_mem_model_141/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/fifo/README.txt b/libraries/technology/ip_arria10/fifo/README.txt
index 48f19d8f0d..cfe2a2a2d8 100755
--- a/libraries/technology/ip_arria10/fifo/README.txt
+++ b/libraries/technology/ip_arria10/fifo/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/fifo
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/fifo
Contents:
diff --git a/libraries/technology/ip_arria10/fifo/generate_ip.sh b/libraries/technology/ip_arria10/fifo/generate_ip.sh
index 7b86d6fd9c..11005f95c6 100755
--- a/libraries/technology/ip_arria10/fifo/generate_ip.sh
+++ b/libraries/technology/ip_arria10/fifo/generate_ip.sh
@@ -39,7 +39,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
index f4f1a6b202..94b0a67c51 100644
--- a/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/flash/asmi_parallel/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/flash/asmi_parallel/generated/sim"
vmap ip_arria10_asmi_parallel_altera_asmi_parallel_150 ./work/
diff --git a/libraries/technology/ip_arria10/flash/asmi_parallel/generate_ip.sh b/libraries/technology/ip_arria10/flash/asmi_parallel/generate_ip.sh
index fc5fb64f74..89aa2bdc59 100755
--- a/libraries/technology/ip_arria10/flash/asmi_parallel/generate_ip.sh
+++ b/libraries/technology/ip_arria10/flash/asmi_parallel/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
index ff92bbf78c..b07ad14a43 100644
--- a/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
index f5746aa6f6..525eab6a87 100644
--- a/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/flash/remote_update/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/flash/remote_update/generated/sim"
vmap ip_arria10_remote_update_altera_remote_update_core_150 ./work/
vmap ip_arria10_remote_update_altera_remote_update_150 ./work/
diff --git a/libraries/technology/ip_arria10/flash/remote_update/generate_ip.sh b/libraries/technology/ip_arria10/flash/remote_update/generate_ip.sh
index 1174a08ec0..806e3f578a 100755
--- a/libraries/technology/ip_arria10/flash/remote_update/generate_ip.sh
+++ b/libraries/technology/ip_arria10/flash/remote_update/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
index a1da1edce3..732cd7b072 100644
--- a/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
index 709861b137..9611ac9b64 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/fractional_pll_clk125/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/fractional_pll_clk125/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk125/generate_ip.sh b/libraries/technology/ip_arria10/fractional_pll_clk125/generate_ip.sh
index e4a41166da..3be0eff606 100755
--- a/libraries/technology/ip_arria10/fractional_pll_clk125/generate_ip.sh
+++ b/libraries/technology/ip_arria10/fractional_pll_clk125/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg
index e3e1e4ab69..825eb56fb4 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
index 032b1953a9..09f0c82f72 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/fractional_pll_clk200/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/fractional_pll_clk200/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk200/generate_ip.sh b/libraries/technology/ip_arria10/fractional_pll_clk200/generate_ip.sh
index f13fa2ffe3..7a5fa7f590 100755
--- a/libraries/technology/ip_arria10/fractional_pll_clk200/generate_ip.sh
+++ b/libraries/technology/ip_arria10/fractional_pll_clk200/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg
index 9efe341b9c..4b8ecae748 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/generate-all-ip.sh b/libraries/technology/ip_arria10/generate-all-ip.sh
index 6f3aacaf5c..f31bf6126c 100755
--- a/libraries/technology/ip_arria10/generate-all-ip.sh
+++ b/libraries/technology/ip_arria10/generate-all-ip.sh
@@ -1,6 +1,6 @@
#!/bin/bash
-files=`find $RADIOHDL/libraries/technology/ip_arria10 -name 'generate_ip.sh' `
+files=`find $RADIOHDL_WORK/libraries/technology/ip_arria10 -name 'generate_ip.sh' `
echo -e "About to generate the following IP blocks:\n$files\n"
diff --git a/libraries/technology/ip_arria10/mac_10g/README.txt b/libraries/technology/ip_arria10/mac_10g/README.txt
index 39766e46cc..1809358e9c 100644
--- a/libraries/technology/ip_arria10/mac_10g/README.txt
+++ b/libraries/technology/ip_arria10/mac_10g/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/mac_10g
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/mac_10g
1) Porting
2) IP component
diff --git a/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
index b73a1147b9..0f37f969c4 100644
--- a/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
@@ -26,8 +26,8 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/mac_10g/generated/sim"
-set IP_TBDIR "$env(RADIOHDL)/libraries/technology/ip_arria10/mac_10g/generated_tb/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/mac_10g/generated/sim"
+set IP_TBDIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/mac_10g/generated_tb/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/mac_10g/generate_ip.sh b/libraries/technology/ip_arria10/mac_10g/generate_ip.sh
index 3ea107bec5..ec19d81816 100755
--- a/libraries/technology/ip_arria10/mac_10g/generate_ip.sh
+++ b/libraries/technology/ip_arria10/mac_10g/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
index 432addcdba..fe9d8cfe4c 100644
--- a/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL/libraries/technology/ip_arria10/mac_10g/generated_tb/generated/sim/ip_arria10_mac_10g_tb.vhd
+ #$RADIOHDL_WORK/libraries/technology/ip_arria10/mac_10g/generated_tb/generated/sim/ip_arria10_mac_10g_tb.vhd
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/README.txt b/libraries/technology/ip_arria10/phy_10gbase_r/README.txt
index 3d1237a61b..f834dcc99e 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/README.txt
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r
1) Porting
2) IP component
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
index 2783be2053..a2f5e5be10 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/phy_10gbase_r/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/phy_10gbase_r/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/generate_ip.sh b/libraries/technology/ip_arria10/phy_10gbase_r/generate_ip.sh
index bb732ad54d..5b4909fd4e 100755
--- a/libraries/technology/ip_arria10/phy_10gbase_r/generate_ip.sh
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
index a9da96f5ea..1d90fe04e6 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
index 907ffbb15b..7130d548d2 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/phy_10gbase_r_12/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/phy_10gbase_r_12/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_12/generate_ip.sh b/libraries/technology/ip_arria10/phy_10gbase_r_12/generate_ip.sh
index f8fe9dbf99..0054ec1bb8 100755
--- a/libraries/technology/ip_arria10/phy_10gbase_r_12/generate_ip.sh
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_12/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg
index df2b66e38e..52f291e044 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
index 761c5fa7f6..ecd8cac0a1 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/phy_10gbase_r_24/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/phy_10gbase_r_24/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_24/generate_ip.sh b/libraries/technology/ip_arria10/phy_10gbase_r_24/generate_ip.sh
index b6193040d7..236321fe68 100755
--- a/libraries/technology/ip_arria10/phy_10gbase_r_24/generate_ip.sh
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_24/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
index ca1857cf44..f203933b41 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
index e78106bd1e..319a668123 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/phy_10gbase_r_4/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/phy_10gbase_r_4/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_4/generate_ip.sh b/libraries/technology/ip_arria10/phy_10gbase_r_4/generate_ip.sh
index 795a08c056..deee2d03d9 100755
--- a/libraries/technology/ip_arria10/phy_10gbase_r_4/generate_ip.sh
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_4/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg
index b41ddab972..84ed2d979e 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
index 51a15947a3..89d1df9134 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/phy_10gbase_r_48/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/phy_10gbase_r_48/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_48/generate_ip.sh b/libraries/technology/ip_arria10/phy_10gbase_r_48/generate_ip.sh
index 658a300732..16e4ca4479 100755
--- a/libraries/technology/ip_arria10/phy_10gbase_r_48/generate_ip.sh
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_48/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg
index 0a0ae1bc3b..23b996d5d1 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
index c138d560d3..ceb880b971 100644
--- a/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/pll_clk125/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/pll_clk125/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/pll_clk125/generate_ip.sh b/libraries/technology/ip_arria10/pll_clk125/generate_ip.sh
index e003654916..6e80538495 100755
--- a/libraries/technology/ip_arria10/pll_clk125/generate_ip.sh
+++ b/libraries/technology/ip_arria10/pll_clk125/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
index fbef174b2a..ba0c574b95 100644
--- a/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
index ffec45c41b..45f591f9eb 100644
--- a/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/pll_clk200/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/pll_clk200/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/pll_clk200/generate_ip.sh b/libraries/technology/ip_arria10/pll_clk200/generate_ip.sh
index 61e5e819ca..15f6b49107 100755
--- a/libraries/technology/ip_arria10/pll_clk200/generate_ip.sh
+++ b/libraries/technology/ip_arria10/pll_clk200/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg
index 03522a7e1e..876299925e 100644
--- a/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
index ce59df714d..8d6c1ffe3a 100644
--- a/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/pll_clk25/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/pll_clk25/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/pll_clk25/generate_ip.sh b/libraries/technology/ip_arria10/pll_clk25/generate_ip.sh
index a71dc4b23a..ee890b1030 100755
--- a/libraries/technology/ip_arria10/pll_clk25/generate_ip.sh
+++ b/libraries/technology/ip_arria10/pll_clk25/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg
index 55e9e73b6a..85ec82a965 100644
--- a/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
index 7a9eb933fb..b9f8625f8c 100644
--- a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/generate_ip.sh b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/generate_ip.sh
index fd6d0e6877..0ab8ca262f 100755
--- a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/generate_ip.sh
+++ b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg
index deacb41f9e..7fe81748c9 100644
--- a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/ram/README.txt b/libraries/technology/ip_arria10/ram/README.txt
index 334f704974..a9fe41102a 100755
--- a/libraries/technology/ip_arria10/ram/README.txt
+++ b/libraries/technology/ip_arria10/ram/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/ram
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ram
Contents:
diff --git a/libraries/technology/ip_arria10/ram/generate_ip.sh b/libraries/technology/ip_arria10/ram/generate_ip.sh
index c6dac88191..c1ca91ebd0 100755
--- a/libraries/technology/ip_arria10/ram/generate_ip.sh
+++ b/libraries/technology/ip_arria10/ram/generate_ip.sh
@@ -39,7 +39,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
index 8011a1bc41..fa0b733b48 100644
--- a/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/temp_sense/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/temp_sense/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/temp_sense/generate_ip.sh b/libraries/technology/ip_arria10/temp_sense/generate_ip.sh
index a64704b54a..3bad9f0bb2 100755
--- a/libraries/technology/ip_arria10/temp_sense/generate_ip.sh
+++ b/libraries/technology/ip_arria10/temp_sense/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10/temp_sense/hdllib.cfg
index 5266b8bcf5..0d4162d734 100644
--- a/libraries/technology/ip_arria10/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10/temp_sense/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
#modelsim_compile_ip_files =
-# $RADIOHDL/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
+# $RADIOHDL_WORK/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
index 92551c4742..51e4722bd7 100644
--- a/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/transceiver_pll_10g/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/transceiver_pll_10g/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/generate_ip.sh b/libraries/technology/ip_arria10/transceiver_pll_10g/generate_ip.sh
index d52cddda76..d42f2ed74c 100755
--- a/libraries/technology/ip_arria10/transceiver_pll_10g/generate_ip.sh
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
index 0858e529e8..75dcfa5eca 100644
--- a/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
index e6ea2fbfb0..69d2418773 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/transceiver_reset_controller_1/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/transceiver_reset_controller_1/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/generate_ip.sh b/libraries/technology/ip_arria10/transceiver_reset_controller_1/generate_ip.sh
index c6562df088..7fc9610b9d 100755
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_1/generate_ip.sh
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
index 180275109a..11f7683e31 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
index eb0fa8bfa8..22ce7e0c27 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/transceiver_reset_controller_12/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/transceiver_reset_controller_12/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_12/generate_ip.sh b/libraries/technology/ip_arria10/transceiver_reset_controller_12/generate_ip.sh
index 053a98b3a8..df0523bb93 100755
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_12/generate_ip.sh
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_12/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg
index 11b372a73f..c6a5d3b797 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
index 368d36c564..1a97798dde 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/transceiver_reset_controller_24/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/transceiver_reset_controller_24/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_24/generate_ip.sh b/libraries/technology/ip_arria10/transceiver_reset_controller_24/generate_ip.sh
index 0b67c011a2..5d2df2513e 100755
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_24/generate_ip.sh
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_24/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
index bb7b3626ee..490fa6c30d 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
index 21e3d5e43f..1d2e7d4997 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/transceiver_reset_controller_4/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/transceiver_reset_controller_4/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_4/generate_ip.sh b/libraries/technology/ip_arria10/transceiver_reset_controller_4/generate_ip.sh
index a1132f0673..9fbe56760f 100755
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_4/generate_ip.sh
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_4/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg
index fa0c96d38c..d24b6726af 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
index 23d218e509..62da163837 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/transceiver_reset_controller_48/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/transceiver_reset_controller_48/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_48/generate_ip.sh b/libraries/technology/ip_arria10/transceiver_reset_controller_48/generate_ip.sh
index 0f94b206ad..1e975d9e03 100755
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_48/generate_ip.sh
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_48/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg
index 0db9821b67..58e0413fd0 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/README.txt b/libraries/technology/ip_arria10/tse_sgmii_gx/README.txt
index 846e784f55..fa105db173 100755
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/README.txt
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/README.txt
@@ -1,8 +1,8 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_gx
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx
The ip_arria10_tse_sgmii_gx IP was ported to Quartus 14.0a10 for Arria10 by creating it in Qsys using the same parameter settings as the ip_arria10_tse_sgmii_lvds, but with GX IO.
The tb_ip_arria10_tse_sgmii_gx.vhd verifies the DUT and simulates OK.
-For more information see: $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
+For more information see: $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
index df199ab12a..22a2478a6c 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
@@ -26,7 +26,7 @@
# - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
# - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/tse_sgmii_gx/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/tse_sgmii_gx/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/generate_ip.sh b/libraries/technology/ip_arria10/tse_sgmii_gx/generate_ip.sh
index c993bc3aa3..949fda1d55 100755
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/generate_ip.sh
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
index aad3d57375..26d59ecf13 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt b/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
index db333f5675..ae9545e000 100755
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds
Contents:
1) Porting
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
index cd1d34428e..395170e9f5 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
@@ -26,7 +26,7 @@
# - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
# - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/tse_sgmii_lvds/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/tse_sgmii_lvds/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/generate_ip.sh b/libraries/technology/ip_arria10/tse_sgmii_lvds/generate_ip.sh
index 92e4b67be2..1627009280 100755
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/generate_ip.sh
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
index d8a27e3848..694b6c70f6 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
index ae08e35d37..0e31995904 100644
--- a/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/voltage_sense/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/voltage_sense/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/voltage_sense/generate_ip.sh b/libraries/technology/ip_arria10/voltage_sense/generate_ip.sh
index 86b053bc2e..44c0232a86 100755
--- a/libraries/technology/ip_arria10/voltage_sense/generate_ip.sh
+++ b/libraries/technology/ip_arria10/voltage_sense/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
index 7268d16a04..a2e3ec5155 100644
--- a/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
[modelsim_project_file]
# There is no simulation model for the FPGA voltage sensor IP
#modelsim_compile_ip_files =
-# $RADIOHDL/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
+# $RADIOHDL_WORK/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl
index 8900569e3f..44e8d9f4bc 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/mac_10g/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/mac_10g/generated/sim"
vmap alt_em10g32_170 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/hdllib.cfg
index 4e64f58057..383c4a3204 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
+ #$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl
index b9a61bdaaf..ff2e50d8d2 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
vmap alt_mem_if_jtag_master_170 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/hdllib.cfg
index 6bd71be1be..189c63a2b6 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl
index 4e0148cb6d..b445f7e500 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/clkbuf_global/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/clkbuf_global/generated/sim"
vmap altclkctrl_170 ./work/
vcom "$IP_DIR/../altclkctrl_170/sim/ip_arria10_e1sg_clkbuf_global_altclkctrl_170_7fwzyby.vhd" -work altclkctrl_170
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/hdllib.cfg
index 53e52737dc..150dab1214 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl
index 678571d01d..036ea3f388 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl
@@ -29,7 +29,7 @@
vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generated/sim"
vmap altera_asmi_parallel_170 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/hdllib.cfg
index 03dcebf48d..0e8e55c1e6 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/hdllib.cfg
@@ -11,5 +11,5 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl
index 34a1a261f4..242b0df1d1 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
vmap altera_avalon_mm_bridge_170 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/hdllib.cfg
index 13d14719a4..1f0e8108fd 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
+ #$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl
index 992f073061..f2394512b8 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl
@@ -30,16 +30,16 @@
#
vmap altera_avalon_onchip_memory2_170 ./work/
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/hdllib.cfg
index 5ceeb58a7d..2edea37fa9 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl
index 281337133e..afd0617db0 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
vmap altera_avalon_packets_to_master_170 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/hdllib.cfg
index 5ab90e77c5..0dc7501636 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl
index 12ef7165fe..5eda20d2ab 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
vmap altera_avalon_sc_fifo_170 ./work/
vlog "$IP_DIR/../altera_avalon_sc_fifo_170/sim/altera_avalon_sc_fifo.v" -work altera_avalon_sc_fifo_170
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/hdllib.cfg
index 9bc4b55fb3..f8ab200bc0 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl
index ea418480be..6c4839b660 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
vmap altera_avalon_st_bytes_to_packets_170 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/hdllib.cfg
index ed679b2fad..0662c5a3d2 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl
index 201e991ee8..c5e0f22569 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
vmap altera_avalon_st_packets_to_bytes_170 ./work/
vlog "$IP_DIR/../altera_avalon_st_packets_to_bytes_170/sim/altera_avalon_st_packets_to_bytes.v" -work altera_avalon_st_packets_to_bytes_170
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/hdllib.cfg
index d04ecd20c4..f8cf50573a 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl
index 972892c081..45d574b99d 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl
@@ -29,42 +29,42 @@
#vlib ./work/ ;# Assume library work already exist
#
vmap altera_emif_170 ./work/
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
vlog "$IP_DIR/../altera_emif_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_170_fpxzpei.v" -work altera_emif_170
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
vlog "$IP_DIR/../altera_emif_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_170_e7aaa3y.v" -work altera_emif_170
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
vlog "$IP_DIR/../altera_emif_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_170_zmrgaza.v" -work altera_emif_170
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
vlog "$IP_DIR/../altera_emif_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_170_xxodvzi.v" -work altera_emif_170
vmap altera_emif_arch_nf_170 ./work/
# ddr4_4g_1600
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti_top.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti_io_aux.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti.sv" -work altera_emif_arch_nf_170
# ddr4_4g_2000
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq_top.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq_io_aux.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq.sv" -work altera_emif_arch_nf_170
# ddr4_8g_1600
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei_top.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei_io_aux.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei.sv" -work altera_emif_arch_nf_170
# ddr4_8g_2400
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_170_as3yf3i_top.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_170_as3yf3i_io_aux.sv" -work altera_emif_arch_nf_170
@@ -110,53 +110,53 @@ set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/g
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/io_12_lane__nf5es_abphy.sv" -work altera_emif_arch_nf_170
vmap altera_emif_cal_slave_nf_170 ./work/
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170
vmap altera_reset_controller_170 ./work/
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_170
vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_170
vmap altera_mm_interconnect_170 ./work/
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_3gbam2q.vhd" -work altera_mm_interconnect_170
vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170
vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_lcqbbfq.vhd" -work altera_mm_interconnect_170
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170
vmap altera_avalon_onchip_memory2_170 ./work/
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
vmap altera_avalon_mm_bridge_170 ./work/
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
vlog "$IP_DIR/../altera_avalon_mm_bridge_170/sim/altera_avalon_mm_bridge.v" -work altera_avalon_mm_bridge_170
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/hdllib.cfg
index 827dca10e5..7e1017d4fd 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl
index 0cabfc5b6e..74fd1d14f3 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl
@@ -31,28 +31,28 @@
vmap altera_emif_arch_nf_170 ./work/
# ddr4_4g_1600
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti_top.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti_io_aux.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti.sv" -work altera_emif_arch_nf_170
# ddr4_4g_2000
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq_top.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq_io_aux.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq.sv" -work altera_emif_arch_nf_170
# ddr4_8g_1600
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei_top.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei_io_aux.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei.sv" -work altera_emif_arch_nf_170
# ddr4_8g_2400
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_170_as3yf3i_top.sv" -work altera_emif_arch_nf_170
vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_170_as3yf3i_io_aux.sv" -work altera_emif_arch_nf_170
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/hdllib.cfg
index 9ae9875f19..8ee9e20c45 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
+ #$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl
index fd26318dbf..8a3a1fc7b4 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl
@@ -31,16 +31,16 @@
vmap altera_emif_cal_slave_nf_170 ./work/
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/hdllib.cfg
index 880bfa7199..c56bf53d57 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl
index a67e4e717b..c2ab5646d9 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl
@@ -31,10 +31,10 @@
vmap altera_eth_tse_170 ./work/
# tse_sgmii_gx
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
vcom "$IP_DIR/../altera_eth_tse_170/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_170_bs6nd6i.vhd" -work altera_eth_tse_170
# tse_sgmii_lvds
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
vcom "$IP_DIR/../altera_eth_tse_170/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_170_kv2t7sq.vhd" -work altera_eth_tse_170
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/hdllib.cfg
index 90be1751ea..a21ef74c59 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/hdllib.cfg
@@ -21,7 +21,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl
index 632980b0fa..ee572db721 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl
@@ -28,6 +28,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
vmap altera_eth_tse_avalon_arbiter_170 ./work/
vlog "$IP_DIR/../altera_eth_tse_avalon_arbiter_170/sim/mentor/altera_eth_tse_avalon_arbiter.v" -work altera_eth_tse_avalon_arbiter_170
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/hdllib.cfg
index 8e921110df..71a9c4e0cc 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl
index 6f5d022c1b..4380a99772 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
vmap altera_eth_tse_mac_170 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/hdllib.cfg
index 82ce945d2d..c8e2e0ffd1 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/hdllib.cfg
@@ -11,6 +11,6 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl
index 4456ba8f17..60a0afa582 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
vmap altera_eth_tse_nf_lvds_terminator_170 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/hdllib.cfg
index 66e05d3284..ad8113152b 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl
index 35458f1cde..26ab106093 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
vmap altera_eth_tse_nf_phyip_terminator_170 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/hdllib.cfg
index a8c8cb1e80..4a68c345a3 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl
index 335a9a7e94..ade847195f 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
vmap altera_eth_tse_pcs_pma_nf_lvds_170 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/hdllib.cfg
index 41c2ef3970..0bb69ecf00 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl
index 8563952cf8..47e92aa0fe 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
vmap altera_eth_tse_pcs_pma_nf_phyip_170 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/hdllib.cfg
index 8c6e48e6b8..14e02053d5 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl
index bc26c17783..d4b2bfb7df 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl
@@ -30,12 +30,12 @@
vmap altera_iopll_170 ./work/
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/pll_clk25/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_clk25/generated/sim"
vlog "$IP_DIR/../altera_iopll_170/sim/ip_arria10_e1sg_pll_clk25_altera_iopll_170_7lq52ua.vo" -work altera_iopll_170
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/pll_clk125/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_clk125/generated/sim"
vlog "$IP_DIR/../altera_iopll_170/sim/ip_arria10_e1sg_pll_clk125_altera_iopll_170_3a4ewza.vo" -work altera_iopll_170
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/pll_clk200/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_clk200/generated/sim"
vlog "$IP_DIR/../altera_iopll_170/sim/ip_arria10_e1sg_pll_clk200_altera_iopll_170_bqwoevq.vo" -work altera_iopll_170
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/hdllib.cfg
index fbb4d7a81c..d75309def4 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl
index 66f56205dd..4da1aeca69 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
vmap altera_ip_col_if_170 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/hdllib.cfg
index 50fbc5fe6e..540bef90d6 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl
index 1d4cac7395..657e2f6557 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
vmap altera_jtag_dc_streaming_170 ./work/
vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_jtag_interface.v" -work altera_jtag_dc_streaming_170
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/hdllib.cfg
index 97ab5a0c8e..58633386cd 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl
index 7848c8ff28..1add231a2d 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl
@@ -27,7 +27,7 @@
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
vmap altera_lvds_170 ./work/
vcom "$IP_DIR/../altera_lvds_170/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_170_m5pqrlq.vhd" -work altera_lvds_170
vcom "$IP_DIR/../altera_lvds_170/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_170_o42lhkq.vhd" -work altera_lvds_170
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/hdllib.cfg
index 7c57a46fc7..5aafdf155e 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl
index 5fd24f5b7a..fba2fedca1 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl
@@ -27,7 +27,7 @@
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
vmap altera_lvds_core20_170 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/hdllib.cfg
index fdc2c86776..a72e4c297c 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl
index a270f35508..3cff03c2cc 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
#
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
vmap altera_merlin_master_translator_170 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/hdllib.cfg
index d0ccefa672..1f2a23c00e 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl
index 66fdebf441..e62f1475ff 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
#
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
vmap altera_merlin_slave_translator_170 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/hdllib.cfg
index c063d07c3f..ef9b259c5f 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl
index 8b15c1f71d..26070a8285 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl
@@ -30,17 +30,17 @@
#
vmap altera_mm_interconnect_170 ./work/
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_3gbam2q.vhd" -work altera_mm_interconnect_170
vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170
vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_lcqbbfq.vhd" -work altera_mm_interconnect_170
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/hdllib.cfg
index aa6f8e7f04..f08778a020 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl
index 1a89c9e523..f6c6f073cc 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/flash/remote_update/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/flash/remote_update/generated/sim"
vmap altera_remote_update_170 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/hdllib.cfg
index 6e71bd65da..fed8c35d6c 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/hdllib.cfg
@@ -11,5 +11,5 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl
index fbf003ec00..534817e5a0 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/flash/remote_update/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/flash/remote_update/generated/sim"
vmap altera_remote_update_core_170 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/hdllib.cfg
index 15d9e9c994..ef449921eb 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/hdllib.cfg
@@ -1,5 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_altera_remote_update_core_170
hdl_library_clause_name = altera_remote_update_core_170
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -7,4 +9,4 @@ synth_files =
test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl
index bdb77d6c74..872cb90083 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
#
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
vmap altera_reset_controller_170 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/hdllib.cfg
index 092ef35e7d..2bf3f30746 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl
index 709cb2f5f7..16bbd179c3 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generated/sim"
vmap altera_common_sv_packages ./work/
vmap altera_xcvr_atx_pll_a10_170 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/hdllib.cfg
index 0f41fa5846..db46806823 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl
index d96408232b..b390847fb3 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generated/sim"
vmap altera_xcvr_fpll_a10_170 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/hdllib.cfg
index 7796dcce2e..fbcddbb6b9 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl
index 578bb1e0bf..6a82671583 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl
@@ -32,7 +32,7 @@ vmap altera_xcvr_native_a10_170 ./work/
vmap altera_common_sv_packages ./work/
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generated/sim"
# common dependencies
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
@@ -68,31 +68,31 @@ set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_otmjdta.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
# phy_10gbase_r_24
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generated/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_170_edf7tdy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_edf7tdy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
# phy_10gbase_r_12
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generated/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_170_uyp7wca.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_uyp7wca.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
# phy_10gbase_r_4
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generated/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_170_5bntvuq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_5bntvuq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
# phy_10gbase_r_3
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generated/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_170_exiqljq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_exiqljq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
# phy_10gbase_r
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generated/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_170_s7t4kxy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_s7t4kxy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
# tse_sgmii_gx
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_xcvr_native_a10_170_q6y47ey.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_q6y47ey.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/hdllib.cfg
index 2183a5d0ce..96fde27cdf 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/hdllib.cfg
@@ -11,6 +11,6 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl
index 24d690a758..a2ab22b40e 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generated/sim"
vmap altera_xcvr_reset_control_170 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/hdllib.cfg
index 14d4ae7d74..eedb9c51bd 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/hdllib.cfg
@@ -11,6 +11,6 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl
index 012fb6f793..5e29d06a31 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
vmap channel_adapter_170 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/hdllib.cfg
index 8545849901..eebe788ab1 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl
index 205892f0f9..1f7ca18055 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
vmap timing_adapter_170 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/hdllib.cfg
index 05cae0c6e5..4633fb177d 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
index 941bd98e5e..3ec2cd3bae 100644
--- a/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/clkbuf_global/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/clkbuf_global/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_clkbuf_global.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/clkbuf_global/generate_ip.sh
index 39a7312b5a..878b355c4b 100755
--- a/libraries/technology/ip_arria10_e1sg/clkbuf_global/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
index 66fbcda43e..7504ddb609 100644
--- a/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/README.txt b/libraries/technology/ip_arria10_e1sg/complex_mult/README.txt
index 6884ec9c59..3e33649f60 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/complex_mult
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/complex_mult
1) Porting
2) IP component
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
index d583f8dd2f..30b5ed4fdf 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/complex_mult/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/complex_mult/generated/sim"
vmap altmult_complex_170 ./work/
vlog "$IP_DIR/../altmult_complex_170/sim/ip_arria10_e1sg_complex_mult_altmult_complex_170_myrk3hi.v" -work altmult_complex_170
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/complex_mult/generate_ip.sh
index 96be7f2926..c09f8f660f 100755
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
index a13aea7eea..02a6d4874a 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/README.txt b/libraries/technology/ip_arria10_e1sg/ddio/README.txt
index 6ba19729bb..1823e822ff 100755
--- a/libraries/technology/ip_arria10_e1sg/ddio/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/ddio/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/ddio
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ddio
Contents:
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
index d0750f0b4a..dbab4802e0 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
@@ -34,7 +34,7 @@ set IPMODEL "SIM";
if {$IPMODEL=="PHY"} {
# OUTDATED AND NOT USED!!
# This file is based on Qsys-generated file msim_setup.tcl.
- set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddio/generated/"
+ set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddio/generated/"
#vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_ddio_in_1_altera_gpio_core_150 ./work/
@@ -60,7 +60,7 @@ if {$IPMODEL=="PHY"} {
} else {
# This file uses a behavioral model because the PHY model does not compile OK, see README.txt.
- set SIM_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddio/sim/"
+ set SIM_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddio/sim/"
vcom "$SIM_DIR/ip_arria10_e1sg_ddio_in_1.vhd"
vcom "$SIM_DIR/ip_arria10_e1sg_ddio_out_1.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ddio/generate_ip.sh
index 38843a3303..389f44f511 100755
--- a/libraries/technology/ip_arria10_e1sg/ddio/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/ddio/generate_ip.sh
@@ -34,7 +34,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
index 4e22b8d962..8fd1e669ff 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
@@ -13,7 +13,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
index 0940d7bc60..46dff72ef5 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_4g_1600.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
index 2665360e00..357e27bb3d 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generate_ip.sh
index 9d98e72bce..9e63a80dc1 100755
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
index 0d945c2c2e..9fa46dcfab 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
index cda82b8f1a..9497e3c7cc 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_4g_2000.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
index d1d4ac6eee..44a321affd 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generate_ip.sh
index 64364ce034..bbbc8b7d3a 100755
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
index 536c9de8e3..695d6e9a6b 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
index 5b537b7446..ef04250d03 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_8g_1600.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
index 7999771512..d384a4b5ea 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generate_ip.sh
index cf24b8c0fc..92679228d0 100755
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
index cd9f99df19..fb991b3967 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
index 9fc229d78e..5798a026b4 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_8g_2400.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
index 474979c64c..c8089fe859 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generate_ip.sh
index b121261404..14eafe5589 100755
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
index 24326c3dab..ceea1ea066 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/README.txt b/libraries/technology/ip_arria10_e1sg/fifo/README.txt
index 48f19d8f0d..cfe2a2a2d8 100755
--- a/libraries/technology/ip_arria10_e1sg/fifo/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/fifo/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/fifo
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/fifo
Contents:
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/fifo/generate_ip.sh
index bf3d60117d..0a36be76c2 100755
--- a/libraries/technology/ip_arria10_e1sg/fifo/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/fifo/generate_ip.sh
@@ -39,7 +39,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
index 564d9fee8a..381c1944ae 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
@@ -29,7 +29,7 @@
vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_asmi_parallel.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generate_ip.sh
index c5d3230359..6bac379b60 100755
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
index d320b46a36..05b50ddd82 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
index 661d93389c..71a2b64c03 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/flash/remote_update/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/flash/remote_update/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_remote_update.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/flash/remote_update/generate_ip.sh
index f9d585f8bb..fdc94c04b3 100755
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
index 3573f2b97b..9db01d2cbd 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
index c322b04b88..6f767532c6 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_fractional_pll_clk125.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/generate_ip.sh
index a64d398529..739ce3f27e 100755
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
index 9634b02d1a..f4a814161a 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
index 66b0acffe2..5c8674a583 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_fractional_pll_clk200.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/generate_ip.sh
index 10802670a7..b5aa729588 100755
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
index 44cd4208ee..1a6b0a376b 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/generate-all-ip.sh b/libraries/technology/ip_arria10_e1sg/generate-all-ip.sh
index 5a4792151f..c35c6f1060 100755
--- a/libraries/technology/ip_arria10_e1sg/generate-all-ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/generate-all-ip.sh
@@ -1,6 +1,6 @@
#!/bin/bash
-files=`find $RADIOHDL/libraries/technology/ip_arria10_e1sg -name 'generate_ip.sh' `
+files=`find $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg -name 'generate_ip.sh' `
echo -e "About to generate the following IP blocks:\n$files\n"
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/README.txt b/libraries/technology/ip_arria10_e1sg/mac_10g/README.txt
index 39766e46cc..1809358e9c 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/mac_10g
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/mac_10g
1) Porting
2) IP component
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
index 182854c2ae..afd8e94094 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/mac_10g/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/mac_10g/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_mac_10g.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/mac_10g/generate_ip.sh
index 510c550c2c..2cfec0ecc4 100755
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2a" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
index df5dd2cd6f..8b45746380 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
+ #$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
index b1f2e646f4..d1275d8574 100644
--- a/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/mult_add4/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/mult_add4/generated/sim"
vmap ip_arria10_e1sg_mult_add4 ./work/
vmap altera_mult_add_170 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/mult_add4/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/mult_add4/generate_ip.sh
index 7e679ec72f..b52b5b14f7 100755
--- a/libraries/technology/ip_arria10_e1sg/mult_add4/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/mult_add4/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
index d1975b4cdb..41b87622bf 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generate_ip.sh
index 7f651810ba..310c756aee 100755
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
index 0512f9e534..d35beb3b4e 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
index 5d77e22a0f..32a75009b8 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_12.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generate_ip.sh
index 0ecdbd7fef..0102778d11 100755
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
index d3cdd5c5e8..29adb1d9b8 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
index f0a762da1b..9cc7830fe8 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_24.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generate_ip.sh
index 32c3254360..58b28fabec 100755
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
index 0bbce083bb..4bd7fc021e 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
index ee72e73fa0..4a869f57e2 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_3.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generate_ip.sh
index 3240ee8311..1bb64ac723 100755
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
index 54dc096906..decc5b54b1 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
index 99833e4807..4f4b143abd 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_4.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generate_ip.sh
index 445f2fed57..ee4b74eceb 100755
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
index 1e221ad118..89b33cab67 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
index 29557e8e1a..f9487e1a4f 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_48.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generate_ip.sh
index 552a7a512e..c0fc1047af 100755
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
index 0ab9d6043a..8876a23c01 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
index b77afd9f1f..643d6d4096 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/pll_clk125/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_clk125/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_clk125.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/pll_clk125/generate_ip.sh
index 17e6673b38..a00ef44c62 100755
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
index 26aa9670ad..5d46c79cf0 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
index e6c1c486d5..281a4c3d46 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
@@ -29,5 +29,5 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/pll_clk200/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_clk200/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_clk200.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/pll_clk200/generate_ip.sh
index 33378d48f5..cf60d4df54 100755
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
index 3e4b94666b..f931e60738 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
index f7704430d6..278ea6499a 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/pll_clk25/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_clk25/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_clk25.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/pll_clk25/generate_ip.sh
index ef4a1a8184..525783f424 100755
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
index a48c2fd138..776f7257d6 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
index 7a9a224c07..36568c9bf3 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_xgmii_mac_clocks.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generate_ip.sh
index 77f31d835c..37e803de61 100755
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
index 646acb5d17..9bbc02a2ca 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/ram/README.txt b/libraries/technology/ip_arria10_e1sg/ram/README.txt
index 334f704974..a9fe41102a 100755
--- a/libraries/technology/ip_arria10_e1sg/ram/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/ram/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/ram
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ram
Contents:
diff --git a/libraries/technology/ip_arria10_e1sg/ram/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ram/generate_ip.sh
index 3349722ddf..a1a766d44d 100755
--- a/libraries/technology/ip_arria10_e1sg/ram/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/ram/generate_ip.sh
@@ -39,7 +39,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
index 9718b9d6eb..c0cef1e9d8 100644
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/temp_sense/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/temp_sense/generated/sim"
vmap altera_temp_sense_170 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/temp_sense/generate_ip.sh
index ab8fbc6a74..be991c110a 100755
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
index 7b8c823272..0d72950c53 100644
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
#modelsim_compile_ip_files =
-# $RADIOHDL/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
+# $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
index e98b88b1eb..63f8171a4b 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_pll_10g.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generate_ip.sh
index 12de447a12..c4af138a6c 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
index 4e68a1f017..08c2ac709b 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
index d870859329..01c8d37521 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_1.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generate_ip.sh
index 17e84e3a49..bdf2f728e8 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
index 4e0fa44f85..66e3ff86ed 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
index be4e8146ae..b4cc6457dc 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_12.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/generate_ip.sh
index db50fda3d1..9dc526c3bb 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
index 127271a295..23934188a7 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
index 9a3467b8c8..21b8cb5187 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_24.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/generate_ip.sh
index 761d94c869..ab440cf7a0 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
index 810f75c8b0..f71b8b1bd4 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
index af3b3937c3..aed0f2bedc 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_3.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generate_ip.sh
index ed92ce368e..db457e873c 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
index 591a426a5d..b12597b826 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
index 18b928a9ee..a4e0bc1b15 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_4.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/generate_ip.sh
index ad1d84d8d1..cb635dde75 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
index 6415a1556f..49ae906062 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
index 0673565d44..7ef9776084 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_48.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/generate_ip.sh
index 81f461f352..9aac11c07a 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
index 5a8b7cda1b..51f03a221a 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/README.txt b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/README.txt
index 846e784f55..fa105db173 100755
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/README.txt
@@ -1,8 +1,8 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_gx
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx
The ip_arria10_tse_sgmii_gx IP was ported to Quartus 14.0a10 for Arria10 by creating it in Qsys using the same parameter settings as the ip_arria10_tse_sgmii_lvds, but with GX IO.
The tb_ip_arria10_tse_sgmii_gx.vhd verifies the DUT and simulates OK.
-For more information see: $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
+For more information see: $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
index 4c2692eead..fcc8f3f3cb 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_tse_sgmii_gx.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generate_ip.sh
index 91152f6cd8..e949f73d02 100755
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
index 03743cf832..abfacc5cb9 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/README.txt b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/README.txt
index 0120d49c00..efe749e3a0 100755
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
-See README.txt for $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds
+See README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
index 5172f9ab3e..28a6acf47c 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_tse_sgmii_lvds.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generate_ip.sh
index 759e004252..27c0af99a9 100755
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
index 4379000892..9a67954387 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
@@ -13,7 +13,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
index 74b7f80f17..3f9a54b2ab 100644
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/voltage_sense/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/voltage_sense/generated/sim"
vmap ip_arria10_e1sg_voltage_sense ./work/
vmap altera_voltage_sensor_170 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/voltage_sense/generate_ip.sh
index df1e1b6ff7..2aa4ddd7b1 100755
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
index fb423817ca..58a16e4119 100644
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
[modelsim_project_file]
# There is no simulation model for the FPGA voltage sensor IP
#modelsim_compile_ip_files =
-# $RADIOHDL/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
+# $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
index 73468f7681..53c76e2b5e 100644
--- a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/clkbuf_global/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/clkbuf_global/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/generate_ip.sh
index 49379c421c..758a7a1300 100755
--- a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg
index d2f1999952..0c279c1749 100644
--- a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/complex_mult/README.txt b/libraries/technology/ip_arria10_e3sge3/complex_mult/README.txt
index 6884ec9c59..3e33649f60 100644
--- a/libraries/technology/ip_arria10_e3sge3/complex_mult/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/complex_mult/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/complex_mult
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/complex_mult
1) Porting
2) IP component
diff --git a/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
index 3208d6b990..7692d23a29 100644
--- a/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/complex_mult/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/complex_mult/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/complex_mult/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/complex_mult/generate_ip.sh
index 17ce37998c..c6270c47fd 100755
--- a/libraries/technology/ip_arria10_e3sge3/complex_mult/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/complex_mult/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg
index 43be8eb955..66eec32570 100644
--- a/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/README.txt b/libraries/technology/ip_arria10_e3sge3/ddio/README.txt
index 6ba19729bb..1823e822ff 100755
--- a/libraries/technology/ip_arria10_e3sge3/ddio/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/ddio
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ddio
Contents:
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
index effc6fdee4..4a9ef46272 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
@@ -26,7 +26,7 @@ set IPMODEL "SIM";
if {$IPMODEL=="PHY"} {
# This file is based on Qsys-generated file msim_setup.tcl.
- set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/ddio/generated/"
+ set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddio/generated/"
#vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_e3sge3_ddio_in_1_altera_gpio_core_151 ./work/
@@ -52,7 +52,7 @@ if {$IPMODEL=="PHY"} {
} else {
# This file uses a behavioral model because the PHY model does not compile OK, see README.txt.
- set SIM_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/ddio/sim/"
+ set SIM_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddio/sim/"
vcom "$SIM_DIR/ip_arria10_e3sge3_ddio_in_1.vhd"
vcom "$SIM_DIR/ip_arria10_e3sge3_ddio_out_1.vhd"
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/ddio/generate_ip.sh
index 03a3952849..6e82be25a6 100755
--- a/libraries/technology/ip_arria10_e3sge3/ddio/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/generate_ip.sh
@@ -34,7 +34,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg
index 32435e25bc..ffdcf8e0d8 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg
@@ -13,7 +13,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
index d84123a805..6d0ae35297 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
index 078caca747..8c69969d8b 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/generated/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/generate_ip.sh
index 456bf4082d..a7d8a8c99a 100755
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg
index a725f7255c..7de6d9cc7e 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
index 6d60c70c53..c7213abdc7 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl
index 970a198dfe..a7fa910541 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/generated/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/generate_ip.sh
index d4e86d0574..f9cc3a792f 100755
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg
index ef60735a91..5b8927482c 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
index d938e48e59..b9cad2a73e 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
index bca2ea4f57..ced3c0a509 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/generated/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/generate_ip.sh
index f33d5f1a97..e69749253f 100755
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg
index 2ecb131124..a90e81ff44 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
index e739c5bafd..3cefb93ecc 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl
index 9e393f40f0..80794294d5 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/generated/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/generate_ip.sh
index c596a2ed76..d94b5a367b 100755
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg
index 8c19e34ac8..91a0f97472 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/fifo/README.txt b/libraries/technology/ip_arria10_e3sge3/fifo/README.txt
index 48f19d8f0d..cfe2a2a2d8 100755
--- a/libraries/technology/ip_arria10_e3sge3/fifo/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/fifo/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/fifo
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/fifo
Contents:
diff --git a/libraries/technology/ip_arria10_e3sge3/fifo/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/fifo/generate_ip.sh
index bc69bfb3cf..9ba8d5f30f 100755
--- a/libraries/technology/ip_arria10_e3sge3/fifo/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/fifo/generate_ip.sh
@@ -39,7 +39,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
index 986ce3beb7..c48cca790f 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/generated/sim"
vmap ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151 ./work/
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/generate_ip.sh
index bbb1b3d862..415afb38df 100755
--- a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg
index 704be79dca..0ceeddd60a 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
index 896f4912a3..995703d181 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/flash/remote_update/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/flash/remote_update/generated/sim"
vmap ip_arria10_e3sge3_remote_update_altera_remote_update_core_151 ./work/
vmap ip_arria10_e3sge3_remote_update_altera_remote_update_151 ./work/
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/generate_ip.sh
index afdc526af2..c7f75c95a3 100755
--- a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg
index 697564797b..4bf49a5928 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
index feed76c693..26d0ca325d 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/generate_ip.sh
index 41436995e9..39c66a5756 100755
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg
index febed22b2c..86e2ac2c1a 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
index c5c3f0f8f7..0383174c3b 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/generate_ip.sh
index 9d8d321ab6..ae8e7c1453 100755
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg
index fd683a26a0..dc5a2ead34 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/generate-all-ip.sh b/libraries/technology/ip_arria10_e3sge3/generate-all-ip.sh
index efb1fd404f..a4edc2b256 100755
--- a/libraries/technology/ip_arria10_e3sge3/generate-all-ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/generate-all-ip.sh
@@ -1,6 +1,6 @@
#!/bin/bash
-files=`find $RADIOHDL/libraries/technology/ip_arria10_e3sge3 -name 'generate_ip.sh' `
+files=`find $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3 -name 'generate_ip.sh' `
echo -e "About to generate the following IP blocks:\n$files\n"
diff --git a/libraries/technology/ip_arria10_e3sge3/mac_10g/README.txt b/libraries/technology/ip_arria10_e3sge3/mac_10g/README.txt
index 39766e46cc..1809358e9c 100644
--- a/libraries/technology/ip_arria10_e3sge3/mac_10g/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/mac_10g/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/mac_10g
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/mac_10g
1) Porting
2) IP component
diff --git a/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
index 91dc85f7e8..23647961fc 100644
--- a/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
@@ -26,8 +26,8 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/mac_10g/generated/sim"
-set IP_TBDIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/mac_10g/generated_tb/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/mac_10g/generated/sim"
+set IP_TBDIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/mac_10g/generated_tb/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/mac_10g/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/mac_10g/generate_ip.sh
index c7844fb9c7..f044512e6f 100755
--- a/libraries/technology/ip_arria10_e3sge3/mac_10g/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/mac_10g/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2a" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
index 0363ce82a4..98c627b440 100644
--- a/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL/libraries/technology/ip_arria10_e3sge3/mac_10g/generated_tb/generated/sim/ip_arria10_e3sge3_mac_10g_tb.vhd
+ #$RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/mac_10g/generated_tb/generated/sim/ip_arria10_e3sge3_mac_10g_tb.vhd
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl
index 2cb6b47731..e3aa9bf13c 100644
--- a/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/mult_add4/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/mult_add4/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/mult_add4/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/mult_add4/generate_ip.sh
index 49a8d3f6d7..f69815f399 100755
--- a/libraries/technology/ip_arria10_e3sge3/mult_add4/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/mult_add4/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
index cc299be023..c58d590f77 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/generate_ip.sh
index a018e42cb5..5c4ec99b83 100755
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg
index 849af13e09..ef62134dae 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
index 07133cd4a6..7b2e6c3379 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/generate_ip.sh
index 8de924c914..50c4340cbf 100755
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg
index fba55e697b..7f282e1841 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
index 2458a6a329..86a711170a 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/generate_ip.sh
index 1c2ecad6dd..67d5db7845 100755
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg
index b04864d239..c71586e637 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
index 12fd3803c8..52f79da7b2 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/generate_ip.sh
index d8e452c226..8d5eea44ca 100755
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg
index efb4fdc211..fa9eb57875 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
index 0c4828bfe8..82b3ff12a7 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/generate_ip.sh
index 8053bf8985..be0fa4e3df 100755
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg
index 6182b3cd25..a9a4f25f2a 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
index e1a730824c..71564250c5 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/pll_clk125/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/pll_clk125/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk125/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/pll_clk125/generate_ip.sh
index bd6d263187..4719ca011f 100755
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk125/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk125/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg
index b87c3842cd..4744956c34 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
index 10b86dcf0f..5418dc79a1 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/pll_clk200/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/pll_clk200/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk200/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/pll_clk200/generate_ip.sh
index 28143365d7..33be5e78da 100755
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk200/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk200/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg
index 746b95e754..bbf989101b 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
index 7c21e1477b..07c26baa46 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/pll_clk25/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/pll_clk25/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk25/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/pll_clk25/generate_ip.sh
index 5ba1c24f21..1842975a9b 100755
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk25/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk25/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg
index d921f8ffc4..faa8018251 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
index 3439eaac59..4e80e99645 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/generate_ip.sh
index f3999e92a4..bcd02e3ab6 100755
--- a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg
index 163fd8ab18..8ffd2a8b64 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/README.txt b/libraries/technology/ip_arria10_e3sge3/ram/README.txt
index 334f704974..a9fe41102a 100755
--- a/libraries/technology/ip_arria10_e3sge3/ram/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/ram/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/ram
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ram
Contents:
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/ram/generate_ip.sh
index eb179c877c..a823b95804 100755
--- a/libraries/technology/ip_arria10_e3sge3/ram/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/ram/generate_ip.sh
@@ -39,7 +39,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
index 7b28095bcc..f863a70074 100644
--- a/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/temp_sense/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/temp_sense/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/temp_sense/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/temp_sense/generate_ip.sh
index e80b08cebe..3bd136fa89 100755
--- a/libraries/technology/ip_arria10_e3sge3/temp_sense/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/temp_sense/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg
index 0f2bea029f..eb2f310663 100644
--- a/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
#modelsim_compile_ip_files =
-# $RADIOHDL/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
+# $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
index b4e0ebc532..806454fac6 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/generate_ip.sh
index 5461170236..7c0cf72bb6 100755
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg
index 24cb2c48da..351187d243 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
index 74ce7d3632..fd40ff8721 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/generate_ip.sh
index be133092b0..4aabb018df 100755
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg
index 38e2dc944a..fd0ff98f51 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
index 05054e25f5..dda89b41c6 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/generate_ip.sh
index 2ee36221e7..66527a06b5 100755
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg
index 491b15792b..6d8544bec1 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
index c6b6ace326..54f87c5f3f 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/generate_ip.sh
index 87585ed5eb..80b6a05bc1 100755
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg
index 6eb1e1c0ca..3104cabeda 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
index 22fa35d5e5..8ad00f7882 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/generate_ip.sh
index 441da965c0..bbebfcca43 100755
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg
index 0d46dbf1cf..4c9fed6698 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
index c11c7f1b14..e77af624de 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/generate_ip.sh
index 6b0e35088a..990f62ead1 100755
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg
index 2598b18af3..86b474c736 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/README.txt b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/README.txt
index 846e784f55..fa105db173 100755
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/README.txt
@@ -1,8 +1,8 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_gx
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx
The ip_arria10_tse_sgmii_gx IP was ported to Quartus 14.0a10 for Arria10 by creating it in Qsys using the same parameter settings as the ip_arria10_tse_sgmii_lvds, but with GX IO.
The tb_ip_arria10_tse_sgmii_gx.vhd verifies the DUT and simulates OK.
-For more information see: $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
+For more information see: $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
index c1a2232975..38368d2110 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
@@ -26,7 +26,7 @@
# - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
# - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/generate_ip.sh
index bfb902fe77..566ba013c1 100755
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg
index 931957a3a1..df60de6e51 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/README.txt b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/README.txt
index 0120d49c00..efe749e3a0 100755
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
-See README.txt for $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds
+See README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
index 2fa7b84ba7..41c63a1ae3 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
@@ -26,7 +26,7 @@
# - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
# - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/generate_ip.sh
index 71ffbc46ed..90ae85bfa7 100755
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg
index 5961fb8881..8c175111ce 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
index acf293d5a9..8b61b7eb88 100644
--- a/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/voltage_sense/generated/sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/voltage_sense/generated/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/voltage_sense/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/voltage_sense/generate_ip.sh
index 584aa5894e..0f8e0f516a 100755
--- a/libraries/technology/ip_arria10_e3sge3/voltage_sense/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/voltage_sense/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb2a
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg
index 5c3a2a7bfe..b6529dfd36 100644
--- a/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
[modelsim_project_file]
# There is no simulation model for the FPGA voltage sensor IP
#modelsim_compile_ip_files =
-# $RADIOHDL/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
+# $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
index 5a773b5915..2690e54a37 100644
--- a/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
@@ -23,7 +23,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
# Get the memory model fro the uphy_4g_* from the ip_stratixiv_ddr3_uphy_4g_800_master example design
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_example_design"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_example_design"
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_mem_model/generate_ip.sh b/libraries/technology/ip_stratixiv/ddr3_mem_model/generate_ip.sh
index 4ce79ca261..2d1b37088b 100755
--- a/libraries/technology/ip_stratixiv/ddr3_mem_model/generate_ip.sh
+++ b/libraries/technology/ip_stratixiv/ddr3_mem_model/generate_ip.sh
@@ -37,7 +37,7 @@
#
# Tool settings for selected target "unb1" with stratixiv
-. ${RADIOHDL}/tools/quartus/set_quartus unb1
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb1
# The ip_stratixiv_ddr3_uphy_4g_800_master.v IP must have been generated
diff --git a/libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg
index 54443d82bc..6e6d7706b8 100644
--- a/libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
index 0287e1c1f8..ab5bd65220 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
index 140a87ea3a..c14c1911ff 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generate_ip.sh b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generate_ip.sh
index 606a1e3bef..8e4111eeae 100755
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generate_ip.sh
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generate_ip.sh
@@ -36,7 +36,7 @@
#
# Tool settings for selected target "unb1" with stratixiv
-. ${RADIOHDL}/tools/quartus/set_quartus unb1
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb1
# Generate IP
if ! [ -d "generated" ]; then
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg
index bd0c67d481..1b5ee24b7e 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg
@@ -11,8 +11,8 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
index a6c92d8db2..1ad73c93b5 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
index 9fba13ceb4..7e5924ab38 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generate_ip.sh b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generate_ip.sh
index 9b5b31184b..891821bdd4 100755
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generate_ip.sh
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generate_ip.sh
@@ -36,7 +36,7 @@
#
# Tool settings for selected target "unb1" with stratixiv
-. ${RADIOHDL}/tools/quartus/set_quartus unb1
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb1
# Generate IP
if ! [ -d "generated" ]; then
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg
index 1b11fbe2fa..9644bb62bc 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg
@@ -11,8 +11,8 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
index 72572588f9..3cd4b20618 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl
index c759a138e7..6a6e860295 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generate_ip.sh b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generate_ip.sh
index fb4f6af395..c6c755d977 100755
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generate_ip.sh
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generate_ip.sh
@@ -36,7 +36,7 @@
#
# Tool settings for selected target "unb1" with stratixiv
-. ${RADIOHDL}/tools/quartus/set_quartus unb1
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb1
# Generate IP
if ! [ -d "generated" ]; then
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg
index 4d64d1ae14..f56145e6a6 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
index 9f01c99f53..1d878a2a3c 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
index 18e0b98691..e0786cddeb 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generate_ip.sh b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generate_ip.sh
index 0a4ca4b56e..0ce4fa270e 100755
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generate_ip.sh
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generate_ip.sh
@@ -36,7 +36,7 @@
#
# Tool settings for selected target "unb1" with stratixiv
-. ${RADIOHDL}/tools/quartus/set_quartus unb1
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb1
# Generate IP
if ! [ -d "generated" ]; then
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg
index 5b71690a3a..1f4f9200a4 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg
@@ -11,8 +11,8 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
index 6314a870e6..962b26b7f9 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
index a65e8718ff..00f508ab33 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generate_ip.sh b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generate_ip.sh
index d33ae63c3d..b651c73760 100755
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generate_ip.sh
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generate_ip.sh
@@ -36,7 +36,7 @@
#
# Tool settings for selected target "unb1" with stratixiv
-. ${RADIOHDL}/tools/quartus/set_quartus unb1
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb1
# Generate IP
if ! [ -d "generated" ]; then
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg
index 09191b848f..bf801765f0 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg
@@ -11,8 +11,8 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/flash/hdllib.cfg b/libraries/technology/ip_stratixiv/flash/hdllib.cfg
index 47a0434734..31d0dceb88 100644
--- a/libraries/technology/ip_stratixiv/flash/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/flash/hdllib.cfg
@@ -13,7 +13,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL/libraries/external/numonyx_m25p128/NU_M25P128_V10/sim/memory_file .
+ $RADIOHDL_WORK/libraries/external/numonyx_m25p128/NU_M25P128_V10/sim/memory_file .
[quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/generate-all-ip.sh b/libraries/technology/ip_stratixiv/generate-all-ip.sh
index ee0c0da47a..6377b91415 100755
--- a/libraries/technology/ip_stratixiv/generate-all-ip.sh
+++ b/libraries/technology/ip_stratixiv/generate-all-ip.sh
@@ -1,6 +1,6 @@
#!/bin/bash
-files=`find $RADIOHDL/libraries/technology/ip_stratixiv -name 'generate_ip.sh' | sort -r `
+files=`find $RADIOHDL_WORK/libraries/technology/ip_stratixiv -name 'generate_ip.sh' | sort -r `
# sort file list backward to generate ddr3_mem_model before ddr3_uphy_4g_800_* (required)
echo -e "About to generate the following IP blocks:\n$files\n"
diff --git a/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl b/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
index 39345203c2..33c1e12bf7 100644
--- a/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
@@ -24,7 +24,7 @@
# file msim_setup.tcl.
# tr_xaui is the first module I did this for.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim"
#vlib ./work/ ;# Assume library work already exists
#vmap work ./work/
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generate_ip.sh b/libraries/technology/ip_stratixiv/mac_10g/generate_ip.sh
index 50b6563809..4f7c890f8c 100755
--- a/libraries/technology/ip_stratixiv/mac_10g/generate_ip.sh
+++ b/libraries/technology/ip_stratixiv/mac_10g/generate_ip.sh
@@ -41,7 +41,7 @@
run_script=0
if [ $run_script -gt 0 ]; then
# Tool settings for selected target "unb1" with stratixiv
- . ${RADIOHDL}/tools/quartus/set_quartus unb1
+ . ${RADIOHDL_GEAR}/quartus/set_quartus unb1
if ! [ -d "generated" ]; then
mkdir generated
diff --git a/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg b/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg
index c548304587..0863274168 100644
--- a/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg
@@ -13,7 +13,7 @@ test_bench_files =
modelsim_copy_files =
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
index 2da2fedde2..ed22b0d052 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
@@ -27,7 +27,7 @@
# correct compile order).
# EK: The model files in phy_xaui_0_sim/ are suitable for all hard xaui IP variants.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim"
#vlib ./work/ ;# EK: Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
index 42bd765382..7eae3900cf 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
+++ b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
@@ -27,7 +27,7 @@
# correct compile order). Bonus of this is also that there will be no errors
# when making all_mod without having run the XAUI megawizard first.
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim"
+set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim"
#vlib ./work/ ;# EK: Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generate_ip.sh b/libraries/technology/ip_stratixiv/phy_xaui/generate_ip.sh
index c6edadc7bc..30ef911296 100755
--- a/libraries/technology/ip_stratixiv/phy_xaui/generate_ip.sh
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generate_ip.sh
@@ -39,7 +39,7 @@
#
# Tool settings for selected target "unb1" with stratixiv
-. ${RADIOHDL}/tools/quartus/set_quartus unb1
+. ${RADIOHDL_GEAR}/quartus/set_quartus unb1
if ! [ -d "generated" ]; then
mkdir generated
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg b/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
index 06cb12d45e..260a93b452 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
@@ -21,8 +21,8 @@ modelsim_copy_files =
wave_tb_ip_stratixiv_phy_xaui_ppm.do .
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
- $RADIOHDL/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
+ $RADIOHDL_WORK/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
[quartus_project_file]
diff --git a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
index 089a409ec2..4f9aec4417 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
@@ -52,7 +52,7 @@ PACKAGE tech_mac_10g_component_pkg IS
-- ip_stratixiv
------------------------------------------------------------------------------
- -- Copied from entity $RADIOHDL/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g.vhd
+ -- Copied from entity $RADIOHDL_WORK/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g.vhd
COMPONENT ip_stratixiv_mac_10g IS
PORT (
csr_clk_clk : in std_logic := '0'; -- csr_clk.clk
diff --git a/libraries/technology/tse/tech_tse_component_pkg.vhd b/libraries/technology/tse/tech_tse_component_pkg.vhd
index 9a92d12862..6671ba6f7e 100644
--- a/libraries/technology/tse/tech_tse_component_pkg.vhd
+++ b/libraries/technology/tse/tech_tse_component_pkg.vhd
@@ -31,7 +31,7 @@ PACKAGE tech_tse_component_pkg IS
-- ip_stratixiv
------------------------------------------------------------------------------
- -- Copied from $RADIOHDL/libraries/technology/ip_stratixiv/tse_sgmii_lvds/ip_stratixiv_tse_sgmii_lvds.vhd
+ -- Copied from $RADIOHDL_WORK/libraries/technology/ip_stratixiv/tse_sgmii_lvds/ip_stratixiv_tse_sgmii_lvds.vhd
COMPONENT ip_stratixiv_tse_sgmii_lvds IS
PORT (
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
@@ -78,7 +78,7 @@ PACKAGE tech_tse_component_pkg IS
);
END COMPONENT;
- -- Copied from $RADIOHDL/libraries/technology/ip_stratixiv/tse_sgmii_gx/ip_stratixiv_tse_sgmii_gx.vhd
+ -- Copied from $RADIOHDL_WORK/libraries/technology/ip_stratixiv/tse_sgmii_gx/ip_stratixiv_tse_sgmii_gx.vhd
COMPONENT ip_stratixiv_tse_sgmii_gx IS
PORT (
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
@@ -147,7 +147,7 @@ PACKAGE tech_tse_component_pkg IS
-- ip_arria10
------------------------------------------------------------------------------
- -- Copied from $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds/generated/sim/ip_arria10_tse_sgmii_lvds.vhd
+ -- Copied from $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/generated/sim/ip_arria10_tse_sgmii_lvds.vhd
COMPONENT ip_arria10_tse_sgmii_lvds IS
PORT (
clk : in std_logic := '0'; -- control_port_clock_connection.clk
@@ -198,7 +198,7 @@ PACKAGE tech_tse_component_pkg IS
END COMPONENT;
- -- Copied from $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_gx/generated/sim/ip_arria10_tse_sgmii_gx.vhd
+ -- Copied from $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx/generated/sim/ip_arria10_tse_sgmii_gx.vhd
COMPONENT ip_arria10_tse_sgmii_gx IS
PORT (
clk : in std_logic := '0'; -- control_port_clock_connection.clk
@@ -265,7 +265,7 @@ PACKAGE tech_tse_component_pkg IS
-- ip_arria10_e3sge3
------------------------------------------------------------------------------
- -- Copied from $RADIOHDL/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/generated/sim/ip_arria10_e3sge3_tse_sgmii_lvds.vhd
+ -- Copied from $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/generated/sim/ip_arria10_e3sge3_tse_sgmii_lvds.vhd
COMPONENT ip_arria10_e3sge3_tse_sgmii_lvds IS
PORT (
reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
@@ -316,7 +316,7 @@ PACKAGE tech_tse_component_pkg IS
END COMPONENT;
- -- Copied from $RADIOHDL/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/generated/sim/ip_arria10_e3sge3_tse_sgmii_gx.vhd
+ -- Copied from $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/generated/sim/ip_arria10_e3sge3_tse_sgmii_gx.vhd
COMPONENT ip_arria10_e3sge3_tse_sgmii_gx IS
PORT (
reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
@@ -383,7 +383,7 @@ PACKAGE tech_tse_component_pkg IS
-- ip_arria10_e1sg
------------------------------------------------------------------------------
- -- Copied from $RADIOHDL/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim/ip_arria10_e1sg_tse_sgmii_lvds.vhd
+ -- Copied from $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim/ip_arria10_e1sg_tse_sgmii_lvds.vhd
COMPONENT ip_arria10_e1sg_tse_sgmii_lvds IS
PORT (
reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
@@ -434,7 +434,7 @@ PACKAGE tech_tse_component_pkg IS
END COMPONENT;
- -- Copied from $RADIOHDL/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim/ip_arria10_e1sg_tse_sgmii_gx.vhd
+ -- Copied from $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim/ip_arria10_e1sg_tse_sgmii_gx.vhd
COMPONENT ip_arria10_e1sg_tse_sgmii_gx IS
PORT (
reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
--
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