- Nov 13, 2014
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Eric Kooistra authored
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Eric Kooistra authored
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Eric Kooistra authored
Enabled tx_pma_clkout to have 312.5 MHz and 156.25 MHz output clocks that are needed for the mac_10g IP when using 64b data.
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Eric Kooistra authored
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Kenneth Hiemstra authored
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Kenneth Hiemstra authored
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Kenneth Hiemstra authored
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Kenneth Hiemstra authored
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- Nov 12, 2014
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Kenneth Hiemstra authored
[tech_tse_lib.tb_tech_tse_pkg]
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Kenneth Hiemstra authored
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Kenneth Hiemstra authored
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Kenneth Hiemstra authored
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Kenneth Hiemstra authored
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Kenneth Hiemstra authored
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Kenneth Hiemstra authored
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- Nov 07, 2014
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Kenneth Hiemstra authored
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Kenneth Hiemstra authored
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Kenneth Hiemstra authored
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- Nov 06, 2014
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Kenneth Hiemstra authored
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Kenneth Hiemstra authored
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Kenneth Hiemstra authored
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Kenneth Hiemstra authored
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- Nov 05, 2014
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Kenneth Hiemstra authored
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Kenneth Hiemstra authored
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Daniel van der Schuur authored
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- Nov 03, 2014
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Daniel van der Schuur authored
.added to hdllib.cfg -Also instantiated common_shiftrams in corr_accumulator; -Correlator now instantiates most required stages .excl. corr_folder
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Eric Kooistra authored
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Eric Kooistra authored
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Jonathan Hargreaves authored
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Daniel van der Schuur authored
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Daniel van der Schuur authored
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Daniel van der Schuur authored
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Eric Kooistra authored
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- Oct 31, 2014
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Kenneth Hiemstra authored
tr_xaui
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Eric Kooistra authored
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Eric Kooistra authored
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Eric Kooistra authored
Use stratixiv 200 MHz PLL from tech_pll/. Only support g_sel=0,1 (skipped g_sel=2, because it is not used in UniBoard1 designs).
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Jonathan Hargreaves authored
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Eric Kooistra authored
Changed "8) Revisions for Quartus" into "8) Design revisions", because the scheme is independent of Quartus. Added title "8) Design revisions" to the contents section.
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Eric Kooistra authored
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