-Fixed syntax errors.

libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd

@@ -35,7 +35,7 @@ ENTITY corr_accumulator IS
   GENERIC (
     g_nof_inputs        : NATURAL;
     g_accumulator_depth : NATURAL;
-    g_data_w        : NATURAL
+    g_data_w            : NATURAL
    ); 
   PORT (
     rst            : IN  STD_LOGIC;
@@ -53,10 +53,10 @@ ARCHITECTURE rtl OF corr_accumulator IS
   -- c_shiftram_delay is such that common_shiftram output aligns exactly with snk_in_arr. Functionally this 
   -- means we aligned the current word to the corresponding previous word at the adder inputs.
   CONSTANT c_shiftram_delay           : NATURAL := g_accumulator_depth-c_shiftram_io_delay;
-  CONSTANT c_shift_w                  : NATURAL := ceil_log2(g_nof_words);
-  CONSTANT c_common_shiftram_shift_in : STD_LOGIC_VECTOR := (c_shift_w-1 DOWNTO 0) := TO_UVEC(c_shiftram_delay, c_shift_w);
+  CONSTANT c_shift_w                  : NATURAL := ceil_log2(g_accumulator_depth);
+  CONSTANT c_common_shiftram_shift_in : STD_LOGIC_VECTOR(c_shift_w-1 DOWNTO 0) := TO_UVEC(c_shiftram_delay, c_shift_w);
 
-  SIGNAL corr_adder_snk_in_2arr_2     : t_dp_sosi_2arr_2(g_nof_inputs-1 DOWNTO 0) -- Array of pairs
+  SIGNAL corr_adder_snk_in_2arr_2     : t_dp_sosi_2arr_2(g_nof_inputs-1 DOWNTO 0); -- Array of pairs
   SIGNAL corr_adder_src_out_arr       : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
 
   SIGNAL common_shiftram_snk_in_arr   : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
@@ -94,8 +94,10 @@ BEGIN
   -- . common_shiftram_src_out_arr = delayed corr_adder_src_out_arr
   -----------------------------------------------------------------------------
   -- Concatenate real&imaginary parts
-  common_shiftram_snk_in_arr(i).data(g_data_w-1   DOWNTO g_data_w/2) <= corr_adder_src_out_arr(i).re(g_data_w/2-1 DOWNTO 0);
-  common_shiftram_snk_in_arr(i).data(g_data_w/2-1 DOWNTO 0)          <= corr_adder_src_out_arr(i).im(g_data_w/2-1 DOWNTO 0);
+  gen_concat_complex : FOR i IN 0 TO g_nof_inputs-1 GENERATE
+    common_shiftram_snk_in_arr(i).data(g_data_w-1   DOWNTO g_data_w/2) <= corr_adder_src_out_arr(i).re(g_data_w/2-1 DOWNTO 0);
+    common_shiftram_snk_in_arr(i).data(g_data_w/2-1 DOWNTO 0)          <= corr_adder_src_out_arr(i).im(g_data_w/2-1 DOWNTO 0);
+  END GENERATE;
 
   gen_common_shiftram : FOR i IN 0 TO g_nof_inputs-1 GENERATE
     u_common_shiftram : ENTITY common_lib.common_shiftram
@@ -121,6 +123,6 @@ BEGIN
   -- Output 1/g_accumulator_depth words per stream
   -- . Not implemented yet.
   -----------------------------------------------------------------------------
-  src_out <= common_shiftram_src_out_arr;
+  src_out_arr <= common_shiftram_src_out_arr;
 
 END rtl;

libraries/dsp/correlator/src/vhdl/corr_adder.vhd

@@ -29,7 +29,7 @@ USE dp_lib.dp_stream_pkg.ALL;
 -- . Provide an array of complex adders with streaming I/O
 -- Description:
 -- . Adds snk_in_2arr_2[i][0] to snk_in_2arr_2[i][1] yielding 
---   src_out_2arr[i] for i in 0..g_nof_inputs-1.
+--   src_out_arr[i] for i in 0..g_nof_inputs-1.
 
 ENTITY corr_adder IS
   GENERIC (
@@ -39,9 +39,9 @@ ENTITY corr_adder IS
     rst            : IN  STD_LOGIC;
     clk            : IN  STD_LOGIC;
 
-    snk_in_2arr_2  : IN  t_dp_sosi_2arr_2(g_nof_inputs);
+    snk_in_2arr_2  : IN  t_dp_sosi_2arr_2(g_nof_inputs-1 DOWNTO 0);
 
-    src_out_2arr   : OUT t_dp_sosi_2arr_2(g_nof_inputs)
+    src_out_arr   : OUT t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0)
   );
 END corr_adder;
 
@@ -65,8 +65,8 @@ BEGIN
       in_ai      => snk_in_2arr_2(i)(0).im(35 DOWNTO 0),
       in_br      => snk_in_2arr_2(i)(1).re(35 DOWNTO 0),
       in_bi      => snk_in_2arr_2(i)(1).im(35 DOWNTO 0),
-      out_re     => src_out_2arr(i).re(63 DOWNTO 0),
-      out_im     => src_out_2arr(i).im(63 DOWNTO 0)
+      out_re     => src_out_arr(i).re(63 DOWNTO 0),
+      out_im     => src_out_arr(i).im(63 DOWNTO 0)
     );     
   END GENERATE;
 

libraries/dsp/correlator/src/vhdl/corr_multiplier.vhd

@@ -39,9 +39,9 @@ ENTITY corr_multiplier IS
     rst            : IN  STD_LOGIC;
     clk            : IN  STD_LOGIC;
 
-    snk_in_2arr_2  : IN  t_dp_sosi_2arr_2(g_nof_inputs);
+    snk_in_2arr_2  : IN  t_dp_sosi_2arr_2(g_nof_inputs-1 DOWNTO 0);
 
-    src_out_2arr   : OUT t_dp_sosi_2arr_2(g_nof_inputs)
+    src_out_arr   : OUT t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0)
   );
 END corr_multiplier;
 
@@ -73,8 +73,8 @@ BEGIN
       in_ai      => snk_in_2arr_2(i)(0).im(17 DOWNTO 0),
       in_br      => snk_in_2arr_2(i)(1).re(17 DOWNTO 0),
       in_bi      => snk_in_2arr_2(i)(1).im(17 DOWNTO 0),
-      out_pr     => src_out_2arr(i).re(35 DOWNTO 0),
-      out_pi     => src_out_2arr(i).im(35 DOWNTO 0)
+      out_pr     => src_out_arr(i).re(35 DOWNTO 0),
+      out_pi     => src_out_arr(i).im(35 DOWNTO 0)
     );     
   END GENERATE;
 

libraries/dsp/correlator/src/vhdl/correlator.vhd

@@ -41,13 +41,14 @@ ENTITY correlator IS
 
     snk_in_arr     : IN  t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
 
-
+    src_out        : OUT t_dp_sosi
   );
 END correlator;
 
 ARCHITECTURE str OF correlator IS
 
-  SIGNAL corr_permutator_src_out_2arr_2 : t_dp_sosi_2arr_2(g_nof_inputs*(g_nof_inputs+1)/2-1 DOWNTO 0) -- Array of pairs
+  SIGNAL corr_permutator_src_out_2arr_2 : t_dp_sosi_2arr_2(g_nof_inputs*(g_nof_inputs+1)/2-1 DOWNTO 0); -- Array of pairs
+  SIGNAL corr_folder_src_out_2arr_2     : t_dp_sosi_2arr_2(g_nof_inputs*(g_nof_inputs+1)/2-1 DOWNTO 0); -- Array of pairs, not folded yet
   SIGNAL corr_multiplier_src_out_arr    : t_dp_sosi_arr(g_nof_mults-1 DOWNTO 0);
   SIGNAL corr_accumulator_src_out_arr   : t_dp_sosi_arr(g_nof_mults-1 DOWNTO 0);
 
@@ -94,8 +95,10 @@ BEGIN
   -----------------------------------------------------------------------------
   u_corr_accumulator : ENTITY work.corr_accumulator
   GENERIC MAP (
-    g_nof_inputs => g_nof_mults
-  )
+    g_nof_inputs        => g_nof_mults,
+    g_accumulator_depth => 10,
+    g_data_w            => 32
+)
   PORT MAP (
     clk            => clk,
     rst            => rst,