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RTSD
HDL
Commits
91f9cc0b
Commit
91f9cc0b
authored
10 years ago
by
Kenneth Hiemstra
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boards/uniboard1/designs/unb1_minimal/doc/README
+13
-17
13 additions, 17 deletions
boards/uniboard1/designs/unb1_minimal/doc/README
boards/uniboard1/designs/unb1_test/doc/README
+4
-8
4 additions, 8 deletions
boards/uniboard1/designs/unb1_test/doc/README
with
17 additions
and
25 deletions
boards/uniboard1/designs/unb1_minimal/doc/README
+
13
−
17
View file @
91f9cc0b
Quick steps to compile and use design [unb1_
test
] in RadionHDL
Quick steps to compile and use design [unb1_
minimal
] in RadionHDL
--------------------------------------------------------------
--------------------------------------------------------------
---
Assuming:
-> ~/RadioHDL --symlink--> ~/svn/UniBoard_FP7/RadioHDL/
-> an empty [build] directory (~/RadioHDL/trunk/build)
-> SOPC mmm
-> Quartus v11.1
Oneclick Commands:
Oneclick Commands:
python
~/RadioHDL/trunk
/tools/oneclick/base/modelsim_config.py
python
$RADIOHDL
/tools/oneclick/base/modelsim_config.py
python
~/RadioHDL/trunk
/tools/oneclick/base/quartus_config.py
python
$RADIOHDL
/tools/oneclick/base/quartus_config.py
-> From here either continue to Modelsim (simulation) or Quartus (synthesis)
-> From here either continue to Modelsim (simulation) or Quartus (synthesis)
...
@@ -19,9 +14,10 @@ Modelsim instructions:
...
@@ -19,9 +14,10 @@ Modelsim instructions:
run_modelsim
run_modelsim
# in Modelsim do:
# in Modelsim do:
lp unb1_test
rm $UNB/Software/python/sim/*
lp unb1_minimal
mk compile all
mk compile all
# now double click on testbenc
e
file
# now double click on testbenc
h
file
as 10
as 10
run 10us
run 10us
# to end simulation:
# to end simulation:
...
@@ -29,25 +25,25 @@ Modelsim instructions:
...
@@ -29,25 +25,25 @@ Modelsim instructions:
Quartus instructions (for SOPC):
Quartus instructions (for SOPC):
unb2_sopc unb1_
test
_sopc && unb2_app unb1_
test
_sopc && unb2_qcomp unb1_
test
_sopc
unb2_sopc unb1_
minimal
_sopc && unb2_app unb1_
minimal
_sopc && unb2_qcomp unb1_
minimal
_sopc
Quartus instructions (for QSYS):
Quartus instructions (for QSYS):
unb2_qsys unb1_
test
_qsys && unb2_app unb1_
test
_qsys use=qsys && unb2_qcomp unb1_
test
_qsys
unb2_qsys unb1_
minimal
_qsys && unb2_app unb1_
minimal
_qsys use=qsys && unb2_qcomp unb1_
minimal
_qsys
Convert .sof to .rbf:
Convert .sof to .rbf:
cd
~/RadioHDL/trunk
/build/quartus/unb1_
test
_sopc/
cd
$RADIOHDL
/build/quartus/unb1_
minimal
_sopc/
quartus_cpf -c --option=/tmp/temp_options_file unb1_
test
_sopc.sof unb1_
test
_sopc.rbf
quartus_cpf -c --option=/tmp/temp_options_file unb1_
minimal
_sopc.sof unb1_
minimal
_sopc.rbf
# assuming in /tmp/temp_options_file: Bitstream_compression=on
# assuming in /tmp/temp_options_file: Bitstream_compression=on
Send to LCU capture5:
Send to LCU capture5:
scp unb1_
test
_sopc.rbf capture5:~/rbf/
scp unb1_
minimal
_sopc.rbf capture5:~/rbf/
# Now login on capture5 and use pythonscripts to program flash:
# Now login on capture5 and use pythonscripts to program flash:
cd python/peripherals/
cd python/peripherals/
python util_system_info.py --gn 0:7 -n4 # updating REGMAPs
python util_system_info.py --gn 0:7 -n4 # updating REGMAPs
python util_system_info.py --gn 0:7 -n2 # Read design names to check if WDI reset to factory is necessary
python util_system_info.py --gn 0:7 -n2 # Read design names to check if WDI reset to factory is necessary
python util_epcs.py --gn 0 -n9 # reset FPGA to factory default (FN0)
python util_epcs.py --gn 0 -n9 # reset FPGA to factory default (FN0)
python util_epcs.py --gn 0 -n4 -s ~/rbf/unb1_
test
.rbf # program rbf file to user flash (FN0)
python util_epcs.py --gn 0 -n4 -s ~/rbf/unb1_
minimal
.rbf # program rbf file to user flash (FN0)
python util_epcs.py --gn 0 -n8 # load user image from flash (FN0)
python util_epcs.py --gn 0 -n8 # load user image from flash (FN0)
python util_system_info.py --gn 0:7 -n4 # obviously updating REGMAPs
python util_system_info.py --gn 0:7 -n4 # obviously updating REGMAPs
python util_system_info.py --gn 0:7 -n2 # Read design names
python util_system_info.py --gn 0:7 -n2 # Read design names
...
...
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Click to expand it.
boards/uniboard1/designs/unb1_test/doc/README
+
4
−
8
View file @
91f9cc0b
Quick steps to compile and use design [unb1_test] in RadionHDL
Quick steps to compile and use design [unb1_test] in RadionHDL
--------------------------------------------------------------
--------------------------------------------------------------
Assuming:
-> ~/RadioHDL --symlink--> ~/svn/UniBoard_FP7/RadioHDL/
-> an empty [build] directory (~/RadioHDL/trunk/build)
-> SOPC mmm
-> Quartus v11.1
Oneclick Commands:
Oneclick Commands:
python
~/RadioHDL/trunk
/tools/oneclick/base/modelsim_config.py
python
$RADIOHDL
/tools/oneclick/base/modelsim_config.py
python
~/RadioHDL/trunk
/tools/oneclick/base/quartus_config.py
python
$RADIOHDL
/tools/oneclick/base/quartus_config.py
-> From here either continue to Modelsim (simulation) or Quartus (synthesis)
-> From here either continue to Modelsim (simulation) or Quartus (synthesis)
...
@@ -19,6 +14,7 @@ Modelsim instructions:
...
@@ -19,6 +14,7 @@ Modelsim instructions:
run_modelsim
run_modelsim
# in Modelsim do:
# in Modelsim do:
rm $UNB/Software/python/sim/*
lp unb1_test
lp unb1_test
mk compile all
mk compile all
# now double click on testbence file
# now double click on testbence file
...
@@ -34,7 +30,7 @@ Quartus instructions (for QSYS):
...
@@ -34,7 +30,7 @@ Quartus instructions (for QSYS):
Convert .sof to .rbf:
Convert .sof to .rbf:
cd
~/RadioHDL/trunk
/build/quartus/unb1_test_qsys/
cd
$RADIOHDL
/build/quartus/unb1_test_qsys/
quartus_cpf -c --option=/tmp/temp_options_file unb1_test_qsys.sof unb1_test_qsys.rbf
quartus_cpf -c --option=/tmp/temp_options_file unb1_test_qsys.sof unb1_test_qsys.rbf
# assuming in /tmp/temp_options_file: Bitstream_compression=on
# assuming in /tmp/temp_options_file: Bitstream_compression=on
...
...
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