Commits · b696ce0ecfc3c57fc89f6df31fd94b2eed93b727 · RTSD / HDL · GitLab

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Nov 14, 2022
- added 72b ddr4 16G IP + example design · b696ce0e
  Reinier van der Walle authored 2 years ago
  
  b696ce0e
Mar 30, 2021
- unb2c fw update · 0332415e
  Kenneth Hiemstra authored 4 years ago
  
  0332415e
Mar 24, 2021
- modelsim IP models · 6887b788
  Kenneth Hiemstra authored 4 years ago
  
  6887b788
Jan 17, 2020
- New IP version e2sg for unb2c using Arria 10AX115U3F45E2SG · f5e8c817
  Jonathan Hargreaves authored 5 years ago
  
  f5e8c817
Sep 25, 2015
- can choose now ddr4 1600 or 2000 · fda9eccc
  Kenneth Hiemstra authored 9 years ago
  
  fda9eccc
Aug 18, 2015
- added ddr4_4g_2000 IP · 08d9a16e
  Kenneth Hiemstra authored 9 years ago
  
  08d9a16e
Aug 13, 2015
- using a dual rank DDR4 but the IP is single rank: disabling 2nd rank by · 0e2b1046
  Kenneth Hiemstra authored 9 years ago
  0e2b1046
Jun 12, 2015
- Connected cal_ok and cal_fail.diff · c85011f5
  Eric Kooistra authored 9 years ago
  
  c85011f5
May 20, 2015
- Updated all IP related files to match Quartus 15.0 which uses libraries with... · 6237fca5
  Eric Kooistra authored 10 years ago
  6237fca5
Apr 08, 2015
- Removed internal DDR memory model (now needs to be instantiated in tb). Use... · 8e1a6162
  Eric Kooistra authored 10 years ago
  8e1a6162
- Rename ctlr_ref_clk into ref_clk to have simpler and more clear name. · f1cda4e0
  Eric Kooistra authored 10 years ago
  
  f1cda4e0
Feb 05, 2015
- svn added missing file. · 6a945baf
  Eric Kooistra authored 10 years ago
  
  6a945baf