Use ip_<device name> directories instead of following the altera/altera_mf library namings.
Move all Altera IP for Stratix IV to ip_stratixiv/ and use prefix ip_stratixiv_<component_name> for the IP files.
Remove xilinx/xilinx_core directory. Instead added ip_virtex4/ directory with empty hdllib.cfg.

Added section 1.4 on clock accurate versus data driven (moved it from the txt file to the doc/pdf)

Added the trails Python scripts made by Daniel van der Schuur (DS) and Harm Jan Pepping (HJP).
Added oneclick_prestudy_readme.txt to keep track of some prestudy meetings and discussions.

The tech_transceiver_gx_stratixiv.vhd is instantiated in tech_transceiver_gx.vhd when g_technology=c_tech_stratixiv.
The tech_transceiver_gx.vhd is the technology independent component for the user.

Use tech_nat_to_mbps_str() from technology_pkg.vhd that is a renamed copy of trnb_nat_to_str() in tr_nonbonded_pkg.vhd.

Ported the gigabit transceiver configuration IP that is used by tr_nonbonded from $UNB to $RADIOHDL.
Renamed the entities and files names to match the naming convention with ip_<ip_lib>_<ip_name> as prefix.
The IP is created for intended_device_family attribute "Stratix IV", so therefor use postfix '_stratixiv'.
In tr_nonbonded for UniBoard1 typically 4, 8 or 12 transceivers are used on each side of the FPGA.
This gxb_reconfig for 2 transceivers is typically intended for PHY simulation with less transceivers.

Ported the gigabit transceiver configuration IP that is used by tr_nonbonded from $UNB to $RADIOHDL.
Renamed the entities and files names to match the naming convention with ip_<ip_lib>_<ip_name> as prefix.
The IP is created for intended_device_family attribute "Stratix IV", so therefor use postfix '_stratixiv'.
In tr_nonbonded for UniBoard1 typically 4, 8 or 12 transceivers are used on each side of the FPGA.

Renamed the entities and files names to match the naming convention with ip_<ip_name>_ as prefix.

Corrected derive_lib_order(), it now uses recursion to keep on reordering the lib_order until it is stable.

- avoids need to compile the model in ip_stratixiv_lib, because it needs to be compiled first and should not be in the synth_files key.
- use model from Numonyx directory in $UNB, instead of the stripped copy in $UNB epcs/tb/vhdl/m25p128_model.
- Numonyx is now part of Micron company, but still keep it in the name.

Compile flash model in synth_files section, because it is used in ip_stratixiv_asmi_parallel.vhd for simulation only.

Renamed altera_mf prefix into using ip_altera_mf prefix. By using extra 'ip_' as prefix it is more clear that it is an IP wrapper between the external IP and the 'tech_' components.

Ported IP for remu (ip_stratixiv_remote_update) and epcs (ip_stratixiv_asmi_parallel) from src/ip in UniBoard to technology/altera/stratixiv and technology/flash in RadioHDL.

Added empty library ip_xilinx_core_lib in technology/xilinx/xilinx_core, to show that the multi technology support works in tech_memory_*.vhd.