Added empty library ip_xilinx_core_lib in technology/xilinx/xilinx_core, to...

Added empty library ip_xilinx_core_lib in technology/xilinx/xilinx_core, to show that the multi technology support works in tech_memory_*.vhd.

libraries/technology/base/technology_pkg.vhd

@@ -27,10 +27,12 @@ PACKAGE technology_pkg IS
 
   -- Technology identifiers
   CONSTANT c_tech_inferred           : INTEGER := 0;
-  CONSTANT c_tech_stratixiv          : INTEGER := 1;
-  CONSTANT c_tech_arria10            : INTEGER := 2;
-  CONSTANT c_tech_stratix10          : INTEGER := 3;
-  CONSTANT c_tech_nof_technologies   : INTEGER := 4;
+  CONSTANT c_tech_virtex4            : INTEGER := 1;   -- e.g. used on RSP3 for Lofar
+  CONSTANT c_tech_stratixiv          : INTEGER := 2;   -- e.g. used on UniBoard1
+  CONSTANT c_tech_virtex6            : INTEGER := 3;   -- e.g. used on Roach2 for Casper
+  CONSTANT c_tech_virtex7            : INTEGER := 4;   -- e.g. used on Roach3 for Casper
+  CONSTANT c_tech_arria10            : INTEGER := 5;   -- e.g. used on UniBoard2
+  CONSTANT c_tech_nof_technologies   : INTEGER := 6;
 
   -- Functions
   FUNCTION tech_sel_a_b(sel : BOOLEAN; a, b : STRING) RETURN STRING;

libraries/technology/memory/hdllib.cfg

 hdl_lib_name = tech_memory
 hdl_library_clause_name = tech_memory_lib
-hdl_lib_uses = technology ip_altera_mf
+hdl_lib_uses = technology ip_altera_mf ip_xilinx_core
 
 build_sim_dir = $HDL_BUILD_DIR
 build_synth_dir = 

libraries/technology/memory/tech_memory_ram_cr_cw.vhd

@@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_altera_mf_lib;
+LIBRARY ip_xilinx_core_lib;
 
 ENTITY tech_memory_ram_cr_cw IS
   GENERIC (

libraries/technology/memory/tech_memory_ram_crw_crw.vhd

@@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_altera_mf_lib;
+LIBRARY ip_xilinx_core_lib;
 
 ENTITY tech_memory_ram_crw_crw IS
   GENERIC (

libraries/technology/memory/tech_memory_ram_crwk_crw.vhd

@@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_altera_mf_lib;
+LIBRARY ip_xilinx_core_lib;
 
 ENTITY tech_memory_ram_crwk_crw IS  -- support different port data widths and corresponding address ranges
   GENERIC (

libraries/technology/memory/tech_memory_ram_r_w.vhd

@@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_altera_mf_lib;
+LIBRARY ip_xilinx_core_lib;
 
 ENTITY tech_memory_ram_r_w IS
   GENERIC (

libraries/technology/memory/tech_memory_rom_r.vhd

@@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_altera_mf_lib;
+LIBRARY ip_xilinx_core_lib;
 
 ENTITY tech_memory_rom_r IS
   GENERIC (

libraries/technology/xilinx/xilinx_core/hdllib.cfg

+hdl_lib_name = ip_xilinx_core
+hdl_library_clause_name = ip_xilinx_core_lib
+hdl_lib_uses = 
+
+build_sim_dir = $HDL_BUILD_DIR
+build_synth_dir = 
+
+synth_files =
+        
+test_bench_files =