Updated oneclick tool flow figure 1 in the pdf.

Added section 1.4 on clock accurate versus data driven (moved it from the txt file to the doc/pdf)

tools/oneclick/prestudy/oneclick_prestudy_readme.txt

@@ -10,34 +10,8 @@ This file keeps some historical notes on the OneClick prestudy results.
   and connect it between 'b' and 'c'. The printed output changes accordingly.
   It's minimal, but hopefully illustrates the concept. 
 
-2) Data driven or RTL accurate, telecon with SA, 15 may 2014
-a)SA are doing trials with MyHDL. They want designers to have access to the RTL
-  without having to know VHDL, because this makes the development feasible
-  for a broad community of engineers like they have now with Matlab/Simulink,
-  and not only to digital engineers. RTL access in Python is what MyHDL
-  provides. MyHDL simulates HDL at the RTL level, i.e. event driven with clocks.
-  The parallel simulation is achieved using sensitivity lists, similar as in
-  VHDL.
-  
-b) Astron wants to model the DSP at the data level, so without the clock. The
-  parallel simulation is not achieved by a sensitivity list and functions that
-  are processed each time an input changes, but instead a function is only 
-  processed when it has sufficient data to calculate its next new output. Hence
-  input data is only processed once. The functions may be mapped on software
-  processes, threads or in a sequential loop. The next investigations focus on
-  using software processes or threads, and on using pipes or queues.
-
-c) MyHDL could be supported in the Astron scheme by treating the MyHDL
-  components as just another source for creating RTL components. Default at
-  Astron we develop our RTL components in VHDL, but one may also start coding
-  in MyHDL and then use the toVHDL() function to convert it to an VHDL
-  component. The advantage of a MyHDL component is that the RTL description
-  in Python can also serve as behavioral model in Python by simply adding 
-  an local clock source (assuming that the RTL description uses the standard
-  MM and ST interfaces). For the VHDL components we manually need to create
-  a model in Python. However this model is typically quite simple.
 
-3) Explorations, 3 june 2014
+2) Explorations, 3 june 2014
   - 7_stream_simplex_2_comp_parallel.py
   Show using software processes and pipes to model components. With 20 processes
   on the 12 core CPU of dop233 this runs much faster then on a quad core CPU.