From f422be4e2712bebd903797796d3bc1b95b3f6bb5 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Tue, 20 Jan 2015 14:59:57 +0000
Subject: [PATCH] Added ip_arria10 DDR4 IP and mem_model.diff
---
libraries/technology/ddr/hdllib.cfg | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/libraries/technology/ddr/hdllib.cfg b/libraries/technology/ddr/hdllib.cfg
index fb025e6048..c2831fecde 100644
--- a/libraries/technology/ddr/hdllib.cfg
+++ b/libraries/technology/ddr/hdllib.cfg
@@ -1,6 +1,12 @@
hdl_lib_name = tech_ddr
hdl_library_clause_name = tech_ddr_lib
-hdl_lib_uses = ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_mem_model common
+hdl_lib_uses = ip_stratixiv_ddr3_uphy_4g_800_master
+ ip_stratixiv_ddr3_uphy_4g_800_slave
+ ip_stratixiv_ddr3_mem_model
+ ip_arria10_ddr4_4g_1600
+ ip_arria10_ddr4_8g_2400
+ ip_arria10_ddr4_mem_model_141
+ common
hdl_lib_technology =
build_dir_sim = $HDL_BUILD_DIR
@@ -10,6 +16,7 @@ synth_files =
tech_ddr_pkg.vhd
tech_ddr_component_pkg.vhd
tech_ddr_stratixiv.vhd
+ tech_ddr_arria10.vhd
tech_ddr_mem_model_component_pkg.vhd
tech_ddr_mem_model.vhd
--
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