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Commit e50aab24 authored by Jonathan Hargreaves's avatar Jonathan Hargreaves
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Modify technology wrappers to include unb2b FPGA Arria 10 version e1sg

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libraries/technology/10gbase_r/hdllib.cfg
+ 22
− 11
View file @ e50aab24
hdl_lib_name = tech_10gbase_r hdl_lib_name = tech_10gbase_r
hdl_library_clause_name = tech_10gbase_r_lib hdl_library_clause_name = tech_10gbase_r_lib
hdl_lib_uses_synth = technology common tech_pll tech_transceiver hdl_lib_uses_synth = technology common tech_pll tech_transceiver
hdl_lib_uses_ip = ip_arria10_phy_10gbase_r ip_arria10_e3sge3_phy_10gbase_r hdl_lib_uses_ip = ip_arria10_phy_10gbase_r ip_arria10_e3sge3_phy_10gbase_r ip_arria10_e1sg_phy_10gbase_r
ip_arria10_phy_10gbase_r_4 ip_arria10_e3sge3_phy_10gbase_r_4 ip_arria10_phy_10gbase_r_4 ip_arria10_e3sge3_phy_10gbase_r_4 ip_arria10_e1sg_phy_10gbase_r_4
ip_arria10_phy_10gbase_r_12 ip_arria10_e3sge3_phy_10gbase_r_12 ip_arria10_phy_10gbase_r_12 ip_arria10_e3sge3_phy_10gbase_r_12 ip_arria10_e1sg_phy_10gbase_r_12
ip_arria10_phy_10gbase_r_24 ip_arria10_e3sge3_phy_10gbase_r_24 ip_arria10_phy_10gbase_r_24 ip_arria10_e3sge3_phy_10gbase_r_24 ip_arria10_e1sg_phy_10gbase_r_24
ip_arria10_phy_10gbase_r_48 ip_arria10_e3sge3_phy_10gbase_r_48 ip_arria10_phy_10gbase_r_48 ip_arria10_e3sge3_phy_10gbase_r_48 ip_arria10_e1sg_phy_10gbase_r_48
ip_arria10_transceiver_pll_10g ip_arria10_e3sge3_transceiver_pll_10g ip_arria10_transceiver_pll_10g ip_arria10_e3sge3_transceiver_pll_10g ip_arria10_e1sg_transceiver_pll_10g
ip_arria10_transceiver_reset_controller_1 ip_arria10_e3sge3_transceiver_reset_controller_1 ip_arria10_transceiver_reset_controller_1 ip_arria10_e3sge3_transceiver_reset_controller_1 ip_arria10_e1sg_transceiver_reset_controller_1
ip_arria10_transceiver_reset_controller_4 ip_arria10_e3sge3_transceiver_reset_controller_4 ip_arria10_transceiver_reset_controller_4 ip_arria10_e3sge3_transceiver_reset_controller_4 ip_arria10_e1sg_transceiver_reset_controller_4
ip_arria10_transceiver_reset_controller_12 ip_arria10_e3sge3_transceiver_reset_controller_12 ip_arria10_transceiver_reset_controller_12 ip_arria10_e3sge3_transceiver_reset_controller_12 ip_arria10_e1sg_transceiver_reset_controller_12
ip_arria10_transceiver_reset_controller_24 ip_arria10_e3sge3_transceiver_reset_controller_24 ip_arria10_transceiver_reset_controller_24 ip_arria10_e3sge3_transceiver_reset_controller_24 ip_arria10_e1sg_transceiver_reset_controller_24
ip_arria10_transceiver_reset_controller_48 ip_arria10_e3sge3_transceiver_reset_controller_48 ip_arria10_transceiver_reset_controller_48 ip_arria10_e3sge3_transceiver_reset_controller_48 ip_arria10_e1sg_transceiver_reset_controller_48
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = hdl_lib_technology =
hdl_lib_disclose_library_clause_names = hdl_lib_disclose_library_clause_names =
...@@ -37,12 +37,23 @@ hdl_lib_disclose_library_clause_names = ...@@ -37,12 +37,23 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e3sge3_transceiver_reset_controller_12 ip_arria10_e3sge3_transceiver_reset_controller_12_altera_xcvr_reset_control_151 ip_arria10_e3sge3_transceiver_reset_controller_12 ip_arria10_e3sge3_transceiver_reset_controller_12_altera_xcvr_reset_control_151
ip_arria10_e3sge3_transceiver_reset_controller_24 ip_arria10_e3sge3_transceiver_reset_controller_24_altera_xcvr_reset_control_151 ip_arria10_e3sge3_transceiver_reset_controller_24 ip_arria10_e3sge3_transceiver_reset_controller_24_altera_xcvr_reset_control_151
ip_arria10_e3sge3_transceiver_reset_controller_48 ip_arria10_e3sge3_transceiver_reset_controller_48_altera_xcvr_reset_control_151 ip_arria10_e3sge3_transceiver_reset_controller_48 ip_arria10_e3sge3_transceiver_reset_controller_48_altera_xcvr_reset_control_151
ip_arria10_e1sg_phy_10gbase_r ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_151
ip_arria10_e1sg_phy_10gbase_r_4 ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_151
ip_arria10_e1sg_phy_10gbase_r_12 ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_151
ip_arria10_e1sg_phy_10gbase_r_24 ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_151
ip_arria10_e1sg_phy_10gbase_r_48 ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_151
ip_arria10_e1sg_transceiver_pll_10g ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151
ip_arria10_e1sg_transceiver_reset_controller_1 ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_151
ip_arria10_e1sg_transceiver_reset_controller_4 ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_151
ip_arria10_e1sg_transceiver_reset_controller_12 ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_151
ip_arria10_e1sg_transceiver_reset_controller_24 ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_151
synth_files = synth_files =
sim_10gbase_r.vhd sim_10gbase_r.vhd
tech_10gbase_r_component_pkg.vhd tech_10gbase_r_component_pkg.vhd
tech_10gbase_r_arria10.vhd tech_10gbase_r_arria10.vhd
tech_10gbase_r_arria10_e3sge3.vhd tech_10gbase_r_arria10_e3sge3.vhd
tech_10gbase_r_arria10_e1sg.vhd
tech_10gbase_r.vhd tech_10gbase_r.vhd
test_bench_files = test_bench_files =
......
libraries/technology/10gbase_r/tech_10gbase_r.vhd
+ 9
− 0
View file @ e50aab24
...@@ -80,6 +80,15 @@ BEGIN ...@@ -80,6 +80,15 @@ BEGIN
tx_serial_arr, rx_serial_arr); tx_serial_arr, rx_serial_arr);
END GENERATE; END GENERATE;
gen_ip_arria10_e1sg : IF c_use_technology=TRUE AND g_technology=c_tech_arria10_e1sg GENERATE
u0 : ENTITY work.tech_10gbase_r_arria10_e1sg
GENERIC MAP (g_sim, g_nof_channels)
PORT MAP (tr_ref_clk_644,
clk_156, rst_156,
xgmii_tx_ready_arr, xgmii_rx_ready_arr, xgmii_tx_dc_arr, xgmii_rx_dc_arr,
tx_serial_arr, rx_serial_arr);
END GENERATE;
gem_sim_10gbase_r : IF c_use_sim_model=TRUE GENERATE gem_sim_10gbase_r : IF c_use_sim_model=TRUE GENERATE
u0 : ENTITY work.sim_10gbase_r u0 : ENTITY work.sim_10gbase_r
GENERIC MAP (g_sim, g_nof_channels) GENERIC MAP (g_sim, g_nof_channels)
......
libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd 0 → 100644
+ 556
− 0
View file @ e50aab24
This diff is collapsed.
libraries/technology/clkbuf/hdllib.cfg
+ 2
− 1
View file @ e50aab24
hdl_lib_name = tech_clkbuf hdl_lib_name = tech_clkbuf
hdl_library_clause_name = tech_clkbuf_lib hdl_library_clause_name = tech_clkbuf_lib
hdl_lib_uses_synth = technology common hdl_lib_uses_synth = technology common
hdl_lib_uses_ip = ip_arria10_clkbuf_global ip_arria10_e3sge3_clkbuf_global hdl_lib_uses_ip = ip_arria10_clkbuf_global ip_arria10_e3sge3_clkbuf_global ip_arria10_e1sg_clkbuf_global
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = hdl_lib_technology =
hdl_lib_disclose_library_clause_names = hdl_lib_disclose_library_clause_names =
ip_arria10_clkbuf_global ip_arria10_clkbuf_global_altclkctrl_150 ip_arria10_clkbuf_global ip_arria10_clkbuf_global_altclkctrl_150
ip_arria10_e3sge3_clkbuf_global ip_arria10_e3sge3_clkbuf_global_altclkctrl_151 ip_arria10_e3sge3_clkbuf_global ip_arria10_e3sge3_clkbuf_global_altclkctrl_151
ip_arria10_e1sg_clkbuf_global ip_arria10_e1sg_clkbuf_global_altclkctrl_151
synth_files = synth_files =
tech_clkbuf_component_pkg.vhd tech_clkbuf_component_pkg.vhd
......
libraries/technology/clkbuf/tech_clkbuf.vhd
+ 14
− 0
View file @ e50aab24
...@@ -28,6 +28,7 @@ USE technology_lib.technology_select_pkg.ALL; ...@@ -28,6 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis. -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_clkbuf_global_altclkctrl_150; LIBRARY ip_arria10_clkbuf_global_altclkctrl_150;
LIBRARY ip_arria10_e3sge3_clkbuf_global_altclkctrl_151; LIBRARY ip_arria10_e3sge3_clkbuf_global_altclkctrl_151;
LIBRARY ip_arria10_e1sg_clkbuf_global_altclkctrl_151;
ENTITY tech_clkbuf IS ENTITY tech_clkbuf IS
GENERIC ( GENERIC (
...@@ -67,4 +68,17 @@ BEGIN ...@@ -67,4 +68,17 @@ BEGIN
outclk => outclk -- outclk outclk => outclk -- outclk
); );
END GENERATE; END GENERATE;
-----------------------------------------------------------------------------
-- ip_arria10_e1sg
-----------------------------------------------------------------------------
gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg AND g_clock_net="GLOBAL" GENERATE
u0 : ip_arria10_e1sg_clkbuf_global
PORT MAP (
inclk => inclk, -- inclk
outclk => outclk -- outclk
);
END GENERATE;
END ARCHITECTURE; END ARCHITECTURE;
libraries/technology/clkbuf/tech_clkbuf_component_pkg.vhd
+ 11
− 0
View file @ e50aab24
...@@ -49,5 +49,16 @@ PACKAGE tech_clkbuf_component_pkg IS ...@@ -49,5 +49,16 @@ PACKAGE tech_clkbuf_component_pkg IS
); );
END COMPONENT; END COMPONENT;
-----------------------------------------------------------------------------
-- ip_arria10_e1sg
-----------------------------------------------------------------------------
COMPONENT ip_arria10_e1sg_clkbuf_global IS
PORT (
inclk : in std_logic := '0'; -- altclkctrl_input.inclk
outclk : out std_logic -- altclkctrl_output.outclk
);
END COMPONENT;
END tech_clkbuf_component_pkg; END tech_clkbuf_component_pkg;
libraries/technology/ddr/hdllib.cfg
+ 9
− 0
View file @ e50aab24
...@@ -13,6 +13,10 @@ hdl_lib_uses_ip = ip_stratixiv_ddr3_uphy_4g_800_master ...@@ -13,6 +13,10 @@ hdl_lib_uses_ip = ip_stratixiv_ddr3_uphy_4g_800_master
ip_arria10_e3sge3_ddr4_8g_1600 ip_arria10_e3sge3_ddr4_8g_1600
ip_arria10_e3sge3_ddr4_4g_2000 ip_arria10_e3sge3_ddr4_4g_2000
ip_arria10_e3sge3_ddr4_8g_2400 ip_arria10_e3sge3_ddr4_8g_2400
ip_arria10_e1sg_ddr4_4g_1600
ip_arria10_e1sg_ddr4_8g_1600
ip_arria10_e1sg_ddr4_4g_2000
ip_arria10_e1sg_ddr4_8g_2400
hdl_lib_uses_sim = ip_stratixiv_ddr3_mem_model hdl_lib_uses_sim = ip_stratixiv_ddr3_mem_model
ip_arria10_ddr4_mem_model_141 ip_arria10_ddr4_mem_model_141
hdl_lib_technology = hdl_lib_technology =
...@@ -29,6 +33,10 @@ hdl_lib_disclose_library_clause_names = ...@@ -29,6 +33,10 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e3sge3_ddr4_8g_1600 ip_arria10_e3sge3_ddr4_8g_1600_altera_emif_151 ip_arria10_e3sge3_ddr4_8g_1600 ip_arria10_e3sge3_ddr4_8g_1600_altera_emif_151
ip_arria10_e3sge3_ddr4_4g_2000 ip_arria10_e3sge3_ddr4_4g_2000_altera_emif_151 ip_arria10_e3sge3_ddr4_4g_2000 ip_arria10_e3sge3_ddr4_4g_2000_altera_emif_151
ip_arria10_e3sge3_ddr4_8g_2400 ip_arria10_e3sge3_ddr4_8g_2400_altera_emif_151 ip_arria10_e3sge3_ddr4_8g_2400 ip_arria10_e3sge3_ddr4_8g_2400_altera_emif_151
ip_arria10_e1sg_ddr4_4g_1600 ip_arria10_e1sg_ddr4_4g_1600_altera_emif_151
ip_arria10_e1sg_ddr4_8g_1600 ip_arria10_e1sg_ddr4_8g_1600_altera_emif_151
ip_arria10_e1sg_ddr4_4g_2000 ip_arria10_e1sg_ddr4_4g_2000_altera_emif_151
ip_arria10_e1sg_ddr4_8g_2400 ip_arria10_e1sg_ddr4_8g_2400_altera_emif_151
ip_stratixiv_ddr3_mem_model ip_stratixiv_ddr3_mem_model_lib ip_stratixiv_ddr3_mem_model ip_stratixiv_ddr3_mem_model_lib
ip_arria10_ddr4_mem_model_141 ip_arria10_ddr4_mem_model_141 ip_arria10_ddr4_mem_model_141 ip_arria10_ddr4_mem_model_141
...@@ -39,6 +47,7 @@ synth_files = ...@@ -39,6 +47,7 @@ synth_files =
tech_ddr_stratixiv.vhd tech_ddr_stratixiv.vhd
tech_ddr_arria10.vhd tech_ddr_arria10.vhd
tech_ddr_arria10_e3sge3.vhd tech_ddr_arria10_e3sge3.vhd
tech_ddr_arria10_e1sg.vhd
tech_ddr.vhd tech_ddr.vhd
test_bench_files = test_bench_files =
......
libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd 0 → 100644
+ 262
− 0
View file @ e50aab24
--------------------------------------------------------------------------------
--
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--------------------------------------------------------------------------------
-- Purpose: DDR4 memory access component for Arria10.
-- Description:
-- Remarks:
-- . The local_init_done goes high some time after power up. It could have been
-- AND-ed with ctlr_miso.waitrequest_n. However the timing closure for
-- ctlr_miso.waitrequest_n can be critical, so therefore it is better not
-- to combinatorially load it with the AND local_init_done. Instead a
-- ctlr_miso.done field was added and used to pass on local_init_done. In fact
-- for normal operation it is sufficient to only wait for
-- ctlr_miso.waitrequest_n. The ctlr_miso.init_done is then only used for
-- DDR interface monitoring purposes.
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_e1sg_ddr4_4g_1600_altera_emif_151;
LIBRARY ip_arria10_e1sg_ddr4_8g_1600_altera_emif_151;
LIBRARY ip_arria10_e1sg_ddr4_4g_2000_altera_emif_151;
LIBRARY ip_arria10_e1sg_ddr4_8g_2400_altera_emif_151;
LIBRARY IEEE, technology_lib, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE work.tech_ddr_pkg.ALL;
USE work.tech_ddr_component_pkg.ALL;
ENTITY tech_ddr_arria10_e1sg IS
GENERIC (
g_tech_ddr : t_c_tech_ddr
);
PORT (
-- PLL reference clock
ref_clk : IN STD_LOGIC;
ref_rst : IN STD_LOGIC;
-- Controller user interface
ctlr_gen_clk : OUT STD_LOGIC;
ctlr_gen_rst : OUT STD_LOGIC;
ctlr_mosi : IN t_mem_ctlr_mosi;
ctlr_miso : OUT t_mem_ctlr_miso;
-- PHY interface
phy_in : IN t_tech_ddr4_phy_in;
phy_io : INOUT t_tech_ddr4_phy_io;
phy_ou : OUT t_tech_ddr4_phy_ou
);
END tech_ddr_arria10_e1sg;
ARCHITECTURE str OF tech_ddr_arria10_e1sg IS
CONSTANT c_gigabytes : NATURAL := func_tech_ddr_module_size(g_tech_ddr);
CONSTANT c_ctlr_address_w : NATURAL := func_tech_ddr_ctlr_address_w(g_tech_ddr);
CONSTANT c_ctlr_data_w : NATURAL := 576;--func_tech_ddr_ctlr_data_w( g_tech_ddr);
SIGNAL i_ctlr_gen_clk : STD_LOGIC;
SIGNAL ref_rst_n : STD_LOGIC;
SIGNAL ctlr_gen_rst_n : STD_LOGIC := '0';
SIGNAL local_cal_success : STD_LOGIC;
SIGNAL local_cal_fail : STD_LOGIC;
BEGIN
ctlr_gen_clk <= i_ctlr_gen_clk;
ref_rst_n <= NOT ref_rst;
ctlr_gen_rst <= NOT ctlr_gen_rst_n;
gen_ip_arria10_e1sg_ddr4_4g_2000 : IF g_tech_ddr.name="DDR4" AND c_gigabytes=4 AND g_tech_ddr.mts=2000 GENERATE
phy_ou.cs_n(1) <= '1';
phy_ou.cke(1) <= '0';
phy_ou.odt(1) <= '0';
u_ip_arria10_e1sg_ddr4_4g_2000 : ip_arria10_e1sg_ddr4_4g_2000
PORT MAP (
amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
amm_read_0 => ctlr_mosi.rd, -- .read
amm_write_0 => ctlr_mosi.wr, -- .write
amm_address_0 => ctlr_mosi.address(c_ctlr_address_w-1 DOWNTO 0), -- .address
amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w-1 DOWNTO 0), -- .readdata
amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w-1 DOWNTO 0), -- .writedata
amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w-1 DOWNTO 0), -- .burstcount
amm_byteenable_0 => (OTHERS=>'1'), -- .byteenable
amm_readdatavalid_0 => ctlr_miso.rdval, -- .readdatavalid
emif_usr_clk => i_ctlr_gen_clk, -- emif_usr_clk_clock_source.clk
emif_usr_reset_n => ctlr_gen_rst_n, -- emif_usr_reset_reset_source.reset_n
global_reset_n => ref_rst_n, -- global_reset_reset_sink.reset_n
mem_ck => phy_ou.ck(g_tech_ddr.ck_w-1 DOWNTO 0), -- mem_conduit_end.mem_ck
mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck_n
mem_a => phy_ou.a(g_tech_ddr.a_w-1 DOWNTO 0), -- .mem_a
sl(mem_act_n) => phy_ou.act_n, -- .mem_act_n
mem_ba => phy_ou.ba(g_tech_ddr.ba_w-1 DOWNTO 0), -- .mem_ba
mem_bg => phy_ou.bg(g_tech_ddr.bg_w-1 DOWNTO 0), -- .mem_bg
mem_cke => phy_ou.cke(g_tech_ddr.cke_w-1 DOWNTO 0), -- .mem_cke
mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n
mem_odt => phy_ou.odt(g_tech_ddr.odt_w-1 DOWNTO 0), -- .mem_odt
sl(mem_reset_n) => phy_ou.reset_n, -- .mem_reset_n
sl(mem_par) => phy_ou.par, -- .mem_par
mem_alert_n => slv(phy_in.alert_n), -- .mem_alert_n
mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs
mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n
mem_dq => phy_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- .mem_dq
mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w-1 DOWNTO 0), -- .mem_dbi_n
oct_rzqin => phy_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
pll_ref_clk => ref_clk, -- pll_ref_clk_clock_sink.clk
local_cal_success => local_cal_success, -- status_conduit_end.local_cal_success
local_cal_fail => local_cal_fail -- .local_cal_fail
);
-- Signals in DDR3 that are not available with DDR4:
--
--avl_burstbegin => ctlr_mosi.burstbegin, -- .beginbursttransfer
-- beginbursttransfer is obselete for new Avalon designs, because the slave can count valid data itself to know when a new burst starts
--
--local_init_done => ctlr_miso.done, -- status.local_init_done
-- local_init_done = ctlr_init_done originally and mapped to ctlr_miso.done for the DDR3 IP. For the DDR4 IP the local_cal_success and
-- NOT local_cal_fail seem to serve as local_init_done
ctlr_miso.done <= local_cal_success AND NOT local_cal_fail WHEN rising_edge(i_ctlr_gen_clk);
ctlr_miso.cal_ok <= local_cal_success;
ctlr_miso.cal_fail <= local_cal_fail;
END GENERATE;
gen_ip_arria10_e1sg_ddr4_4g_1600 : IF g_tech_ddr.name="DDR4" AND c_gigabytes=4 AND g_tech_ddr.mts=1600 GENERATE
phy_ou.cs_n(1) <= '1';
phy_ou.cke(1) <= '0';
phy_ou.odt(1) <= '0';
u_ip_arria10_e1sg_ddr4_4g_1600 : ip_arria10_e1sg_ddr4_4g_1600
PORT MAP (
amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
amm_read_0 => ctlr_mosi.rd, -- .read
amm_write_0 => ctlr_mosi.wr, -- .write
amm_address_0 => ctlr_mosi.address(c_ctlr_address_w-1 DOWNTO 0), -- .address
amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w-1 DOWNTO 0), -- .readdata
amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w-1 DOWNTO 0), -- .writedata
amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w-1 DOWNTO 0), -- .burstcount
amm_byteenable_0 => (OTHERS=>'1'), -- .byteenable
amm_readdatavalid_0 => ctlr_miso.rdval, -- .readdatavalid
emif_usr_clk => i_ctlr_gen_clk, -- emif_usr_clk_clock_source.clk
emif_usr_reset_n => ctlr_gen_rst_n, -- emif_usr_reset_reset_source.reset_n
global_reset_n => ref_rst_n, -- global_reset_reset_sink.reset_n
mem_ck => phy_ou.ck(g_tech_ddr.ck_w-1 DOWNTO 0), -- mem_conduit_end.mem_ck
mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck_n
mem_a => phy_ou.a(g_tech_ddr.a_w-1 DOWNTO 0), -- .mem_a
sl(mem_act_n) => phy_ou.act_n, -- .mem_act_n
mem_ba => phy_ou.ba(g_tech_ddr.ba_w-1 DOWNTO 0), -- .mem_ba
mem_bg => phy_ou.bg(g_tech_ddr.bg_w-1 DOWNTO 0), -- .mem_bg
mem_cke => phy_ou.cke(g_tech_ddr.cke_w-1 DOWNTO 0), -- .mem_cke
mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n
mem_odt => phy_ou.odt(g_tech_ddr.odt_w-1 DOWNTO 0), -- .mem_odt
sl(mem_reset_n) => phy_ou.reset_n, -- .mem_reset_n
sl(mem_par) => phy_ou.par, -- .mem_par
mem_alert_n => slv(phy_in.alert_n), -- .mem_alert_n
mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs
mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n
mem_dq => phy_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- .mem_dq
mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w-1 DOWNTO 0), -- .mem_dbi_n
oct_rzqin => phy_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
pll_ref_clk => ref_clk, -- pll_ref_clk_clock_sink.clk
local_cal_success => local_cal_success, -- status_conduit_end.local_cal_success
local_cal_fail => local_cal_fail -- .local_cal_fail
);
-- Signals in DDR3 that are not available with DDR4:
--
--avl_burstbegin => ctlr_mosi.burstbegin, -- .beginbursttransfer
-- beginbursttransfer is obselete for new Avalon designs, because the slave can count valid data itself to know when a new burst starts
--
--local_init_done => ctlr_miso.done, -- status.local_init_done
-- local_init_done = ctlr_init_done originally and mapped to ctlr_miso.done for the DDR3 IP. For the DDR4 IP the local_cal_success and
-- NOT local_cal_fail seem to serve as local_init_done
ctlr_miso.done <= local_cal_success AND NOT local_cal_fail WHEN rising_edge(i_ctlr_gen_clk);
ctlr_miso.cal_ok <= local_cal_success;
ctlr_miso.cal_fail <= local_cal_fail;
END GENERATE;
gen_ip_arria10_e1sg_ddr4_8g_1600 : IF g_tech_ddr.name="DDR4" AND c_gigabytes=8 AND g_tech_ddr.mts=1600 GENERATE
u_ip_arria10_e1sg_ddr4_8g_1600 : ip_arria10_e1sg_ddr4_8g_1600
PORT MAP (
amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
amm_read_0 => ctlr_mosi.rd, -- .read
amm_write_0 => ctlr_mosi.wr, -- .write
amm_address_0 => ctlr_mosi.address(c_ctlr_address_w-1 DOWNTO 0), -- .address
amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w-1 DOWNTO 0), -- .readdata
amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w-1 DOWNTO 0), -- .writedata
amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w-1 DOWNTO 0), -- .burstcount
amm_byteenable_0 => (OTHERS=>'1'), -- .byteenable
amm_readdatavalid_0 => ctlr_miso.rdval, -- .readdatavalid
emif_usr_clk => i_ctlr_gen_clk, -- emif_usr_clk_clock_source.clk
emif_usr_reset_n => ctlr_gen_rst_n, -- emif_usr_reset_reset_source.reset_n
global_reset_n => ref_rst_n, -- global_reset_reset_sink.reset_n
mem_ck => phy_ou.ck(g_tech_ddr.ck_w-1 DOWNTO 0), -- mem_conduit_end.mem_ck
mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck_n
mem_a => phy_ou.a(g_tech_ddr.a_w-1 DOWNTO 0), -- .mem_a
sl(mem_act_n) => phy_ou.act_n, -- .mem_act_n
mem_ba => phy_ou.ba(g_tech_ddr.ba_w-1 DOWNTO 0), -- .mem_ba
mem_bg => phy_ou.bg(g_tech_ddr.bg_w-1 DOWNTO 0), -- .mem_bg
mem_cke => phy_ou.cke(g_tech_ddr.cke_w-1 DOWNTO 0), -- .mem_cke
mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n
mem_odt => phy_ou.odt(g_tech_ddr.odt_w-1 DOWNTO 0), -- .mem_odt
sl(mem_reset_n) => phy_ou.reset_n, -- .mem_reset_n
sl(mem_par) => phy_ou.par, -- .mem_par
mem_alert_n => slv(phy_in.alert_n), -- .mem_alert_n
mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs
mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n
mem_dq => phy_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- .mem_dq
mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w-1 DOWNTO 0), -- .mem_dbi_n
oct_rzqin => phy_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
pll_ref_clk => ref_clk, -- pll_ref_clk_clock_sink.clk
local_cal_success => local_cal_success, -- status_conduit_end.local_cal_success
local_cal_fail => local_cal_fail -- .local_cal_fail
);
-- Signals in DDR3 that are not available with DDR4:
--
--avl_burstbegin => ctlr_mosi.burstbegin, -- .beginbursttransfer
-- beginbursttransfer is obselete for new Avalon designs, because the slave can count valid data itself to know when a new burst starts
--
--local_init_done => ctlr_miso.done, -- status.local_init_done
-- local_init_done = ctlr_init_done originally and mapped to ctlr_miso.done for the DDR3 IP. For the DDR4 IP the local_cal_success and
-- NOT local_cal_fail seem to serve as local_init_done
ctlr_miso.done <= local_cal_success AND NOT local_cal_fail WHEN rising_edge(i_ctlr_gen_clk);
ctlr_miso.cal_ok <= local_cal_success;
ctlr_miso.cal_fail <= local_cal_fail;
END GENERATE;
END str;
libraries/technology/ddr/tech_ddr_component_pkg.vhd
+ 118
− 0
View file @ e50aab24
...@@ -487,6 +487,124 @@ PACKAGE tech_ddr_component_pkg IS ...@@ -487,6 +487,124 @@ PACKAGE tech_ddr_component_pkg IS
); );
END COMPONENT; END COMPONENT;
------------------------------------------------------------------------------
-- ip_arria10_e1sg
------------------------------------------------------------------------------
-- Manually derived VHDL entity from VHDL file $RADIOHDL/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim/ip_arria10_e1sg_ddr4_4g_1600.vhd
COMPONENT ip_arria10_e1sg_ddr4_4g_1600 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
amm_read_0 : in std_logic := '0'; -- .read
amm_write_0 : in std_logic := '0'; -- .write
amm_address_0 : in std_logic_vector(25 downto 0) := (others => '0'); -- .address
amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
amm_readdatavalid_0 : out std_logic; -- .readdatavalid
emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
mem_ck : out std_logic_vector(0 downto 0); -- mem_conduit_end.mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n
mem_a : out std_logic_vector(16 downto 0); -- .mem_a
mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
mem_par : out std_logic_vector(0 downto 0); -- .mem_par
mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
local_cal_fail : out std_logic -- .local_cal_fail
);
END COMPONENT;
-- Dual rank version of ip_arria10_e1sg_ddr4_4g_1600.vhd
COMPONENT ip_arria10_e1sg_ddr4_8g_1600 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
amm_read_0 : in std_logic := '0'; -- .read
amm_write_0 : in std_logic := '0'; -- .write
amm_address_0 : in std_logic_vector(26 downto 0) := (others => '0'); -- .address
amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
amm_readdatavalid_0 : out std_logic; -- .readdatavalid
emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
mem_ck : out std_logic_vector(1 downto 0); -- mem_conduit_end.mem_ck
mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
mem_a : out std_logic_vector(16 downto 0); -- .mem_a
mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
mem_cke : out std_logic_vector(1 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(1 downto 0); -- .mem_cs_n
mem_odt : out std_logic_vector(1 downto 0); -- .mem_odt
mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
mem_par : out std_logic_vector(0 downto 0); -- .mem_par
mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
local_cal_fail : out std_logic -- .local_cal_fail
);
END COMPONENT;
-- Manually derived VHDL entity from VHDL file $RADIOHDL/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim/ip_arria10_e1sg_ddr4_4g_2000.vhd
COMPONENT ip_arria10_e1sg_ddr4_4g_2000 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
amm_read_0 : in std_logic := '0'; -- .read
amm_write_0 : in std_logic := '0'; -- .write
amm_address_0 : in std_logic_vector(25 downto 0) := (others => '0'); -- .address
amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
amm_readdatavalid_0 : out std_logic; -- .readdatavalid
emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
mem_ck : out std_logic_vector(0 downto 0); -- mem_conduit_end.mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n
mem_a : out std_logic_vector(16 downto 0); -- .mem_a
mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
mem_par : out std_logic_vector(0 downto 0); -- .mem_par
mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
local_cal_fail : out std_logic -- .local_cal_fail
);
END COMPONENT;
END tech_ddr_component_pkg; END tech_ddr_component_pkg;
PACKAGE BODY tech_ddr_component_pkg IS PACKAGE BODY tech_ddr_component_pkg IS
......
libraries/technology/eth_10g/hdllib.cfg
+ 1
− 0
View file @ e50aab24
...@@ -8,6 +8,7 @@ synth_files = ...@@ -8,6 +8,7 @@ synth_files =
tech_eth_10g_stratixiv.vhd tech_eth_10g_stratixiv.vhd
tech_eth_10g_arria10.vhd tech_eth_10g_arria10.vhd
tech_eth_10g_arria10_e3sge3.vhd tech_eth_10g_arria10_e3sge3.vhd
tech_eth_10g_arria10_e1sg.vhd
tech_eth_10g_clocks.vhd tech_eth_10g_clocks.vhd
tech_eth_10g.vhd tech_eth_10g.vhd
......
libraries/technology/eth_10g/tech_eth_10g.vhd
+ 42
− 0
View file @ e50aab24
...@@ -258,4 +258,46 @@ BEGIN ...@@ -258,4 +258,46 @@ BEGIN
serial_rx_arr => serial_rx_arr serial_rx_arr => serial_rx_arr
); );
END GENERATE; END GENERATE;
gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
u0 : ENTITY work.tech_eth_10g_arria10_e1sg
GENERIC MAP (
g_sim => g_sim,
g_sim_level => g_sim_level,
g_nof_channels => g_nof_channels,
g_direction => g_direction,
g_pre_header_padding => g_pre_header_padding
)
PORT MAP (
-- Transceiver PLL reference clock
tr_ref_clk_644 => tr_ref_clk_644,
-- Data clocks
clk_312 => tr_ref_clk_312,
clk_156 => tr_ref_clk_156,
rst_156 => tr_ref_rst_156,
-- MM
mm_clk => mm_clk,
mm_rst => mm_rst,
mac_mosi => mac_mosi,
mac_miso => mac_miso,
reg_eth10g_mosi => reg_eth10g_mosi,
reg_eth10g_miso => reg_eth10g_miso,
-- ST
tx_snk_in_arr => tx_snk_in_arr, -- 64 bit data @ tr_ref_clk_156
tx_snk_out_arr => tx_snk_out_arr,
rx_src_out_arr => rx_src_out_arr, -- 64 bit data @ tr_ref_clk_156
rx_src_in_arr => rx_src_in_arr,
-- Serial
serial_tx_arr => serial_tx_arr,
serial_rx_arr => serial_rx_arr
);
END GENERATE;
END str; END str;
libraries/technology/eth_10g/tech_eth_10g_arria10_e1sg.vhd 0 → 100644
+ 314
− 0
View file @ e50aab24
--------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--------------------------------------------------------------------------------
-- Purpose: Combine mac_10g and 10gbase_r for c_tech_arria10_e1sg
-- Description
--
-- The clocks come from an external central fPLL:
--
-- tx_ref_clk_644 --> fPLL --> clk_312
-- clk_156, rst_156
-- Blockdiagram:
--
-- 312 156 644
-- _________ | | | ____________
-- | | | | | | |
-- | |<--/ | \-->| |
-- | |<-----+----->| |
-- | | | |
-- | | XGMII | |
-- tx_snk --->|tech_ |------------>|tech_ |---> serial_tx
-- rx_src <---|mac_10g|<------------|10gbase_r |<--- serial_rx
-- | | | |
-- |_______|--\ /--|__________|
-- | | |
-- mac_mm | |
-- | v
-- ( v xgmii_tx_ready)
-- tx_snk_out.xon <--(xgmii_link_status[1:0])
--
-- . g_direction:
-- "TX_RX" = Default support bidir
-- "TX_ONLY" = Uses a bidir MAC and connects the MAC Tx to the MAC RX.
-- "RX_ONLY" = Same as "TX_RX"
-- See tech_eth_10g_stratixiv.vhd for more details.
--
-- Remarks:
-- . xgmii_link_status:
-- When the xgmii_tx_ready from the 10gbase_r and the xgmii_link_status from
-- the mac_10g are both be OK then the tx_snk.xon is asserted to allow the
-- user data transmission.
-- The tb_tech_eth_10g reveals that xgmii_tx_ready goes high after some power
-- up time and then remains active independent of link_fault.
-- A link fault eg. due to rx disconnect is detected by the link fault status:
-- 0 = OK
-- 1 = local fault
-- 2 = remote fault
--
-- From google search:
-- Link fault Operation
-- 1) Device B detects loss of signal. Local fault is signaled by PHY of Device B to Device B.
-- 2) Device B ceases transmission of MAC frames and transmits remote fault to Device A.
-- 3) Device A receives remote fault from Device B.
-- 4) Device A stops sending frames, continuously generates Idle.
--
-- Hence when the xgmii_link_status is OK then the other side is also OK so
-- then it is also appropriate to release tx_snk.xon.
--
-- The XGMII link status can be monitored via the reg_eth10 MM register:
--
-- addr data[31:0]
-- 0 [0] = tx_snk_out_arr(I).xon
-- [1] = xgmii_tx_ready_arr(I)
-- [3:2] = xgmii_link_status_arr(I)
--
LIBRARY IEEE, common_lib, dp_lib, technology_lib, tech_10gbase_r_lib, tech_mac_10g_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE technology_lib.technology_pkg.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_interface_layers_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE tech_mac_10g_lib.tech_mac_10g_component_pkg.ALL;
ENTITY tech_eth_10g_arria10_e1sg IS
GENERIC (
g_sim : BOOLEAN := FALSE;
g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model
g_nof_channels : NATURAL := 1;
g_direction : STRING := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
g_pre_header_padding : BOOLEAN := FALSE
);
PORT (
-- Transceiver PLL reference clock
tr_ref_clk_644 : IN STD_LOGIC := '0'; -- 644.531250 MHz for 10GBASE-R
-- Data clocks
clk_312 : IN STD_LOGIC := '0';
clk_156 : IN STD_LOGIC := '0';
rst_156 : IN STD_LOGIC := '0';
-- MM
mm_clk : IN STD_LOGIC;
mm_rst : IN STD_LOGIC;
mac_mosi : IN t_mem_mosi; -- MAG_10G (CSR)
mac_miso : OUT t_mem_miso;
reg_eth10g_mosi : IN t_mem_mosi; -- ETH10G (link status register)
reg_eth10g_miso : OUT t_mem_miso;
-- ST
tx_snk_in_arr : IN t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ clk_156
tx_snk_out_arr : OUT t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ clk_156
rx_src_in_arr : IN t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
-- Serial
serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
);
END tech_eth_10g_arria10_e1sg;
ARCHITECTURE str OF tech_eth_10g_arria10_e1sg IS
-- Enable or disable the conditions that must be ok to release tx_snk_out_arr xon
CONSTANT c_check_link_status : BOOLEAN := g_direction/="TX_ONLY";
CONSTANT c_check_xgmii_tx_ready : BOOLEAN := g_direction/="RX_ONLY";
SIGNAL i_tx_snk_out_arr : t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
-- MAG_10G control status registers
SIGNAL mac_mosi_arr : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
SIGNAL mac_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0);
-- XON control
SIGNAL mac_snk_out_arr : t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
-- XGMII
SIGNAL xgmii_link_status_arr : t_tech_mac_10g_xgmii_status_arr(g_nof_channels-1 DOWNTO 0); -- 2 bit, from MAC_10g
SIGNAL xgmii_tx_ready_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- 1 bit, from PHY 10gbase_r
SIGNAL xgmii_tx_dc_arr : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
SIGNAL xgmii_rx_dc_arr : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
SIGNAL xgmii_internal_dc_arr : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
-- Link status monitor
CONSTANT c_mem_reg_eth10g_adr_w : NATURAL := 1;
CONSTANT c_mem_reg_eth10g_dat_w : NATURAL := 32;
CONSTANT c_mem_reg_eth10g_nof_data : NATURAL := 1;
CONSTANT c_mem_reg_eth10g : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_eth10g_adr_w , c_mem_reg_eth10g_dat_w , c_mem_reg_eth10g_nof_data, 'X');
SIGNAL reg_eth10g_mosi_arr : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
SIGNAL reg_eth10g_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0);
SIGNAL mm_reg_eth10g_arr : t_slv_32_arr(g_nof_channels-1 DOWNTO 0);
BEGIN
tx_snk_out_arr <= i_tx_snk_out_arr;
gen_mac : FOR I IN 0 TO g_nof_channels-1 GENERATE
i_tx_snk_out_arr(I).ready <= mac_snk_out_arr(I).ready; -- pass on MAC cycle accurate backpressure
p_xon_flow_control : PROCESS(clk_156)
VARIABLE v_xgmii_link_status : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0) := "00";
VARIABLE v_xgmii_tx_ready : STD_LOGIC := '1';
BEGIN
IF rising_edge(clk_156) THEN
i_tx_snk_out_arr(I).xon <= '0';
-- First gather all conditions that are enabled to affect xon. The default value is such that it enables xon when the condition is not checked.
IF c_check_link_status =TRUE THEN v_xgmii_link_status := xgmii_link_status_arr(I); END IF; -- check both remote fault [1] and local fault [0]
IF c_check_xgmii_tx_ready=TRUE THEN v_xgmii_tx_ready := xgmii_tx_ready_arr(I); END IF;
-- Now apply the conditions to xon
IF v_xgmii_tx_ready='1' AND v_xgmii_link_status="00" THEN
i_tx_snk_out_arr(I).xon <= '1'; -- XON when Tx PHY is ready and XGMII is ok
END IF;
END IF;
END PROCESS;
u_tech_mac_10g : ENTITY tech_mac_10g_lib.tech_mac_10g
GENERIC MAP (
g_technology => c_tech_arria10_e1sg,
g_pre_header_padding => g_pre_header_padding
)
PORT MAP (
-- MM
mm_clk => mm_clk,
mm_rst => mm_rst,
csr_mosi => mac_mosi_arr(I),
csr_miso => mac_miso_arr(I),
-- ST
tx_clk_312 => clk_312,
tx_clk_156 => clk_156,
tx_rst => rst_156,
tx_snk_in => tx_snk_in_arr(I), -- 64 bit data
tx_snk_out => mac_snk_out_arr(I),
rx_clk_312 => clk_312,
rx_clk_156 => clk_156,
rx_rst => rst_156,
rx_src_out => rx_src_out_arr(I), -- 64 bit data
rx_src_in => rx_src_in_arr(I),
-- XGMII
xgmii_link_status => xgmii_link_status_arr(I),
xgmii_tx_data => xgmii_tx_dc_arr(I),
xgmii_rx_data => xgmii_internal_dc_arr(I)
);
END GENERATE;
xgmii_internal_dc_arr <= xgmii_tx_dc_arr WHEN g_direction="TX_ONLY" ELSE xgmii_rx_dc_arr;
u_tech_10gbase_r: ENTITY tech_10gbase_r_lib.tech_10gbase_r
GENERIC MAP (
g_technology => c_tech_arria10_e1sg,
g_sim => g_sim,
g_sim_level => g_sim_level,
g_nof_channels => g_nof_channels
)
PORT MAP (
-- Transceiver PLL reference clock
tr_ref_clk_644 => tr_ref_clk_644,
-- XGMII clocks
clk_156 => clk_156,
rst_156 => rst_156,
-- XGMII interface
xgmii_tx_ready_arr => xgmii_tx_ready_arr,
xgmii_rx_ready_arr => OPEN,
xgmii_tx_dc_arr => xgmii_tx_dc_arr,
xgmii_rx_dc_arr => xgmii_rx_dc_arr,
-- PHY serial IO
tx_serial_arr => serial_tx_arr,
rx_serial_arr => serial_rx_arr
);
gen_reg_eth10g : FOR I IN 0 TO g_nof_channels-1 GENERATE
mm_reg_eth10g_arr(I) <= RESIZE_UVEC(xgmii_link_status_arr(I) & xgmii_tx_ready_arr(I) & i_tx_snk_out_arr(I).xon, c_mem_reg_eth10g_dat_w);
u_reg_map : ENTITY common_lib.common_reg_r_w_dc
GENERIC MAP (
g_cross_clock_domain => TRUE,
g_in_new_latency => 0,
g_readback => FALSE,
g_reg => c_mem_reg_eth10g,
g_init_reg => (OTHERS => '0')
)
PORT MAP (
-- Clocks and reset
mm_rst => mm_rst,
mm_clk => mm_clk,
st_rst => rst_156,
st_clk => clk_156,
-- Memory Mapped Slave in mm_clk domain
sla_in => reg_eth10g_mosi_arr(I),
sla_out => reg_eth10g_miso_arr(I),
-- MM registers in st_clk domain
reg_wr_arr => OPEN,
reg_rd_arr => OPEN,
in_new => '1',
in_reg => mm_reg_eth10g_arr(I),
out_reg => OPEN
);
END GENERATE;
-----------------------------------------------------------------------------
-- MM bus mux
-----------------------------------------------------------------------------
u_common_mem_mux_mac : ENTITY common_lib.common_mem_mux
GENERIC MAP (
g_nof_mosi => g_nof_channels,
g_mult_addr_w => func_tech_mac_10g_csr_addr_w(c_tech_arria10)
)
PORT MAP (
mosi => mac_mosi,
miso => mac_miso,
mosi_arr => mac_mosi_arr,
miso_arr => mac_miso_arr
);
u_common_mem_mux_eth10g : ENTITY common_lib.common_mem_mux
GENERIC MAP (
g_nof_mosi => g_nof_channels,
g_mult_addr_w => c_mem_reg_eth10g_adr_w
)
PORT MAP (
mosi => reg_eth10g_mosi,
miso => reg_eth10g_miso,
mosi_arr => reg_eth10g_mosi_arr,
miso_arr => reg_eth10g_miso_arr
);
END str;
libraries/technology/eth_10g/tech_eth_10g_clocks.vhd
+ 1
− 1
View file @ e50aab24
...@@ -85,7 +85,7 @@ BEGIN ...@@ -85,7 +85,7 @@ BEGIN
eth_rx_rst_arr <= rx_rst_arr; eth_rx_rst_arr <= rx_rst_arr;
END GENERATE; END GENERATE;
gen_clocks_10gbase_r : IF g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 GENERATE gen_clocks_10gbase_r : IF g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg GENERATE
eth_tx_clk_arr <= (OTHERS=>tr_ref_clk_156); eth_tx_clk_arr <= (OTHERS=>tr_ref_clk_156);
eth_tx_rst_arr <= (OTHERS=>tr_ref_rst_156); eth_tx_rst_arr <= (OTHERS=>tr_ref_rst_156);
......
libraries/technology/fifo/hdllib.cfg
+ 2
− 1
View file @ e50aab24
hdl_lib_name = tech_fifo hdl_lib_name = tech_fifo
hdl_library_clause_name = tech_fifo_lib hdl_library_clause_name = tech_fifo_lib
hdl_lib_uses_synth = technology ip_stratixiv_fifo ip_arria10_fifo ip_arria10_e3sge3_fifo hdl_lib_uses_synth = technology ip_stratixiv_fifo ip_arria10_fifo ip_arria10_e3sge3_fifo ip_arria10_e1sg_fifo
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = hdl_lib_technology =
hdl_lib_disclose_library_clause_names = hdl_lib_disclose_library_clause_names =
ip_stratixiv_fifo ip_stratixiv_fifo_lib ip_stratixiv_fifo ip_stratixiv_fifo_lib
ip_arria10_fifo ip_arria10_fifo_lib ip_arria10_fifo ip_arria10_fifo_lib
ip_arria10_e3sge3_fifo ip_arria10_e3sge3_fifo_lib ip_arria10_e3sge3_fifo ip_arria10_e3sge3_fifo_lib
ip_arria10_e1sg_fifo ip_arria10_e1sg_fifo_lib
synth_files = synth_files =
tech_fifo_component_pkg.vhd tech_fifo_component_pkg.vhd
......
libraries/technology/fifo/tech_fifo_component_pkg.vhd
+ 65
− 0
View file @ e50aab24
...@@ -222,5 +222,70 @@ PACKAGE tech_fifo_component_pkg IS ...@@ -222,5 +222,70 @@ PACKAGE tech_fifo_component_pkg IS
); );
END COMPONENT; END COMPONENT;
-----------------------------------------------------------------------------
-- ip_arria10_e1sg
-----------------------------------------------------------------------------
COMPONENT ip_arria10_e1sg_fifo_sc IS
GENERIC (
g_use_eab : STRING := "ON";
g_dat_w : NATURAL := 20;
g_nof_words : NATURAL := 1024
);
PORT (
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT ip_arria10_e1sg_fifo_dc IS
GENERIC (
g_use_eab : STRING := "ON";
g_dat_w : NATURAL := 20;
g_nof_words : NATURAL := 1024
);
PORT (
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
wrfull : OUT STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT ip_arria10_e1sg_fifo_dc_mixed_widths IS
GENERIC (
g_nof_words : NATURAL := 1024; -- FIFO size in nof wr_dat words
g_wrdat_w : NATURAL := 20;
g_rddat_w : NATURAL := 10
);
PORT (
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
wrfull : OUT STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
);
END COMPONENT;
END tech_fifo_component_pkg; END tech_fifo_component_pkg;
libraries/technology/fifo/tech_fifo_dc.vhd
+ 7
− 0
View file @ e50aab24
...@@ -29,6 +29,7 @@ USE technology_lib.technology_select_pkg.ALL; ...@@ -29,6 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_fifo_lib; LIBRARY ip_stratixiv_fifo_lib;
LIBRARY ip_arria10_fifo_lib; LIBRARY ip_arria10_fifo_lib;
LIBRARY ip_arria10_e3sge3_fifo_lib; LIBRARY ip_arria10_e3sge3_fifo_lib;
LIBRARY ip_arria10_e1sg_fifo_lib;
ENTITY tech_fifo_dc IS ENTITY tech_fifo_dc IS
GENERIC ( GENERIC (
...@@ -75,4 +76,10 @@ BEGIN ...@@ -75,4 +76,10 @@ BEGIN
PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw); PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
END GENERATE; END GENERATE;
gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
u0 : ip_arria10_e1sg_fifo_dc
GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
END GENERATE;
END ARCHITECTURE; END ARCHITECTURE;
libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
+ 7
− 0
View file @ e50aab24
...@@ -29,6 +29,7 @@ USE technology_lib.technology_select_pkg.ALL; ...@@ -29,6 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_fifo_lib; LIBRARY ip_stratixiv_fifo_lib;
LIBRARY ip_arria10_fifo_lib; LIBRARY ip_arria10_fifo_lib;
LIBRARY ip_arria10_e3sge3_fifo_lib; LIBRARY ip_arria10_e3sge3_fifo_lib;
LIBRARY ip_arria10_e1sg_fifo_lib;
ENTITY tech_fifo_dc_mixed_widths IS ENTITY tech_fifo_dc_mixed_widths IS
GENERIC ( GENERIC (
...@@ -75,4 +76,10 @@ BEGIN ...@@ -75,4 +76,10 @@ BEGIN
PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw); PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
END GENERATE; END GENERATE;
gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
u0 : ip_arria10_e1sg_fifo_dc_mixed_widths
GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
END GENERATE;
END ARCHITECTURE; END ARCHITECTURE;
libraries/technology/fifo/tech_fifo_sc.vhd
+ 7
− 0
View file @ e50aab24
...@@ -29,6 +29,7 @@ USE technology_lib.technology_select_pkg.ALL; ...@@ -29,6 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_fifo_lib; LIBRARY ip_stratixiv_fifo_lib;
LIBRARY ip_arria10_fifo_lib; LIBRARY ip_arria10_fifo_lib;
LIBRARY ip_arria10_e3sge3_fifo_lib; LIBRARY ip_arria10_e3sge3_fifo_lib;
LIBRARY ip_arria10_e1sg_fifo_lib;
ENTITY tech_fifo_sc IS ENTITY tech_fifo_sc IS
GENERIC ( GENERIC (
...@@ -73,4 +74,10 @@ BEGIN ...@@ -73,4 +74,10 @@ BEGIN
PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw); PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
END GENERATE; END GENERATE;
gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
u0 : ip_arria10_e1sg_fifo_sc
GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
END GENERATE;
END ARCHITECTURE; END ARCHITECTURE;
libraries/technology/flash/hdllib.cfg
+ 4
− 0
View file @ e50aab24
...@@ -6,6 +6,8 @@ hdl_lib_uses_synth = technology ...@@ -6,6 +6,8 @@ hdl_lib_uses_synth = technology
ip_arria10_remote_update ip_arria10_remote_update
ip_arria10_e3sge3_asmi_parallel ip_arria10_e3sge3_asmi_parallel
ip_arria10_e3sge3_remote_update ip_arria10_e3sge3_remote_update
ip_arria10_e1sg_asmi_parallel
ip_arria10_e1sg_remote_update
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = hdl_lib_technology =
hdl_lib_disclose_library_clause_names = hdl_lib_disclose_library_clause_names =
...@@ -14,6 +16,8 @@ hdl_lib_disclose_library_clause_names = ...@@ -14,6 +16,8 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_remote_update ip_arria10_remote_update_altera_remote_update_150 ip_arria10_remote_update ip_arria10_remote_update_altera_remote_update_150
ip_arria10_e3sge3_asmi_parallel ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151 ip_arria10_e3sge3_asmi_parallel ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151
ip_arria10_e3sge3_remote_update ip_arria10_e3sge3_remote_update_altera_remote_update_151 ip_arria10_e3sge3_remote_update ip_arria10_e3sge3_remote_update_altera_remote_update_151
ip_arria10_e1sg_asmi_parallel ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_151
ip_arria10_e1sg_remote_update ip_arria10_e1sg_remote_update_altera_remote_update_151
synth_files = synth_files =
tech_flash_component_pkg.vhd tech_flash_component_pkg.vhd
......
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