From e50aab24a6fbb597291ce8b332bdb587faab8487 Mon Sep 17 00:00:00 2001
From: Jonathan Hargreaves <hargreaves@astron.nl>
Date: Wed, 15 Feb 2017 15:10:25 +0000
Subject: [PATCH] Modify technology wrappers to include unb2b FPGA Arria 10
version e1sg
---
libraries/technology/10gbase_r/hdllib.cfg | 33 +-
.../technology/10gbase_r/tech_10gbase_r.vhd | 9 +
.../10gbase_r/tech_10gbase_r_arria10_e1sg.vhd | 556 ++++++++++++++++++
.../tech_10gbase_r_component_pkg.vhd | 384 ++++++++++++
libraries/technology/clkbuf/hdllib.cfg | 3 +-
libraries/technology/clkbuf/tech_clkbuf.vhd | 14 +
.../clkbuf/tech_clkbuf_component_pkg.vhd | 11 +
libraries/technology/ddr/hdllib.cfg | 9 +
.../technology/ddr/tech_ddr_arria10_e1sg.vhd | 262 +++++++++
.../technology/ddr/tech_ddr_component_pkg.vhd | 118 ++++
libraries/technology/eth_10g/hdllib.cfg | 1 +
libraries/technology/eth_10g/tech_eth_10g.vhd | 42 ++
.../eth_10g/tech_eth_10g_arria10_e1sg.vhd | 314 ++++++++++
.../eth_10g/tech_eth_10g_clocks.vhd | 2 +-
libraries/technology/fifo/hdllib.cfg | 3 +-
.../fifo/tech_fifo_component_pkg.vhd | 65 ++
libraries/technology/fifo/tech_fifo_dc.vhd | 7 +
.../fifo/tech_fifo_dc_mixed_widths.vhd | 7 +
libraries/technology/fifo/tech_fifo_sc.vhd | 7 +
libraries/technology/flash/hdllib.cfg | 4 +
.../flash/tech_flash_asmi_parallel.vhd | 6 +
.../flash/tech_flash_component_pkg.vhd | 45 +-
.../flash/tech_flash_remote_update.vhd | 7 +
.../technology/fpga_temp_sens/hdllib.cfg | 3 +-
.../fpga_temp_sens/tech_fpga_temp_sens.vhd | 11 +
.../tech_fpga_temp_sens_component_pkg.vhd | 9 +
.../technology/fpga_voltage_sens/hdllib.cfg | 3 +-
.../tech_fpga_voltage_sens.vhd | 20 +
.../tech_fpga_voltage_sens_component_pkg.vhd | 18 +
.../technology/fractional_pll/hdllib.cfg | 6 +-
.../tech_fractional_pll_clk125.vhd | 15 +
.../tech_fractional_pll_clk200.vhd | 14 +
.../tech_fractional_pll_component_pkg.vhd | 31 +
libraries/technology/iobuf/hdllib.cfg | 3 +-
.../iobuf/tech_iobuf_component_pkg.vhd | 32 +
.../technology/iobuf/tech_iobuf_ddio_in.vhd | 9 +-
.../technology/iobuf/tech_iobuf_ddio_out.vhd | 7 +
libraries/technology/mac_10g/hdllib.cfg | 4 +-
libraries/technology/mac_10g/tech_mac_10g.vhd | 12 +-
.../mac_10g/tech_mac_10g_arria10_e1sg.vhd | 145 +++++
.../mac_10g/tech_mac_10g_component_pkg.vhd | 50 ++
libraries/technology/memory/hdllib.cfg | 3 +-
.../memory/tech_memory_component_pkg.vhd | 94 +++
.../memory/tech_memory_ram_cr_cw.vhd | 7 +
.../memory/tech_memory_ram_crw_crw.vhd | 7 +
.../memory/tech_memory_ram_crwk_crw.vhd | 7 +
.../technology/memory/tech_memory_ram_r_w.vhd | 7 +
.../technology/memory/tech_memory_rom_r.vhd | 15 +
libraries/technology/mult/hdllib.cfg | 2 +
libraries/technology/mult/tech_mult_add4.vhd | 27 +
.../mult/tech_mult_component_pkg.vhd | 29 +
libraries/technology/pll/hdllib.cfg | 12 +-
libraries/technology/pll/tech_pll_clk125.vhd | 15 +
libraries/technology/pll/tech_pll_clk200.vhd | 13 +
libraries/technology/pll/tech_pll_clk25.vhd | 14 +
.../technology/pll/tech_pll_component_pkg.vhd | 53 ++
.../pll/tech_pll_xgmii_mac_clocks.vhd | 13 +
libraries/technology/technology_pkg.vhd | 5 +-
libraries/technology/tse/hdllib.cfg | 4 +
libraries/technology/tse/tech_tse.vhd | 13 +
.../technology/tse/tech_tse_arria10_e1sg.vhd | 256 ++++++++
.../technology/tse/tech_tse_component_pkg.vhd | 119 +++-
62 files changed, 2983 insertions(+), 33 deletions(-)
create mode 100644 libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
create mode 100644 libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd
create mode 100644 libraries/technology/eth_10g/tech_eth_10g_arria10_e1sg.vhd
create mode 100644 libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd
create mode 100644 libraries/technology/tse/tech_tse_arria10_e1sg.vhd
diff --git a/libraries/technology/10gbase_r/hdllib.cfg b/libraries/technology/10gbase_r/hdllib.cfg
index 1b351c5222..df262a14c6 100644
--- a/libraries/technology/10gbase_r/hdllib.cfg
+++ b/libraries/technology/10gbase_r/hdllib.cfg
@@ -1,17 +1,17 @@
hdl_lib_name = tech_10gbase_r
hdl_library_clause_name = tech_10gbase_r_lib
hdl_lib_uses_synth = technology common tech_pll tech_transceiver
-hdl_lib_uses_ip = ip_arria10_phy_10gbase_r ip_arria10_e3sge3_phy_10gbase_r
- ip_arria10_phy_10gbase_r_4 ip_arria10_e3sge3_phy_10gbase_r_4
- ip_arria10_phy_10gbase_r_12 ip_arria10_e3sge3_phy_10gbase_r_12
- ip_arria10_phy_10gbase_r_24 ip_arria10_e3sge3_phy_10gbase_r_24
- ip_arria10_phy_10gbase_r_48 ip_arria10_e3sge3_phy_10gbase_r_48
- ip_arria10_transceiver_pll_10g ip_arria10_e3sge3_transceiver_pll_10g
- ip_arria10_transceiver_reset_controller_1 ip_arria10_e3sge3_transceiver_reset_controller_1
- ip_arria10_transceiver_reset_controller_4 ip_arria10_e3sge3_transceiver_reset_controller_4
- ip_arria10_transceiver_reset_controller_12 ip_arria10_e3sge3_transceiver_reset_controller_12
- ip_arria10_transceiver_reset_controller_24 ip_arria10_e3sge3_transceiver_reset_controller_24
- ip_arria10_transceiver_reset_controller_48 ip_arria10_e3sge3_transceiver_reset_controller_48
+hdl_lib_uses_ip = ip_arria10_phy_10gbase_r ip_arria10_e3sge3_phy_10gbase_r ip_arria10_e1sg_phy_10gbase_r
+ ip_arria10_phy_10gbase_r_4 ip_arria10_e3sge3_phy_10gbase_r_4 ip_arria10_e1sg_phy_10gbase_r_4
+ ip_arria10_phy_10gbase_r_12 ip_arria10_e3sge3_phy_10gbase_r_12 ip_arria10_e1sg_phy_10gbase_r_12
+ ip_arria10_phy_10gbase_r_24 ip_arria10_e3sge3_phy_10gbase_r_24 ip_arria10_e1sg_phy_10gbase_r_24
+ ip_arria10_phy_10gbase_r_48 ip_arria10_e3sge3_phy_10gbase_r_48 ip_arria10_e1sg_phy_10gbase_r_48
+ ip_arria10_transceiver_pll_10g ip_arria10_e3sge3_transceiver_pll_10g ip_arria10_e1sg_transceiver_pll_10g
+ ip_arria10_transceiver_reset_controller_1 ip_arria10_e3sge3_transceiver_reset_controller_1 ip_arria10_e1sg_transceiver_reset_controller_1
+ ip_arria10_transceiver_reset_controller_4 ip_arria10_e3sge3_transceiver_reset_controller_4 ip_arria10_e1sg_transceiver_reset_controller_4
+ ip_arria10_transceiver_reset_controller_12 ip_arria10_e3sge3_transceiver_reset_controller_12 ip_arria10_e1sg_transceiver_reset_controller_12
+ ip_arria10_transceiver_reset_controller_24 ip_arria10_e3sge3_transceiver_reset_controller_24 ip_arria10_e1sg_transceiver_reset_controller_24
+ ip_arria10_transceiver_reset_controller_48 ip_arria10_e3sge3_transceiver_reset_controller_48 ip_arria10_e1sg_transceiver_reset_controller_48
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
@@ -37,12 +37,23 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e3sge3_transceiver_reset_controller_12 ip_arria10_e3sge3_transceiver_reset_controller_12_altera_xcvr_reset_control_151
ip_arria10_e3sge3_transceiver_reset_controller_24 ip_arria10_e3sge3_transceiver_reset_controller_24_altera_xcvr_reset_control_151
ip_arria10_e3sge3_transceiver_reset_controller_48 ip_arria10_e3sge3_transceiver_reset_controller_48_altera_xcvr_reset_control_151
+ ip_arria10_e1sg_phy_10gbase_r ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_151
+ ip_arria10_e1sg_phy_10gbase_r_4 ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_151
+ ip_arria10_e1sg_phy_10gbase_r_12 ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_151
+ ip_arria10_e1sg_phy_10gbase_r_24 ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_151
+ ip_arria10_e1sg_phy_10gbase_r_48 ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_151
+ ip_arria10_e1sg_transceiver_pll_10g ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151
+ ip_arria10_e1sg_transceiver_reset_controller_1 ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_151
+ ip_arria10_e1sg_transceiver_reset_controller_4 ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_151
+ ip_arria10_e1sg_transceiver_reset_controller_12 ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_151
+ ip_arria10_e1sg_transceiver_reset_controller_24 ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_151
synth_files =
sim_10gbase_r.vhd
tech_10gbase_r_component_pkg.vhd
tech_10gbase_r_arria10.vhd
tech_10gbase_r_arria10_e3sge3.vhd
+ tech_10gbase_r_arria10_e1sg.vhd
tech_10gbase_r.vhd
test_bench_files =
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r.vhd b/libraries/technology/10gbase_r/tech_10gbase_r.vhd
index aa0600af4a..f1ea244a9f 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r.vhd
@@ -80,6 +80,15 @@ BEGIN
tx_serial_arr, rx_serial_arr);
END GENERATE;
+ gen_ip_arria10_e1sg : IF c_use_technology=TRUE AND g_technology=c_tech_arria10_e1sg GENERATE
+ u0 : ENTITY work.tech_10gbase_r_arria10_e1sg
+ GENERIC MAP (g_sim, g_nof_channels)
+ PORT MAP (tr_ref_clk_644,
+ clk_156, rst_156,
+ xgmii_tx_ready_arr, xgmii_rx_ready_arr, xgmii_tx_dc_arr, xgmii_rx_dc_arr,
+ tx_serial_arr, rx_serial_arr);
+ END GENERATE;
+
gem_sim_10gbase_r : IF c_use_sim_model=TRUE GENERATE
u0 : ENTITY work.sim_10gbase_r
GENERIC MAP (g_sim, g_nof_channels)
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
new file mode 100644
index 0000000000..32171c4708
--- /dev/null
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
@@ -0,0 +1,556 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_151;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_151;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_151;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_151;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_151;
+LIBRARY ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_151;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_151;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_151;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_151;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_48_altera_xcvr_reset_control_151;
+
+LIBRARY IEEE, tech_pll_lib, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_interface_layers_pkg.ALL;
+USE tech_pll_lib.tech_pll_component_pkg.ALL;
+USE work.tech_10gbase_r_component_pkg.ALL;
+
+ENTITY tech_10gbase_r_arria10_e1sg IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_nof_channels : NATURAL := 1
+ );
+ PORT (
+ -- Transceiver ATX PLL reference clock
+ tr_ref_clk_644 : IN STD_LOGIC; -- 644.531250 MHz
+
+ -- XGMII clocks
+ clk_156 : IN STD_LOGIC; -- 156.25 MHz
+ rst_156 : IN STD_LOGIC;
+
+ -- XGMII interface
+ xgmii_tx_ready_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- can be used for xon flow control
+ xgmii_rx_ready_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- typically leave not connected
+ xgmii_tx_dc_arr : IN t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
+ xgmii_rx_dc_arr : OUT t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
+
+ -- PHY serial IO
+ tx_serial_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ rx_serial_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
+ );
+END tech_10gbase_r_arria10_e1sg;
+
+
+ARCHITECTURE str OF tech_10gbase_r_arria10_e1sg IS
+
+ -- FIXME check selection of g_nof_channels to be 1,4,12 or 24
+
+ --CONSTANT c_nof_channels_per_ip : NATURAL := sel_a_b(g_nof_channels=24, 24, 1); -- only support single 1 or block of 12
+ --CONSTANT c_nof_channels_per_ip : NATURAL := 24 WHEN g_nof_channels=24 ELSE 12 WHEN g_nof_channels=12 ELSE 1;
+ CONSTANT c_nof_channels_per_ip : NATURAL := g_nof_channels;
+
+
+ CONSTANT IP_SIZE : NATURAL := c_nof_channels_per_ip; -- short constant name alias to improve index readability
+ CONSTANT IP_SIZE_DATA : NATURAL := IP_SIZE * c_xgmii_data_w;
+ CONSTANT IP_SIZE_CONTROL : NATURAL := IP_SIZE * c_xgmii_nof_lanes;
+
+ SIGNAL tx_serial_clk : STD_LOGIC_VECTOR(0 DOWNTO 0);
+
+ SIGNAL tr_coreclkin : STD_LOGIC_VECTOR(0 DOWNTO 0);
+
+ SIGNAL tx_parallel_data_arr : t_xgmii_d_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit
+ SIGNAL rx_parallel_data_arr : t_xgmii_d_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit
+ SIGNAL tx_control_arr : t_xgmii_c_arr(g_nof_channels-1 DOWNTO 0); -- 8 bit
+ SIGNAL rx_control_arr : t_xgmii_c_arr(g_nof_channels-1 DOWNTO 0); -- 8 bit
+
+ -- IP block SLV signals
+ SIGNAL tx_serial_clk_slv : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ SIGNAL tr_coreclkin_slv : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ SIGNAL tx_parallel_data_arr_slv : STD_LOGIC_VECTOR(g_nof_channels*c_xgmii_data_w-1 DOWNTO 0); -- 64 bit
+ SIGNAL rx_parallel_data_arr_slv : STD_LOGIC_VECTOR(g_nof_channels*c_xgmii_data_w-1 DOWNTO 0); -- 64 bit
+ SIGNAL tx_control_arr_slv : STD_LOGIC_VECTOR(g_nof_channels*c_xgmii_nof_lanes-1 DOWNTO 0); -- 8 bit
+ SIGNAL rx_control_arr_slv : STD_LOGIC_VECTOR(g_nof_channels*c_xgmii_nof_lanes-1 DOWNTO 0); -- 8 bit
+
+ -- transceiver reset controller
+ SIGNAL tx_analogreset_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'1');
+ SIGNAL tx_digitalreset_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'1');
+ SIGNAL rx_analogreset_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'1');
+ SIGNAL rx_digitalreset_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'1');
+ SIGNAL tx_cal_busy_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL rx_cal_busy_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL rx_is_lockedtodata_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'0');
+
+ SIGNAL cal_busy_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'0');
+
+ -- transceiver ATX PLL for 10G
+ SIGNAL atx_pll_powerdown_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL atx_pll_locked_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL atx_pll_locked : STD_LOGIC;
+ SIGNAL atx_pll_cal_busy : STD_LOGIC;
+
+BEGIN
+
+ -- Clocks
+ tr_coreclkin(0) <= clk_156;
+
+ gen_glue_logic : FOR I IN 0 TO g_nof_channels-1 GENERATE
+ -- Reset controller
+ cal_busy_arr(I) <= tx_cal_busy_arr(I) OR atx_pll_cal_busy;
+
+ -- On hardware use atx_pll_locked for all channels, in simulation model some timing difference between the channels
+ gen_hw : IF g_sim=FALSE GENERATE
+ atx_pll_locked_arr(I) <= atx_pll_locked;
+ END GENERATE;
+ gen_sim : IF g_sim=TRUE GENERATE
+ atx_pll_locked_arr(I) <= TRANSPORT atx_pll_locked AFTER tech_pll_clk_156_period*I;
+ END GENERATE;
+
+ -- XGMII
+ tx_parallel_data_arr(I) <= func_xgmii_d(xgmii_tx_dc_arr(I));
+ tx_control_arr(I) <= func_xgmii_c(xgmii_tx_dc_arr(I));
+
+ xgmii_rx_dc_arr(I) <= func_xgmii_dc(rx_parallel_data_arr(I), rx_control_arr(I));
+ END GENERATE;
+
+
+ gen_phy_1 : IF c_nof_channels_per_ip=1 GENERATE
+ gen_channels : FOR I IN 0 TO g_nof_channels-1 GENERATE
+ u_ip_arria10_e1sg_phy_10gbase_r : ip_arria10_e1sg_phy_10gbase_r
+ PORT MAP (
+ tx_analogreset => tx_analogreset_arr(I DOWNTO I),
+ tx_digitalreset => tx_digitalreset_arr(I DOWNTO I),
+ rx_analogreset => rx_analogreset_arr(I DOWNTO I),
+ rx_digitalreset => rx_digitalreset_arr(I DOWNTO I),
+ tx_cal_busy => tx_cal_busy_arr(I DOWNTO I),
+ rx_cal_busy => rx_cal_busy_arr(I DOWNTO I),
+
+ tx_serial_clk0 => tx_serial_clk,
+ rx_cdr_refclk0 => tr_ref_clk_644,
+ tx_serial_data => tx_serial_arr(I DOWNTO I),
+ rx_serial_data => rx_serial_arr(I DOWNTO I),
+
+ rx_is_lockedtoref => OPEN,
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(I DOWNTO I),
+
+ tx_coreclkin => tr_coreclkin, -- 156.25 MHz
+ rx_coreclkin => tr_coreclkin, -- 156.25 MHz
+
+ tx_parallel_data => tx_parallel_data_arr(I),
+ rx_parallel_data => rx_parallel_data_arr(I),
+ tx_control => tx_control_arr(I),
+ rx_control => rx_control_arr(I)
+
+ --tx_err_ins : in std_logic := '0'; -- tx_err_ins.tx_err_ins
+ --tx_enh_data_valid : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
+ --tx_enh_fifo_full : out std_logic_vector(0 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
+ --tx_enh_fifo_pfull : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ --tx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ --tx_enh_fifo_pempty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+
+ --rx_enh_data_valid : out std_logic_vector(0 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
+ --rx_enh_fifo_full : out std_logic_vector(0 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
+ --rx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ --rx_enh_fifo_del : out std_logic_vector(0 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
+ --rx_enh_fifo_insert : out std_logic_vector(0 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ --rx_enh_highber : out std_logic_vector(0 downto 0); -- rx_enh_highber.rx_enh_highber
+ --rx_enh_blk_lock : out std_logic_vector(0 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
+
+ --unused_tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0'); -- unused_tx_parallel_data.unused_tx_parallel_data
+ --unused_tx_control : in std_logic_vector(8 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
+ --unused_rx_parallel_data : out std_logic_vector(63 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
+ --unused_rx_control : out std_logic_vector(11 downto 0); -- unused_rx_control.unused_rx_control
+ );
+
+ u_ip_arria10_e1sg_transceiver_reset_controller_1 : ip_arria10_e1sg_transceiver_reset_controller_1
+ PORT MAP (
+ clock => clk_156,
+ reset => rst_156,
+ pll_powerdown => atx_pll_powerdown_arr(I DOWNTO I),
+ tx_analogreset => tx_analogreset_arr(I DOWNTO I),
+ tx_digitalreset => tx_digitalreset_arr(I DOWNTO I),
+ tx_ready => xgmii_tx_ready_arr(I DOWNTO I),
+ pll_locked => atx_pll_locked_arr(I DOWNTO I),
+ pll_select => "0", -- set to zero when using one PLL
+ tx_cal_busy => cal_busy_arr(I DOWNTO I),
+ rx_analogreset => rx_analogreset_arr(I DOWNTO I),
+ rx_digitalreset => rx_digitalreset_arr(I DOWNTO I),
+ rx_ready => xgmii_rx_ready_arr(I DOWNTO I),
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(I DOWNTO I),
+ rx_cal_busy => rx_cal_busy_arr(I DOWNTO I)
+ );
+ END GENERATE;
+ END GENERATE;
+
+
+
+ gen_phy_4 : IF c_nof_channels_per_ip=4 GENERATE
+ tx_serial_clk_slv <= (OTHERS=>tx_serial_clk(0));
+ tr_coreclkin_slv <= (OTHERS=>tr_coreclkin(0));
+
+ gen_channels : FOR I IN 0 TO g_nof_channels-1 GENERATE
+ tx_parallel_data_arr_slv((I+1)*c_xgmii_data_w-1 DOWNTO I*c_xgmii_data_w) <= tx_parallel_data_arr(I);
+ tx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes) <= tx_control_arr(I);
+
+ rx_parallel_data_arr(I) <= rx_parallel_data_arr_slv((I+1)*c_xgmii_data_w-1 DOWNTO I*c_xgmii_data_w);
+ rx_control_arr(I) <= rx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes);
+ END GENERATE;
+
+ u_ip_arria10_e1sg_phy_10gbase_r_4 : ip_arria10_e1sg_phy_10gbase_r_4
+ PORT MAP (
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+
+ --rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+
+ --tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
+ --rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
+
+ --tx_err_ins : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
+ --tx_enh_data_valid : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
+ --tx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ --tx_enh_fifo_full : out std_logic_vector(11 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
+ --tx_enh_fifo_pempty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ --tx_enh_fifo_pfull : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ --tx_pma_div_clkout : out std_logic_vector(11 downto 0); -- tx_pma_div_clkout.clk
+
+ --rx_enh_blk_lock : out std_logic_vector(11 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
+ --rx_enh_data_valid : out std_logic_vector(11 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
+ --rx_enh_fifo_del : out std_logic_vector(11 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
+ --rx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ --rx_enh_fifo_full : out std_logic_vector(11 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
+ --rx_enh_fifo_insert : out std_logic_vector(11 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ --rx_enh_highber : out std_logic_vector(11 downto 0); -- rx_enh_highber.rx_enh_highber
+
+ --unused_rx_control : out std_logic_vector(287 downto 0); -- unused_rx_control.unused_rx_control
+ --unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
+ --unused_tx_control : in std_logic_vector(215 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
+ --unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ );
+
+ u_ip_arria10_e1sg_transceiver_reset_controller_4 : ip_arria10_e1sg_transceiver_reset_controller_4
+ PORT MAP (
+ clock => clk_156, -- : in std_logic := '0'; -- clock.clk
+ pll_locked => atx_pll_locked_arr(0 DOWNTO 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_powerdown => atx_pll_powerdown_arr(0 DOWNTO 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ reset => rst_156, -- : in std_logic := '0'; -- reset.reset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 DOWNTO 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ );
+ END GENERATE;
+
+
+
+
+ gen_phy_12 : IF c_nof_channels_per_ip=12 GENERATE
+ tx_serial_clk_slv <= (OTHERS=>tx_serial_clk(0));
+ tr_coreclkin_slv <= (OTHERS=>tr_coreclkin(0));
+
+ gen_channels : FOR I IN 0 TO g_nof_channels-1 GENERATE
+ tx_parallel_data_arr_slv((I+1)*c_xgmii_data_w-1 DOWNTO I*c_xgmii_data_w) <= tx_parallel_data_arr(I);
+ tx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes) <= tx_control_arr(I);
+
+ rx_parallel_data_arr(I) <= rx_parallel_data_arr_slv((I+1)*c_xgmii_data_w-1 DOWNTO I*c_xgmii_data_w);
+ rx_control_arr(I) <= rx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes);
+ END GENERATE;
+
+ u_ip_arria10_e1sg_phy_10gbase_r_12 : ip_arria10_e1sg_phy_10gbase_r_12
+ PORT MAP (
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+
+ --rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+
+ --tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
+ --rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
+
+ --tx_err_ins : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
+ --tx_enh_data_valid : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
+ --tx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ --tx_enh_fifo_full : out std_logic_vector(11 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
+ --tx_enh_fifo_pempty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ --tx_enh_fifo_pfull : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ --tx_pma_div_clkout : out std_logic_vector(11 downto 0); -- tx_pma_div_clkout.clk
+
+ --rx_enh_blk_lock : out std_logic_vector(11 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
+ --rx_enh_data_valid : out std_logic_vector(11 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
+ --rx_enh_fifo_del : out std_logic_vector(11 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
+ --rx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ --rx_enh_fifo_full : out std_logic_vector(11 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
+ --rx_enh_fifo_insert : out std_logic_vector(11 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ --rx_enh_highber : out std_logic_vector(11 downto 0); -- rx_enh_highber.rx_enh_highber
+
+ --unused_rx_control : out std_logic_vector(287 downto 0); -- unused_rx_control.unused_rx_control
+ --unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
+ --unused_tx_control : in std_logic_vector(215 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
+ --unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ );
+
+ u_ip_arria10_e1sg_transceiver_reset_controller_12 : ip_arria10_e1sg_transceiver_reset_controller_12
+ PORT MAP (
+ clock => clk_156, -- : in std_logic := '0'; -- clock.clk
+ pll_locked => atx_pll_locked_arr(0 DOWNTO 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_powerdown => atx_pll_powerdown_arr(0 DOWNTO 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ reset => rst_156, -- : in std_logic := '0'; -- reset.reset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 DOWNTO 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ );
+ END GENERATE;
+
+
+
+
+ gen_phy_24 : IF c_nof_channels_per_ip=24 GENERATE
+ tx_serial_clk_slv <= (OTHERS=>tx_serial_clk(0));
+ tr_coreclkin_slv <= (OTHERS=>tr_coreclkin(0));
+
+ gen_channels : FOR I IN 0 TO g_nof_channels-1 GENERATE
+ tx_parallel_data_arr_slv((I+1)*c_xgmii_data_w-1 DOWNTO I*c_xgmii_data_w) <= tx_parallel_data_arr(I);
+ tx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes) <= tx_control_arr(I);
+
+ rx_parallel_data_arr(I) <= rx_parallel_data_arr_slv((I+1)*c_xgmii_data_w-1 DOWNTO I*c_xgmii_data_w);
+ rx_control_arr(I) <= rx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes);
+ END GENERATE;
+
+ u_ip_arria10_e1sg_phy_10gbase_r_24 : ip_arria10_e1sg_phy_10gbase_r_24
+ PORT MAP (
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+
+ --rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+
+ --tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
+ --rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
+
+ --tx_err_ins : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
+ --tx_enh_data_valid : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
+ --tx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ --tx_enh_fifo_full : out std_logic_vector(11 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
+ --tx_enh_fifo_pempty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ --tx_enh_fifo_pfull : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ --tx_pma_div_clkout : out std_logic_vector(11 downto 0); -- tx_pma_div_clkout.clk
+
+ --rx_enh_blk_lock : out std_logic_vector(11 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
+ --rx_enh_data_valid : out std_logic_vector(11 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
+ --rx_enh_fifo_del : out std_logic_vector(11 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
+ --rx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ --rx_enh_fifo_full : out std_logic_vector(11 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
+ --rx_enh_fifo_insert : out std_logic_vector(11 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ --rx_enh_highber : out std_logic_vector(11 downto 0); -- rx_enh_highber.rx_enh_highber
+
+ --unused_rx_control : out std_logic_vector(287 downto 0); -- unused_rx_control.unused_rx_control
+ --unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
+ --unused_tx_control : in std_logic_vector(215 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
+ --unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ );
+
+ u_ip_arria10_e1sg_transceiver_reset_controller_24 : ip_arria10_e1sg_transceiver_reset_controller_24
+ PORT MAP (
+ clock => clk_156, -- : in std_logic := '0'; -- clock.clk
+ pll_locked => atx_pll_locked_arr(0 DOWNTO 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_powerdown => atx_pll_powerdown_arr(0 DOWNTO 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ reset => rst_156, -- : in std_logic := '0'; -- reset.reset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 DOWNTO 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ );
+ END GENERATE;
+
+
+
+
+ gen_phy_48 : IF c_nof_channels_per_ip=48 GENERATE
+ tx_serial_clk_slv <= (OTHERS=>tx_serial_clk(0));
+ tr_coreclkin_slv <= (OTHERS=>tr_coreclkin(0));
+
+ gen_channels : FOR I IN 0 TO g_nof_channels-1 GENERATE
+ tx_parallel_data_arr_slv((I+1)*c_xgmii_data_w-1 DOWNTO I*c_xgmii_data_w) <= tx_parallel_data_arr(I);
+ tx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes) <= tx_control_arr(I);
+
+ rx_parallel_data_arr(I) <= rx_parallel_data_arr_slv((I+1)*c_xgmii_data_w-1 DOWNTO I*c_xgmii_data_w);
+ rx_control_arr(I) <= rx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes);
+ END GENERATE;
+
+ u_ip_arria10_e1sg_phy_10gbase_r_48 : ip_arria10_e1sg_phy_10gbase_r_48
+ PORT MAP (
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+
+ --rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+
+ --tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
+ --rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
+
+ --tx_err_ins : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
+ --tx_enh_data_valid : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
+ --tx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ --tx_enh_fifo_full : out std_logic_vector(11 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
+ --tx_enh_fifo_pempty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ --tx_enh_fifo_pfull : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ --tx_pma_div_clkout : out std_logic_vector(11 downto 0); -- tx_pma_div_clkout.clk
+
+ --rx_enh_blk_lock : out std_logic_vector(11 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
+ --rx_enh_data_valid : out std_logic_vector(11 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
+ --rx_enh_fifo_del : out std_logic_vector(11 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
+ --rx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ --rx_enh_fifo_full : out std_logic_vector(11 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
+ --rx_enh_fifo_insert : out std_logic_vector(11 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ --rx_enh_highber : out std_logic_vector(11 downto 0); -- rx_enh_highber.rx_enh_highber
+
+ --unused_rx_control : out std_logic_vector(287 downto 0); -- unused_rx_control.unused_rx_control
+ --unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
+ --unused_tx_control : in std_logic_vector(215 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
+ --unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ );
+
+ u_ip_arria10_e1sg_transceiver_reset_controller_48 : ip_arria10_e1sg_transceiver_reset_controller_48
+ PORT MAP (
+ clock => clk_156, -- : in std_logic := '0'; -- clock.clk
+ pll_locked => atx_pll_locked_arr(0 DOWNTO 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_powerdown => atx_pll_powerdown_arr(0 DOWNTO 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ reset => rst_156, -- : in std_logic := '0'; -- reset.reset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 DOWNTO 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ );
+ END GENERATE;
+
+
+ -- ATX PLL
+ u_ip_arria10_e1sg_transceiver_pll_10g : ip_arria10_e1sg_transceiver_pll_10g
+ PORT MAP (
+ pll_powerdown => atx_pll_powerdown_arr(0), -- only use reset controller 0 for ATX PLL power down, leave others not used
+ pll_refclk0 => tr_ref_clk_644,
+ pll_locked => atx_pll_locked,
+ pll_cal_busy => atx_pll_cal_busy,
+ mcgb_rst => atx_pll_powerdown_arr(0),
+ mcgb_serial_clk => tx_serial_clk(0)
+ );
+
+END str;
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd
index 9dc4cac6dc..de14ea8cf5 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd
@@ -794,4 +794,388 @@ PACKAGE tech_10gbase_r_component_pkg IS
);
END COMPONENT;
+ ------------------------------------------------------------------------------
+ -- ip_arria10_e1sg
+ ------------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_e1sg_phy_10gbase_r IS
+ PORT (
+ tx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy
+ rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy
+ tx_serial_clk0 : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
+ tx_serial_data : out std_logic_vector(0 downto 0); -- tx_serial_data.tx_serial_data
+ rx_serial_data : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_is_lockedtoref : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ tx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ rx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ tx_clkout : out std_logic_vector(0 downto 0); -- tx_clkout.clk
+ rx_clkout : out std_logic_vector(0 downto 0); -- rx_clkout.clk
+ tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ rx_parallel_data : out std_logic_vector(63 downto 0); -- rx_parallel_data.rx_parallel_data
+ tx_pma_div_clkout : out std_logic_vector(0 downto 0); -- tx_pma_div_clkout.clk
+ tx_control : in std_logic_vector(7 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_err_ins : in std_logic := '0'; -- tx_err_ins.tx_err_ins
+ unused_tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0'); -- unused_tx_parallel_data.unused_tx_parallel_data
+ unused_tx_control : in std_logic_vector(8 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
+ rx_control : out std_logic_vector(7 downto 0); -- rx_control.rx_control
+ unused_rx_parallel_data : out std_logic_vector(63 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_rx_control : out std_logic_vector(11 downto 0); -- unused_rx_control.unused_rx_control
+ tx_enh_data_valid : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_fifo_full : out std_logic_vector(0 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_pfull : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_pempty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ rx_enh_data_valid : out std_logic_vector(0 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_fifo_full : out std_logic_vector(0 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_del : out std_logic_vector(0 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_insert : out std_logic_vector(0 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_highber : out std_logic_vector(0 downto 0); -- rx_enh_highber.rx_enh_highber
+ rx_enh_blk_lock : out std_logic_vector(0 downto 0) -- rx_enh_blk_lock.rx_enh_blk_lock
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e1sg_phy_10gbase_r_4
+ port (
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read
+ reconfig_address : in std_logic_vector(11 downto 0) := (others => '0'); -- .address
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reconfig_readdata : out std_logic_vector(31 downto 0); -- .readdata
+ reconfig_waitrequest : out std_logic_vector(0 downto 0); -- .waitrequest
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_clk.clk
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_reset.reset
+ rx_analogreset : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_cal_busy : out std_logic_vector(3 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_clkout : out std_logic_vector(3 downto 0); -- rx_clkout.clk
+ rx_control : out std_logic_vector(31 downto 0); -- rx_control.rx_control
+ rx_coreclkin : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_digitalreset : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_enh_blk_lock : out std_logic_vector(3 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_data_valid : out std_logic_vector(3 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_fifo_del : out std_logic_vector(3 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_empty : out std_logic_vector(3 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_full : out std_logic_vector(3 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_insert : out std_logic_vector(3 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_highber : out std_logic_vector(3 downto 0); -- rx_enh_highber.rx_enh_highber
+ rx_is_lockedtodata : out std_logic_vector(3 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtoref : out std_logic_vector(3 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_parallel_data : out std_logic_vector(255 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_prbs_done : out std_logic_vector(3 downto 0); -- rx_prbs_done.rx_prbs_done
+ rx_prbs_err : out std_logic_vector(3 downto 0); -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err_clr : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_serial_data : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_seriallpbken : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
+ tx_analogreset : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_cal_busy : out std_logic_vector(3 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_clkout : out std_logic_vector(3 downto 0); -- tx_clkout.clk
+ tx_control : in std_logic_vector(31 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_coreclkin : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_digitalreset : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_enh_data_valid : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_fifo_empty : out std_logic_vector(3 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_full : out std_logic_vector(3 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_pempty : out std_logic_vector(3 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pfull : out std_logic_vector(3 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_err_ins : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
+ tx_parallel_data : in std_logic_vector(255 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_serial_clk0 : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_data : out std_logic_vector(3 downto 0); -- tx_serial_data.tx_serial_data
+ unused_rx_control : out std_logic_vector(47 downto 0); -- unused_rx_control.unused_rx_control
+ unused_rx_parallel_data : out std_logic_vector(255 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_tx_control : in std_logic_vector(35 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
+ unused_tx_parallel_data : in std_logic_vector(255 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e1sg_phy_10gbase_r_12
+ PORT (
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read
+ reconfig_address : in std_logic_vector(13 downto 0) := (others => '0'); -- .address
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reconfig_readdata : out std_logic_vector(31 downto 0); -- .readdata
+ reconfig_waitrequest : out std_logic_vector(0 downto 0); -- .waitrequest
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_clk.clk
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_reset.reset
+ rx_analogreset : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_cal_busy : out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
+ rx_control : out std_logic_vector(95 downto 0); -- rx_control.rx_control
+ rx_coreclkin : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_digitalreset : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_enh_blk_lock : out std_logic_vector(11 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_data_valid : out std_logic_vector(11 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_fifo_del : out std_logic_vector(11 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_full : out std_logic_vector(11 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_insert : out std_logic_vector(11 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_highber : out std_logic_vector(11 downto 0); -- rx_enh_highber.rx_enh_highber
+ rx_is_lockedtodata : out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_parallel_data : out std_logic_vector(767 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_prbs_done : out std_logic_vector(11 downto 0); -- rx_prbs_done.rx_prbs_done
+ rx_prbs_err : out std_logic_vector(11 downto 0); -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err_clr : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_serial_data : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_seriallpbken : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
+ tx_analogreset : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_cal_busy : out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
+ tx_control : in std_logic_vector(95 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_coreclkin : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_digitalreset : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_enh_data_valid : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_full : out std_logic_vector(11 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_pempty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pfull : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_err_ins : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
+ tx_parallel_data : in std_logic_vector(767 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_serial_clk0 : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_data : out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ unused_rx_control : out std_logic_vector(143 downto 0); -- unused_rx_control.unused_rx_control
+ unused_rx_parallel_data : out std_logic_vector(767 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_tx_control : in std_logic_vector(107 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
+ unused_tx_parallel_data : in std_logic_vector(767 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e1sg_phy_10gbase_r_24
+ PORT (
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read
+ reconfig_address : in std_logic_vector(14 downto 0) := (others => '0'); -- .address
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reconfig_readdata : out std_logic_vector(31 downto 0); -- .readdata
+ reconfig_waitrequest : out std_logic_vector(0 downto 0); -- .waitrequest
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_clk.clk
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_reset.reset
+ rx_analogreset : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_cal_busy : out std_logic_vector(23 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_clkout : out std_logic_vector(23 downto 0); -- rx_clkout.clk
+ rx_control : out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ rx_coreclkin : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_digitalreset : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_enh_blk_lock : out std_logic_vector(23 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_data_valid : out std_logic_vector(23 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_fifo_del : out std_logic_vector(23 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_empty : out std_logic_vector(23 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_full : out std_logic_vector(23 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_insert : out std_logic_vector(23 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_highber : out std_logic_vector(23 downto 0); -- rx_enh_highber.rx_enh_highber
+ rx_is_lockedtodata : out std_logic_vector(23 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtoref : out std_logic_vector(23 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_parallel_data : out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_prbs_done : out std_logic_vector(23 downto 0); -- rx_prbs_done.rx_prbs_done
+ rx_prbs_err : out std_logic_vector(23 downto 0); -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err_clr : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_serial_data : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_seriallpbken : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
+ tx_analogreset : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_cal_busy : out std_logic_vector(23 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_clkout : out std_logic_vector(23 downto 0); -- tx_clkout.clk
+ tx_control : in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_coreclkin : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_digitalreset : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_enh_data_valid : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_fifo_empty : out std_logic_vector(23 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_full : out std_logic_vector(23 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_pempty : out std_logic_vector(23 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pfull : out std_logic_vector(23 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_err_ins : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
+ tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_serial_clk0 : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_data : out std_logic_vector(23 downto 0); -- tx_serial_data.tx_serial_data
+ unused_rx_control : out std_logic_vector(287 downto 0); -- unused_rx_control.unused_rx_control
+ unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_tx_control : in std_logic_vector(215 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
+ unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e1sg_phy_10gbase_r_48
+ PORT (
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read
+ reconfig_address : in std_logic_vector(15 downto 0) := (others => '0'); -- .address
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reconfig_readdata : out std_logic_vector(31 downto 0); -- .readdata
+ reconfig_waitrequest : out std_logic_vector(0 downto 0); -- .waitrequest
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_clk.clk
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_reset.reset
+ rx_analogreset : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_cal_busy : out std_logic_vector(47 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_clkout : out std_logic_vector(47 downto 0); -- rx_clkout.clk
+ rx_control : out std_logic_vector(383 downto 0); -- rx_control.rx_control
+ rx_coreclkin : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_digitalreset : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_enh_blk_lock : out std_logic_vector(47 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_data_valid : out std_logic_vector(47 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_fifo_del : out std_logic_vector(47 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_empty : out std_logic_vector(47 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_full : out std_logic_vector(47 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_insert : out std_logic_vector(47 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_highber : out std_logic_vector(47 downto 0); -- rx_enh_highber.rx_enh_highber
+ rx_is_lockedtodata : out std_logic_vector(47 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtoref : out std_logic_vector(47 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_parallel_data : out std_logic_vector(3071 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_prbs_done : out std_logic_vector(47 downto 0); -- rx_prbs_done.rx_prbs_done
+ rx_prbs_err : out std_logic_vector(47 downto 0); -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err_clr : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_serial_data : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_seriallpbken : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
+ tx_analogreset : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_cal_busy : out std_logic_vector(47 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_clkout : out std_logic_vector(47 downto 0); -- tx_clkout.clk
+ tx_control : in std_logic_vector(383 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_coreclkin : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_digitalreset : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_enh_data_valid : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_fifo_empty : out std_logic_vector(47 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_full : out std_logic_vector(47 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_pempty : out std_logic_vector(47 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pfull : out std_logic_vector(47 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_err_ins : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
+ tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_serial_clk0 : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_data : out std_logic_vector(47 downto 0); -- tx_serial_data.tx_serial_data
+ unused_rx_control : out std_logic_vector(575 downto 0); -- unused_rx_control.unused_rx_control
+ unused_rx_parallel_data : out std_logic_vector(3071 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_tx_control : in std_logic_vector(431 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
+ unused_tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e1sg_transceiver_pll_10g IS
+ PORT (
+ mcgb_rst : in std_logic := '0'; -- mcgb_rst.mcgb_rst
+ mcgb_serial_clk : out std_logic; -- mcgb_serial_clk.clk
+ pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
+ pll_locked : out std_logic; -- pll_locked.pll_locked
+ pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
+ pll_refclk0 : in std_logic := '0'; -- pll_refclk0.clk
+ reconfig_write0 : in std_logic := '0'; -- reconfig_avmm0.write
+ reconfig_read0 : in std_logic := '0'; -- .read
+ reconfig_address0 : in std_logic_vector(9 downto 0) := (others => '0'); -- .address
+ reconfig_writedata0 : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reconfig_readdata0 : out std_logic_vector(31 downto 0); -- .readdata
+ reconfig_waitrequest0 : out std_logic; -- .waitrequest
+ reconfig_clk0 : in std_logic := '0'; -- reconfig_clk0.clk
+ reconfig_reset0 : in std_logic := '0'; -- reconfig_reset0.reset
+ tx_serial_clk : out std_logic -- tx_serial_clk.clk
+-- pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
+-- pll_refclk0 : in std_logic := '0'; -- pll_refclk0.clk
+-- pll_locked : out std_logic; -- pll_locked.pll_locked
+-- pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
+-- mcgb_rst : in std_logic := '0';
+-- mcgb_serial_clk : out std_logic -- tx_serial_clk.clk
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e1sg_transceiver_reset_controller_1 IS
+ PORT (
+ clock : in std_logic := '0'; -- clock.clk
+ reset : in std_logic := '0'; -- reset.reset
+ pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ tx_analogreset : out std_logic_vector(0 downto 0); -- tx_analogreset.tx_analogreset
+ tx_digitalreset : out std_logic_vector(0 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_ready : out std_logic_vector(0 downto 0); -- tx_ready.tx_ready
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ tx_cal_busy : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ rx_analogreset : out std_logic_vector(0 downto 0); -- rx_analogreset.rx_analogreset
+ rx_digitalreset : out std_logic_vector(0 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_ready : out std_logic_vector(0 downto 0); -- rx_ready.rx_ready
+ rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_cal_busy : in std_logic_vector(0 downto 0) := (others => '0') -- rx_cal_busy.rx_cal_busy
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e1sg_transceiver_reset_controller_4
+ port (
+ clock : in std_logic := '0'; -- clock.clk
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ reset : in std_logic := '0'; -- reset.reset
+ rx_analogreset : out std_logic_vector(3 downto 0); -- rx_analogreset.rx_analogreset
+ rx_cal_busy : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset : out std_logic_vector(3 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_ready : out std_logic_vector(3 downto 0); -- rx_ready.rx_ready
+ tx_analogreset : out std_logic_vector(3 downto 0); -- tx_analogreset.tx_analogreset
+ tx_cal_busy : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_digitalreset : out std_logic_vector(3 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_ready : out std_logic_vector(3 downto 0) -- tx_ready.tx_ready
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e1sg_transceiver_reset_controller_12
+ PORT (
+ clock : in std_logic := '0'; -- clock.clk
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ reset : in std_logic := '0'; -- reset.reset
+ rx_analogreset : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_ready : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ tx_analogreset : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_digitalreset : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_ready : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e1sg_transceiver_reset_controller_24
+ PORT (
+ clock : in std_logic := '0'; -- clock.clk
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ reset : in std_logic := '0'; -- reset.reset
+ rx_analogreset : out std_logic_vector(23 downto 0); -- rx_analogreset.rx_analogreset
+ rx_cal_busy : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset : out std_logic_vector(23 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_ready : out std_logic_vector(23 downto 0); -- rx_ready.rx_ready
+ tx_analogreset : out std_logic_vector(23 downto 0); -- tx_analogreset.tx_analogreset
+ tx_cal_busy : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_digitalreset : out std_logic_vector(23 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_ready : out std_logic_vector(23 downto 0) -- tx_ready.tx_ready
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e1sg_transceiver_reset_controller_48
+ PORT (
+ clock : in std_logic := '0'; -- clock.clk
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ reset : in std_logic := '0'; -- reset.reset
+ rx_analogreset : out std_logic_vector(47 downto 0); -- rx_analogreset.rx_analogreset
+ rx_cal_busy : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset : out std_logic_vector(47 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_ready : out std_logic_vector(47 downto 0); -- rx_ready.rx_ready
+ tx_analogreset : out std_logic_vector(47 downto 0); -- tx_analogreset.tx_analogreset
+ tx_cal_busy : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_digitalreset : out std_logic_vector(47 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_ready : out std_logic_vector(47 downto 0) -- tx_ready.tx_ready
+ );
+ END COMPONENT;
+
END tech_10gbase_r_component_pkg;
diff --git a/libraries/technology/clkbuf/hdllib.cfg b/libraries/technology/clkbuf/hdllib.cfg
index 65ae3c75e1..ea613dc680 100644
--- a/libraries/technology/clkbuf/hdllib.cfg
+++ b/libraries/technology/clkbuf/hdllib.cfg
@@ -1,12 +1,13 @@
hdl_lib_name = tech_clkbuf
hdl_library_clause_name = tech_clkbuf_lib
hdl_lib_uses_synth = technology common
-hdl_lib_uses_ip = ip_arria10_clkbuf_global ip_arria10_e3sge3_clkbuf_global
+hdl_lib_uses_ip = ip_arria10_clkbuf_global ip_arria10_e3sge3_clkbuf_global ip_arria10_e1sg_clkbuf_global
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_arria10_clkbuf_global ip_arria10_clkbuf_global_altclkctrl_150
ip_arria10_e3sge3_clkbuf_global ip_arria10_e3sge3_clkbuf_global_altclkctrl_151
+ ip_arria10_e1sg_clkbuf_global ip_arria10_e1sg_clkbuf_global_altclkctrl_151
synth_files =
tech_clkbuf_component_pkg.vhd
diff --git a/libraries/technology/clkbuf/tech_clkbuf.vhd b/libraries/technology/clkbuf/tech_clkbuf.vhd
index f7bb50c7ae..ef2500794b 100644
--- a/libraries/technology/clkbuf/tech_clkbuf.vhd
+++ b/libraries/technology/clkbuf/tech_clkbuf.vhd
@@ -28,6 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_clkbuf_global_altclkctrl_150;
LIBRARY ip_arria10_e3sge3_clkbuf_global_altclkctrl_151;
+LIBRARY ip_arria10_e1sg_clkbuf_global_altclkctrl_151;
ENTITY tech_clkbuf IS
GENERIC (
@@ -67,4 +68,17 @@ BEGIN
outclk => outclk -- outclk
);
END GENERATE;
+
+ -----------------------------------------------------------------------------
+ -- ip_arria10_e1sg
+ -----------------------------------------------------------------------------
+
+ gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg AND g_clock_net="GLOBAL" GENERATE
+ u0 : ip_arria10_e1sg_clkbuf_global
+ PORT MAP (
+ inclk => inclk, -- inclk
+ outclk => outclk -- outclk
+ );
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/clkbuf/tech_clkbuf_component_pkg.vhd b/libraries/technology/clkbuf/tech_clkbuf_component_pkg.vhd
index efc4c049e0..b398fe7481 100644
--- a/libraries/technology/clkbuf/tech_clkbuf_component_pkg.vhd
+++ b/libraries/technology/clkbuf/tech_clkbuf_component_pkg.vhd
@@ -49,5 +49,16 @@ PACKAGE tech_clkbuf_component_pkg IS
);
END COMPONENT;
+ -----------------------------------------------------------------------------
+ -- ip_arria10_e1sg
+ -----------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_e1sg_clkbuf_global IS
+ PORT (
+ inclk : in std_logic := '0'; -- altclkctrl_input.inclk
+ outclk : out std_logic -- altclkctrl_output.outclk
+ );
+ END COMPONENT;
+
END tech_clkbuf_component_pkg;
diff --git a/libraries/technology/ddr/hdllib.cfg b/libraries/technology/ddr/hdllib.cfg
index b05e8e080a..08c18b3366 100644
--- a/libraries/technology/ddr/hdllib.cfg
+++ b/libraries/technology/ddr/hdllib.cfg
@@ -13,6 +13,10 @@ hdl_lib_uses_ip = ip_stratixiv_ddr3_uphy_4g_800_master
ip_arria10_e3sge3_ddr4_8g_1600
ip_arria10_e3sge3_ddr4_4g_2000
ip_arria10_e3sge3_ddr4_8g_2400
+ ip_arria10_e1sg_ddr4_4g_1600
+ ip_arria10_e1sg_ddr4_8g_1600
+ ip_arria10_e1sg_ddr4_4g_2000
+ ip_arria10_e1sg_ddr4_8g_2400
hdl_lib_uses_sim = ip_stratixiv_ddr3_mem_model
ip_arria10_ddr4_mem_model_141
hdl_lib_technology =
@@ -29,6 +33,10 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e3sge3_ddr4_8g_1600 ip_arria10_e3sge3_ddr4_8g_1600_altera_emif_151
ip_arria10_e3sge3_ddr4_4g_2000 ip_arria10_e3sge3_ddr4_4g_2000_altera_emif_151
ip_arria10_e3sge3_ddr4_8g_2400 ip_arria10_e3sge3_ddr4_8g_2400_altera_emif_151
+ ip_arria10_e1sg_ddr4_4g_1600 ip_arria10_e1sg_ddr4_4g_1600_altera_emif_151
+ ip_arria10_e1sg_ddr4_8g_1600 ip_arria10_e1sg_ddr4_8g_1600_altera_emif_151
+ ip_arria10_e1sg_ddr4_4g_2000 ip_arria10_e1sg_ddr4_4g_2000_altera_emif_151
+ ip_arria10_e1sg_ddr4_8g_2400 ip_arria10_e1sg_ddr4_8g_2400_altera_emif_151
ip_stratixiv_ddr3_mem_model ip_stratixiv_ddr3_mem_model_lib
ip_arria10_ddr4_mem_model_141 ip_arria10_ddr4_mem_model_141
@@ -39,6 +47,7 @@ synth_files =
tech_ddr_stratixiv.vhd
tech_ddr_arria10.vhd
tech_ddr_arria10_e3sge3.vhd
+ tech_ddr_arria10_e1sg.vhd
tech_ddr.vhd
test_bench_files =
diff --git a/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd b/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd
new file mode 100644
index 0000000000..49f45f3b2e
--- /dev/null
+++ b/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd
@@ -0,0 +1,262 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+
+-- Purpose: DDR4 memory access component for Arria10.
+-- Description:
+-- Remarks:
+-- . The local_init_done goes high some time after power up. It could have been
+-- AND-ed with ctlr_miso.waitrequest_n. However the timing closure for
+-- ctlr_miso.waitrequest_n can be critical, so therefore it is better not
+-- to combinatorially load it with the AND local_init_done. Instead a
+-- ctlr_miso.done field was added and used to pass on local_init_done. In fact
+-- for normal operation it is sufficient to only wait for
+-- ctlr_miso.waitrequest_n. The ctlr_miso.init_done is then only used for
+-- DDR interface monitoring purposes.
+
+-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
+LIBRARY ip_arria10_e1sg_ddr4_4g_1600_altera_emif_151;
+LIBRARY ip_arria10_e1sg_ddr4_8g_1600_altera_emif_151;
+LIBRARY ip_arria10_e1sg_ddr4_4g_2000_altera_emif_151;
+LIBRARY ip_arria10_e1sg_ddr4_8g_2400_altera_emif_151;
+
+LIBRARY IEEE, technology_lib, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE work.tech_ddr_pkg.ALL;
+USE work.tech_ddr_component_pkg.ALL;
+
+ENTITY tech_ddr_arria10_e1sg IS
+ GENERIC (
+ g_tech_ddr : t_c_tech_ddr
+ );
+ PORT (
+ -- PLL reference clock
+ ref_clk : IN STD_LOGIC;
+ ref_rst : IN STD_LOGIC;
+
+ -- Controller user interface
+ ctlr_gen_clk : OUT STD_LOGIC;
+ ctlr_gen_rst : OUT STD_LOGIC;
+
+ ctlr_mosi : IN t_mem_ctlr_mosi;
+ ctlr_miso : OUT t_mem_ctlr_miso;
+
+ -- PHY interface
+ phy_in : IN t_tech_ddr4_phy_in;
+ phy_io : INOUT t_tech_ddr4_phy_io;
+ phy_ou : OUT t_tech_ddr4_phy_ou
+ );
+END tech_ddr_arria10_e1sg;
+
+
+ARCHITECTURE str OF tech_ddr_arria10_e1sg IS
+
+ CONSTANT c_gigabytes : NATURAL := func_tech_ddr_module_size(g_tech_ddr);
+
+ CONSTANT c_ctlr_address_w : NATURAL := func_tech_ddr_ctlr_address_w(g_tech_ddr);
+ CONSTANT c_ctlr_data_w : NATURAL := 576;--func_tech_ddr_ctlr_data_w( g_tech_ddr);
+
+ SIGNAL i_ctlr_gen_clk : STD_LOGIC;
+ SIGNAL ref_rst_n : STD_LOGIC;
+ SIGNAL ctlr_gen_rst_n : STD_LOGIC := '0';
+
+ SIGNAL local_cal_success : STD_LOGIC;
+ SIGNAL local_cal_fail : STD_LOGIC;
+
+BEGIN
+
+ ctlr_gen_clk <= i_ctlr_gen_clk;
+
+ ref_rst_n <= NOT ref_rst;
+ ctlr_gen_rst <= NOT ctlr_gen_rst_n;
+
+ gen_ip_arria10_e1sg_ddr4_4g_2000 : IF g_tech_ddr.name="DDR4" AND c_gigabytes=4 AND g_tech_ddr.mts=2000 GENERATE
+
+ phy_ou.cs_n(1) <= '1';
+ phy_ou.cke(1) <= '0';
+ phy_ou.odt(1) <= '0';
+
+ u_ip_arria10_e1sg_ddr4_4g_2000 : ip_arria10_e1sg_ddr4_4g_2000
+ PORT MAP (
+ amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_read_0 => ctlr_mosi.rd, -- .read
+ amm_write_0 => ctlr_mosi.wr, -- .write
+ amm_address_0 => ctlr_mosi.address(c_ctlr_address_w-1 DOWNTO 0), -- .address
+ amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w-1 DOWNTO 0), -- .readdata
+ amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w-1 DOWNTO 0), -- .writedata
+ amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w-1 DOWNTO 0), -- .burstcount
+ amm_byteenable_0 => (OTHERS=>'1'), -- .byteenable
+ amm_readdatavalid_0 => ctlr_miso.rdval, -- .readdatavalid
+ emif_usr_clk => i_ctlr_gen_clk, -- emif_usr_clk_clock_source.clk
+ emif_usr_reset_n => ctlr_gen_rst_n, -- emif_usr_reset_reset_source.reset_n
+ global_reset_n => ref_rst_n, -- global_reset_reset_sink.reset_n
+ mem_ck => phy_ou.ck(g_tech_ddr.ck_w-1 DOWNTO 0), -- mem_conduit_end.mem_ck
+ mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck_n
+ mem_a => phy_ou.a(g_tech_ddr.a_w-1 DOWNTO 0), -- .mem_a
+ sl(mem_act_n) => phy_ou.act_n, -- .mem_act_n
+ mem_ba => phy_ou.ba(g_tech_ddr.ba_w-1 DOWNTO 0), -- .mem_ba
+ mem_bg => phy_ou.bg(g_tech_ddr.bg_w-1 DOWNTO 0), -- .mem_bg
+ mem_cke => phy_ou.cke(g_tech_ddr.cke_w-1 DOWNTO 0), -- .mem_cke
+ mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n
+ mem_odt => phy_ou.odt(g_tech_ddr.odt_w-1 DOWNTO 0), -- .mem_odt
+ sl(mem_reset_n) => phy_ou.reset_n, -- .mem_reset_n
+ sl(mem_par) => phy_ou.par, -- .mem_par
+ mem_alert_n => slv(phy_in.alert_n), -- .mem_alert_n
+ mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs
+ mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n
+ mem_dq => phy_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- .mem_dq
+ mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w-1 DOWNTO 0), -- .mem_dbi_n
+ oct_rzqin => phy_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
+ pll_ref_clk => ref_clk, -- pll_ref_clk_clock_sink.clk
+ local_cal_success => local_cal_success, -- status_conduit_end.local_cal_success
+ local_cal_fail => local_cal_fail -- .local_cal_fail
+ );
+
+ -- Signals in DDR3 that are not available with DDR4:
+ --
+ --avl_burstbegin => ctlr_mosi.burstbegin, -- .beginbursttransfer
+ -- beginbursttransfer is obselete for new Avalon designs, because the slave can count valid data itself to know when a new burst starts
+ --
+ --local_init_done => ctlr_miso.done, -- status.local_init_done
+ -- local_init_done = ctlr_init_done originally and mapped to ctlr_miso.done for the DDR3 IP. For the DDR4 IP the local_cal_success and
+ -- NOT local_cal_fail seem to serve as local_init_done
+
+ ctlr_miso.done <= local_cal_success AND NOT local_cal_fail WHEN rising_edge(i_ctlr_gen_clk);
+ ctlr_miso.cal_ok <= local_cal_success;
+ ctlr_miso.cal_fail <= local_cal_fail;
+
+ END GENERATE;
+
+ gen_ip_arria10_e1sg_ddr4_4g_1600 : IF g_tech_ddr.name="DDR4" AND c_gigabytes=4 AND g_tech_ddr.mts=1600 GENERATE
+
+ phy_ou.cs_n(1) <= '1';
+ phy_ou.cke(1) <= '0';
+ phy_ou.odt(1) <= '0';
+
+ u_ip_arria10_e1sg_ddr4_4g_1600 : ip_arria10_e1sg_ddr4_4g_1600
+ PORT MAP (
+ amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_read_0 => ctlr_mosi.rd, -- .read
+ amm_write_0 => ctlr_mosi.wr, -- .write
+ amm_address_0 => ctlr_mosi.address(c_ctlr_address_w-1 DOWNTO 0), -- .address
+ amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w-1 DOWNTO 0), -- .readdata
+ amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w-1 DOWNTO 0), -- .writedata
+ amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w-1 DOWNTO 0), -- .burstcount
+ amm_byteenable_0 => (OTHERS=>'1'), -- .byteenable
+ amm_readdatavalid_0 => ctlr_miso.rdval, -- .readdatavalid
+ emif_usr_clk => i_ctlr_gen_clk, -- emif_usr_clk_clock_source.clk
+ emif_usr_reset_n => ctlr_gen_rst_n, -- emif_usr_reset_reset_source.reset_n
+ global_reset_n => ref_rst_n, -- global_reset_reset_sink.reset_n
+ mem_ck => phy_ou.ck(g_tech_ddr.ck_w-1 DOWNTO 0), -- mem_conduit_end.mem_ck
+ mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck_n
+ mem_a => phy_ou.a(g_tech_ddr.a_w-1 DOWNTO 0), -- .mem_a
+ sl(mem_act_n) => phy_ou.act_n, -- .mem_act_n
+ mem_ba => phy_ou.ba(g_tech_ddr.ba_w-1 DOWNTO 0), -- .mem_ba
+ mem_bg => phy_ou.bg(g_tech_ddr.bg_w-1 DOWNTO 0), -- .mem_bg
+ mem_cke => phy_ou.cke(g_tech_ddr.cke_w-1 DOWNTO 0), -- .mem_cke
+ mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n
+ mem_odt => phy_ou.odt(g_tech_ddr.odt_w-1 DOWNTO 0), -- .mem_odt
+ sl(mem_reset_n) => phy_ou.reset_n, -- .mem_reset_n
+ sl(mem_par) => phy_ou.par, -- .mem_par
+ mem_alert_n => slv(phy_in.alert_n), -- .mem_alert_n
+ mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs
+ mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n
+ mem_dq => phy_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- .mem_dq
+ mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w-1 DOWNTO 0), -- .mem_dbi_n
+ oct_rzqin => phy_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
+ pll_ref_clk => ref_clk, -- pll_ref_clk_clock_sink.clk
+ local_cal_success => local_cal_success, -- status_conduit_end.local_cal_success
+ local_cal_fail => local_cal_fail -- .local_cal_fail
+ );
+
+ -- Signals in DDR3 that are not available with DDR4:
+ --
+ --avl_burstbegin => ctlr_mosi.burstbegin, -- .beginbursttransfer
+ -- beginbursttransfer is obselete for new Avalon designs, because the slave can count valid data itself to know when a new burst starts
+ --
+ --local_init_done => ctlr_miso.done, -- status.local_init_done
+ -- local_init_done = ctlr_init_done originally and mapped to ctlr_miso.done for the DDR3 IP. For the DDR4 IP the local_cal_success and
+ -- NOT local_cal_fail seem to serve as local_init_done
+
+ ctlr_miso.done <= local_cal_success AND NOT local_cal_fail WHEN rising_edge(i_ctlr_gen_clk);
+ ctlr_miso.cal_ok <= local_cal_success;
+ ctlr_miso.cal_fail <= local_cal_fail;
+
+ END GENERATE;
+
+ gen_ip_arria10_e1sg_ddr4_8g_1600 : IF g_tech_ddr.name="DDR4" AND c_gigabytes=8 AND g_tech_ddr.mts=1600 GENERATE
+
+ u_ip_arria10_e1sg_ddr4_8g_1600 : ip_arria10_e1sg_ddr4_8g_1600
+ PORT MAP (
+ amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_read_0 => ctlr_mosi.rd, -- .read
+ amm_write_0 => ctlr_mosi.wr, -- .write
+ amm_address_0 => ctlr_mosi.address(c_ctlr_address_w-1 DOWNTO 0), -- .address
+ amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w-1 DOWNTO 0), -- .readdata
+ amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w-1 DOWNTO 0), -- .writedata
+ amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w-1 DOWNTO 0), -- .burstcount
+ amm_byteenable_0 => (OTHERS=>'1'), -- .byteenable
+ amm_readdatavalid_0 => ctlr_miso.rdval, -- .readdatavalid
+ emif_usr_clk => i_ctlr_gen_clk, -- emif_usr_clk_clock_source.clk
+ emif_usr_reset_n => ctlr_gen_rst_n, -- emif_usr_reset_reset_source.reset_n
+ global_reset_n => ref_rst_n, -- global_reset_reset_sink.reset_n
+ mem_ck => phy_ou.ck(g_tech_ddr.ck_w-1 DOWNTO 0), -- mem_conduit_end.mem_ck
+ mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck_n
+ mem_a => phy_ou.a(g_tech_ddr.a_w-1 DOWNTO 0), -- .mem_a
+ sl(mem_act_n) => phy_ou.act_n, -- .mem_act_n
+ mem_ba => phy_ou.ba(g_tech_ddr.ba_w-1 DOWNTO 0), -- .mem_ba
+ mem_bg => phy_ou.bg(g_tech_ddr.bg_w-1 DOWNTO 0), -- .mem_bg
+ mem_cke => phy_ou.cke(g_tech_ddr.cke_w-1 DOWNTO 0), -- .mem_cke
+ mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n
+ mem_odt => phy_ou.odt(g_tech_ddr.odt_w-1 DOWNTO 0), -- .mem_odt
+ sl(mem_reset_n) => phy_ou.reset_n, -- .mem_reset_n
+ sl(mem_par) => phy_ou.par, -- .mem_par
+ mem_alert_n => slv(phy_in.alert_n), -- .mem_alert_n
+ mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs
+ mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n
+ mem_dq => phy_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- .mem_dq
+ mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w-1 DOWNTO 0), -- .mem_dbi_n
+ oct_rzqin => phy_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
+ pll_ref_clk => ref_clk, -- pll_ref_clk_clock_sink.clk
+ local_cal_success => local_cal_success, -- status_conduit_end.local_cal_success
+ local_cal_fail => local_cal_fail -- .local_cal_fail
+ );
+
+ -- Signals in DDR3 that are not available with DDR4:
+ --
+ --avl_burstbegin => ctlr_mosi.burstbegin, -- .beginbursttransfer
+ -- beginbursttransfer is obselete for new Avalon designs, because the slave can count valid data itself to know when a new burst starts
+ --
+ --local_init_done => ctlr_miso.done, -- status.local_init_done
+ -- local_init_done = ctlr_init_done originally and mapped to ctlr_miso.done for the DDR3 IP. For the DDR4 IP the local_cal_success and
+ -- NOT local_cal_fail seem to serve as local_init_done
+
+ ctlr_miso.done <= local_cal_success AND NOT local_cal_fail WHEN rising_edge(i_ctlr_gen_clk);
+ ctlr_miso.cal_ok <= local_cal_success;
+ ctlr_miso.cal_fail <= local_cal_fail;
+
+ END GENERATE;
+
+END str;
diff --git a/libraries/technology/ddr/tech_ddr_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
index 90b2764098..2c34cc0b1d 100644
--- a/libraries/technology/ddr/tech_ddr_component_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
@@ -487,6 +487,124 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
+ ------------------------------------------------------------------------------
+ -- ip_arria10_e1sg
+ ------------------------------------------------------------------------------
+
+ -- Manually derived VHDL entity from VHDL file $RADIOHDL/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim/ip_arria10_e1sg_ddr4_4g_1600.vhd
+ COMPONENT ip_arria10_e1sg_ddr4_4g_1600 IS
+ PORT (
+ amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_read_0 : in std_logic := '0'; -- .read
+ amm_write_0 : in std_logic := '0'; -- .write
+ amm_address_0 : in std_logic_vector(25 downto 0) := (others => '0'); -- .address
+ amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
+ amm_readdatavalid_0 : out std_logic; -- .readdatavalid
+ emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
+ emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
+ global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
+ mem_ck : out std_logic_vector(0 downto 0); -- mem_conduit_end.mem_ck
+ mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n
+ mem_a : out std_logic_vector(16 downto 0); -- .mem_a
+ mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
+ mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
+ mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
+ mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
+ mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
+ mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
+ mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
+ mem_par : out std_logic_vector(0 downto 0); -- .mem_par
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
+ oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
+ pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
+ local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
+ local_cal_fail : out std_logic -- .local_cal_fail
+ );
+ END COMPONENT;
+
+ -- Dual rank version of ip_arria10_e1sg_ddr4_4g_1600.vhd
+ COMPONENT ip_arria10_e1sg_ddr4_8g_1600 IS
+ PORT (
+ amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_read_0 : in std_logic := '0'; -- .read
+ amm_write_0 : in std_logic := '0'; -- .write
+ amm_address_0 : in std_logic_vector(26 downto 0) := (others => '0'); -- .address
+ amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
+ amm_readdatavalid_0 : out std_logic; -- .readdatavalid
+ emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
+ emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
+ global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
+ mem_ck : out std_logic_vector(1 downto 0); -- mem_conduit_end.mem_ck
+ mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
+ mem_a : out std_logic_vector(16 downto 0); -- .mem_a
+ mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
+ mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
+ mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
+ mem_cke : out std_logic_vector(1 downto 0); -- .mem_cke
+ mem_cs_n : out std_logic_vector(1 downto 0); -- .mem_cs_n
+ mem_odt : out std_logic_vector(1 downto 0); -- .mem_odt
+ mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
+ mem_par : out std_logic_vector(0 downto 0); -- .mem_par
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
+ oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
+ pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
+ local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
+ local_cal_fail : out std_logic -- .local_cal_fail
+ );
+ END COMPONENT;
+
+ -- Manually derived VHDL entity from VHDL file $RADIOHDL/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim/ip_arria10_e1sg_ddr4_4g_2000.vhd
+ COMPONENT ip_arria10_e1sg_ddr4_4g_2000 IS
+ PORT (
+ amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_read_0 : in std_logic := '0'; -- .read
+ amm_write_0 : in std_logic := '0'; -- .write
+ amm_address_0 : in std_logic_vector(25 downto 0) := (others => '0'); -- .address
+ amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
+ amm_readdatavalid_0 : out std_logic; -- .readdatavalid
+ emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
+ emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
+ global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
+ mem_ck : out std_logic_vector(0 downto 0); -- mem_conduit_end.mem_ck
+ mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n
+ mem_a : out std_logic_vector(16 downto 0); -- .mem_a
+ mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
+ mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
+ mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
+ mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
+ mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
+ mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
+ mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
+ mem_par : out std_logic_vector(0 downto 0); -- .mem_par
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
+ oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
+ pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
+ local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
+ local_cal_fail : out std_logic -- .local_cal_fail
+ );
+ END COMPONENT;
+
END tech_ddr_component_pkg;
PACKAGE BODY tech_ddr_component_pkg IS
diff --git a/libraries/technology/eth_10g/hdllib.cfg b/libraries/technology/eth_10g/hdllib.cfg
index 2a96d0c0c9..f481d799cb 100644
--- a/libraries/technology/eth_10g/hdllib.cfg
+++ b/libraries/technology/eth_10g/hdllib.cfg
@@ -8,6 +8,7 @@ synth_files =
tech_eth_10g_stratixiv.vhd
tech_eth_10g_arria10.vhd
tech_eth_10g_arria10_e3sge3.vhd
+ tech_eth_10g_arria10_e1sg.vhd
tech_eth_10g_clocks.vhd
tech_eth_10g.vhd
diff --git a/libraries/technology/eth_10g/tech_eth_10g.vhd b/libraries/technology/eth_10g/tech_eth_10g.vhd
index 424f30731f..5270cb8e4c 100644
--- a/libraries/technology/eth_10g/tech_eth_10g.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g.vhd
@@ -258,4 +258,46 @@ BEGIN
serial_rx_arr => serial_rx_arr
);
END GENERATE;
+
+ gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
+ u0 : ENTITY work.tech_eth_10g_arria10_e1sg
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_nof_channels => g_nof_channels,
+ g_direction => g_direction,
+ g_pre_header_padding => g_pre_header_padding
+ )
+ PORT MAP (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => tr_ref_clk_644,
+
+ -- Data clocks
+ clk_312 => tr_ref_clk_312,
+ clk_156 => tr_ref_clk_156,
+ rst_156 => tr_ref_rst_156,
+
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ mac_mosi => mac_mosi,
+ mac_miso => mac_miso,
+
+ reg_eth10g_mosi => reg_eth10g_mosi,
+ reg_eth10g_miso => reg_eth10g_miso,
+
+ -- ST
+ tx_snk_in_arr => tx_snk_in_arr, -- 64 bit data @ tr_ref_clk_156
+ tx_snk_out_arr => tx_snk_out_arr,
+
+ rx_src_out_arr => rx_src_out_arr, -- 64 bit data @ tr_ref_clk_156
+ rx_src_in_arr => rx_src_in_arr,
+
+ -- Serial
+ serial_tx_arr => serial_tx_arr,
+ serial_rx_arr => serial_rx_arr
+ );
+ END GENERATE;
+
END str;
diff --git a/libraries/technology/eth_10g/tech_eth_10g_arria10_e1sg.vhd b/libraries/technology/eth_10g/tech_eth_10g_arria10_e1sg.vhd
new file mode 100644
index 0000000000..6e9eb12a02
--- /dev/null
+++ b/libraries/technology/eth_10g/tech_eth_10g_arria10_e1sg.vhd
@@ -0,0 +1,314 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+
+-- Purpose: Combine mac_10g and 10gbase_r for c_tech_arria10_e1sg
+-- Description
+--
+-- The clocks come from an external central fPLL:
+--
+-- tx_ref_clk_644 --> fPLL --> clk_312
+-- clk_156, rst_156
+-- Blockdiagram:
+--
+-- 312 156 644
+-- _________ | | | ____________
+-- | | | | | | |
+-- | |<--/ | \-->| |
+-- | |<-----+----->| |
+-- | | | |
+-- | | XGMII | |
+-- tx_snk --->|tech_ |------------>|tech_ |---> serial_tx
+-- rx_src <---|mac_10g|<------------|10gbase_r |<--- serial_rx
+-- | | | |
+-- |_______|--\ /--|__________|
+-- | | |
+-- mac_mm | |
+-- | v
+-- ( v xgmii_tx_ready)
+-- tx_snk_out.xon <--(xgmii_link_status[1:0])
+--
+-- . g_direction:
+-- "TX_RX" = Default support bidir
+-- "TX_ONLY" = Uses a bidir MAC and connects the MAC Tx to the MAC RX.
+-- "RX_ONLY" = Same as "TX_RX"
+-- See tech_eth_10g_stratixiv.vhd for more details.
+--
+-- Remarks:
+-- . xgmii_link_status:
+-- When the xgmii_tx_ready from the 10gbase_r and the xgmii_link_status from
+-- the mac_10g are both be OK then the tx_snk.xon is asserted to allow the
+-- user data transmission.
+-- The tb_tech_eth_10g reveals that xgmii_tx_ready goes high after some power
+-- up time and then remains active independent of link_fault.
+-- A link fault eg. due to rx disconnect is detected by the link fault status:
+-- 0 = OK
+-- 1 = local fault
+-- 2 = remote fault
+--
+-- From google search:
+-- Link fault Operation
+-- 1) Device B detects loss of signal. Local fault is signaled by PHY of Device B to Device B.
+-- 2) Device B ceases transmission of MAC frames and transmits remote fault to Device A.
+-- 3) Device A receives remote fault from Device B.
+-- 4) Device A stops sending frames, continuously generates Idle.
+--
+-- Hence when the xgmii_link_status is OK then the other side is also OK so
+-- then it is also appropriate to release tx_snk.xon.
+--
+-- The XGMII link status can be monitored via the reg_eth10 MM register:
+--
+-- addr data[31:0]
+-- 0 [0] = tx_snk_out_arr(I).xon
+-- [1] = xgmii_tx_ready_arr(I)
+-- [3:2] = xgmii_link_status_arr(I)
+--
+
+LIBRARY IEEE, common_lib, dp_lib, technology_lib, tech_10gbase_r_lib, tech_mac_10g_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_interface_layers_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE tech_mac_10g_lib.tech_mac_10g_component_pkg.ALL;
+
+ENTITY tech_eth_10g_arria10_e1sg IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model
+ g_nof_channels : NATURAL := 1;
+ g_direction : STRING := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_pre_header_padding : BOOLEAN := FALSE
+ );
+ PORT (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 : IN STD_LOGIC := '0'; -- 644.531250 MHz for 10GBASE-R
+
+ -- Data clocks
+ clk_312 : IN STD_LOGIC := '0';
+ clk_156 : IN STD_LOGIC := '0';
+ rst_156 : IN STD_LOGIC := '0';
+
+ -- MM
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+
+ mac_mosi : IN t_mem_mosi; -- MAG_10G (CSR)
+ mac_miso : OUT t_mem_miso;
+
+ reg_eth10g_mosi : IN t_mem_mosi; -- ETH10G (link status register)
+ reg_eth10g_miso : OUT t_mem_miso;
+
+ -- ST
+ tx_snk_in_arr : IN t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ clk_156
+ tx_snk_out_arr : OUT t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
+
+ rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ clk_156
+ rx_src_in_arr : IN t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
+
+ -- Serial
+ serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
+ );
+END tech_eth_10g_arria10_e1sg;
+
+
+ARCHITECTURE str OF tech_eth_10g_arria10_e1sg IS
+
+ -- Enable or disable the conditions that must be ok to release tx_snk_out_arr xon
+ CONSTANT c_check_link_status : BOOLEAN := g_direction/="TX_ONLY";
+ CONSTANT c_check_xgmii_tx_ready : BOOLEAN := g_direction/="RX_ONLY";
+
+ SIGNAL i_tx_snk_out_arr : t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
+
+ -- MAG_10G control status registers
+ SIGNAL mac_mosi_arr : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
+ SIGNAL mac_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0);
+
+ -- XON control
+ SIGNAL mac_snk_out_arr : t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
+
+ -- XGMII
+ SIGNAL xgmii_link_status_arr : t_tech_mac_10g_xgmii_status_arr(g_nof_channels-1 DOWNTO 0); -- 2 bit, from MAC_10g
+ SIGNAL xgmii_tx_ready_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- 1 bit, from PHY 10gbase_r
+ SIGNAL xgmii_tx_dc_arr : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
+ SIGNAL xgmii_rx_dc_arr : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
+ SIGNAL xgmii_internal_dc_arr : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
+
+ -- Link status monitor
+ CONSTANT c_mem_reg_eth10g_adr_w : NATURAL := 1;
+ CONSTANT c_mem_reg_eth10g_dat_w : NATURAL := 32;
+ CONSTANT c_mem_reg_eth10g_nof_data : NATURAL := 1;
+ CONSTANT c_mem_reg_eth10g : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_eth10g_adr_w , c_mem_reg_eth10g_dat_w , c_mem_reg_eth10g_nof_data, 'X');
+
+ SIGNAL reg_eth10g_mosi_arr : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
+ SIGNAL reg_eth10g_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0);
+
+ SIGNAL mm_reg_eth10g_arr : t_slv_32_arr(g_nof_channels-1 DOWNTO 0);
+
+BEGIN
+ tx_snk_out_arr <= i_tx_snk_out_arr;
+
+ gen_mac : FOR I IN 0 TO g_nof_channels-1 GENERATE
+
+ i_tx_snk_out_arr(I).ready <= mac_snk_out_arr(I).ready; -- pass on MAC cycle accurate backpressure
+
+ p_xon_flow_control : PROCESS(clk_156)
+ VARIABLE v_xgmii_link_status : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0) := "00";
+ VARIABLE v_xgmii_tx_ready : STD_LOGIC := '1';
+ BEGIN
+ IF rising_edge(clk_156) THEN
+ i_tx_snk_out_arr(I).xon <= '0';
+
+ -- First gather all conditions that are enabled to affect xon. The default value is such that it enables xon when the condition is not checked.
+ IF c_check_link_status =TRUE THEN v_xgmii_link_status := xgmii_link_status_arr(I); END IF; -- check both remote fault [1] and local fault [0]
+ IF c_check_xgmii_tx_ready=TRUE THEN v_xgmii_tx_ready := xgmii_tx_ready_arr(I); END IF;
+
+ -- Now apply the conditions to xon
+ IF v_xgmii_tx_ready='1' AND v_xgmii_link_status="00" THEN
+ i_tx_snk_out_arr(I).xon <= '1'; -- XON when Tx PHY is ready and XGMII is ok
+ END IF;
+ END IF;
+ END PROCESS;
+
+ u_tech_mac_10g : ENTITY tech_mac_10g_lib.tech_mac_10g
+ GENERIC MAP (
+ g_technology => c_tech_arria10_e1sg,
+ g_pre_header_padding => g_pre_header_padding
+ )
+ PORT MAP (
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ csr_mosi => mac_mosi_arr(I),
+ csr_miso => mac_miso_arr(I),
+
+ -- ST
+ tx_clk_312 => clk_312,
+ tx_clk_156 => clk_156,
+ tx_rst => rst_156,
+ tx_snk_in => tx_snk_in_arr(I), -- 64 bit data
+ tx_snk_out => mac_snk_out_arr(I),
+
+ rx_clk_312 => clk_312,
+ rx_clk_156 => clk_156,
+ rx_rst => rst_156,
+ rx_src_out => rx_src_out_arr(I), -- 64 bit data
+ rx_src_in => rx_src_in_arr(I),
+
+ -- XGMII
+ xgmii_link_status => xgmii_link_status_arr(I),
+ xgmii_tx_data => xgmii_tx_dc_arr(I),
+ xgmii_rx_data => xgmii_internal_dc_arr(I)
+ );
+ END GENERATE;
+
+ xgmii_internal_dc_arr <= xgmii_tx_dc_arr WHEN g_direction="TX_ONLY" ELSE xgmii_rx_dc_arr;
+
+ u_tech_10gbase_r: ENTITY tech_10gbase_r_lib.tech_10gbase_r
+ GENERIC MAP (
+ g_technology => c_tech_arria10_e1sg,
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_nof_channels => g_nof_channels
+ )
+ PORT MAP (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => tr_ref_clk_644,
+
+ -- XGMII clocks
+ clk_156 => clk_156,
+ rst_156 => rst_156,
+
+ -- XGMII interface
+ xgmii_tx_ready_arr => xgmii_tx_ready_arr,
+ xgmii_rx_ready_arr => OPEN,
+ xgmii_tx_dc_arr => xgmii_tx_dc_arr,
+ xgmii_rx_dc_arr => xgmii_rx_dc_arr,
+
+ -- PHY serial IO
+ tx_serial_arr => serial_tx_arr,
+ rx_serial_arr => serial_rx_arr
+ );
+
+
+ gen_reg_eth10g : FOR I IN 0 TO g_nof_channels-1 GENERATE
+ mm_reg_eth10g_arr(I) <= RESIZE_UVEC(xgmii_link_status_arr(I) & xgmii_tx_ready_arr(I) & i_tx_snk_out_arr(I).xon, c_mem_reg_eth10g_dat_w);
+
+ u_reg_map : ENTITY common_lib.common_reg_r_w_dc
+ GENERIC MAP (
+ g_cross_clock_domain => TRUE,
+ g_in_new_latency => 0,
+ g_readback => FALSE,
+ g_reg => c_mem_reg_eth10g,
+ g_init_reg => (OTHERS => '0')
+ )
+ PORT MAP (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => rst_156,
+ st_clk => clk_156,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_eth10g_mosi_arr(I),
+ sla_out => reg_eth10g_miso_arr(I),
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_new => '1',
+ in_reg => mm_reg_eth10g_arr(I),
+ out_reg => OPEN
+ );
+ END GENERATE;
+
+
+ -----------------------------------------------------------------------------
+ -- MM bus mux
+ -----------------------------------------------------------------------------
+ u_common_mem_mux_mac : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => g_nof_channels,
+ g_mult_addr_w => func_tech_mac_10g_csr_addr_w(c_tech_arria10)
+ )
+ PORT MAP (
+ mosi => mac_mosi,
+ miso => mac_miso,
+ mosi_arr => mac_mosi_arr,
+ miso_arr => mac_miso_arr
+ );
+
+ u_common_mem_mux_eth10g : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => g_nof_channels,
+ g_mult_addr_w => c_mem_reg_eth10g_adr_w
+ )
+ PORT MAP (
+ mosi => reg_eth10g_mosi,
+ miso => reg_eth10g_miso,
+ mosi_arr => reg_eth10g_mosi_arr,
+ miso_arr => reg_eth10g_miso_arr
+ );
+
+END str;
diff --git a/libraries/technology/eth_10g/tech_eth_10g_clocks.vhd b/libraries/technology/eth_10g/tech_eth_10g_clocks.vhd
index c8c653f2a1..2e9f9805f0 100644
--- a/libraries/technology/eth_10g/tech_eth_10g_clocks.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g_clocks.vhd
@@ -85,7 +85,7 @@ BEGIN
eth_rx_rst_arr <= rx_rst_arr;
END GENERATE;
- gen_clocks_10gbase_r : IF g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 GENERATE
+ gen_clocks_10gbase_r : IF g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg GENERATE
eth_tx_clk_arr <= (OTHERS=>tr_ref_clk_156);
eth_tx_rst_arr <= (OTHERS=>tr_ref_rst_156);
diff --git a/libraries/technology/fifo/hdllib.cfg b/libraries/technology/fifo/hdllib.cfg
index d9be8a27aa..94cd2d59f2 100644
--- a/libraries/technology/fifo/hdllib.cfg
+++ b/libraries/technology/fifo/hdllib.cfg
@@ -1,12 +1,13 @@
hdl_lib_name = tech_fifo
hdl_library_clause_name = tech_fifo_lib
-hdl_lib_uses_synth = technology ip_stratixiv_fifo ip_arria10_fifo ip_arria10_e3sge3_fifo
+hdl_lib_uses_synth = technology ip_stratixiv_fifo ip_arria10_fifo ip_arria10_e3sge3_fifo ip_arria10_e1sg_fifo
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_stratixiv_fifo ip_stratixiv_fifo_lib
ip_arria10_fifo ip_arria10_fifo_lib
ip_arria10_e3sge3_fifo ip_arria10_e3sge3_fifo_lib
+ ip_arria10_e1sg_fifo ip_arria10_e1sg_fifo_lib
synth_files =
tech_fifo_component_pkg.vhd
diff --git a/libraries/technology/fifo/tech_fifo_component_pkg.vhd b/libraries/technology/fifo/tech_fifo_component_pkg.vhd
index 69b2209adb..7ba288c714 100644
--- a/libraries/technology/fifo/tech_fifo_component_pkg.vhd
+++ b/libraries/technology/fifo/tech_fifo_component_pkg.vhd
@@ -222,5 +222,70 @@ PACKAGE tech_fifo_component_pkg IS
);
END COMPONENT;
+ -----------------------------------------------------------------------------
+ -- ip_arria10_e1sg
+ -----------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_e1sg_fifo_sc IS
+ GENERIC (
+ g_use_eab : STRING := "ON";
+ g_dat_w : NATURAL := 20;
+ g_nof_words : NATURAL := 1024
+ );
+ PORT (
+ aclr : IN STD_LOGIC ;
+ clock : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdreq : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ empty : OUT STD_LOGIC ;
+ full : OUT STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
+ usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e1sg_fifo_dc IS
+ GENERIC (
+ g_use_eab : STRING := "ON";
+ g_dat_w : NATURAL := 20;
+ g_nof_words : NATURAL := 1024
+ );
+ PORT (
+ aclr : IN STD_LOGIC := '0';
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ rdreq : IN STD_LOGIC ;
+ wrclk : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdempty : OUT STD_LOGIC ;
+ rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
+ wrfull : OUT STD_LOGIC ;
+ wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e1sg_fifo_dc_mixed_widths IS
+ GENERIC (
+ g_nof_words : NATURAL := 1024; -- FIFO size in nof wr_dat words
+ g_wrdat_w : NATURAL := 20;
+ g_rddat_w : NATURAL := 10
+ );
+ PORT (
+ aclr : IN STD_LOGIC := '0';
+ data : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ rdreq : IN STD_LOGIC ;
+ wrclk : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
+ rdempty : OUT STD_LOGIC ;
+ rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
+ wrfull : OUT STD_LOGIC ;
+ wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
END tech_fifo_component_pkg;
diff --git a/libraries/technology/fifo/tech_fifo_dc.vhd b/libraries/technology/fifo/tech_fifo_dc.vhd
index f19df9a1b4..f51d503dbf 100644
--- a/libraries/technology/fifo/tech_fifo_dc.vhd
+++ b/libraries/technology/fifo/tech_fifo_dc.vhd
@@ -29,6 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_fifo_lib;
LIBRARY ip_arria10_fifo_lib;
LIBRARY ip_arria10_e3sge3_fifo_lib;
+LIBRARY ip_arria10_e1sg_fifo_lib;
ENTITY tech_fifo_dc IS
GENERIC (
@@ -75,4 +76,10 @@ BEGIN
PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
END GENERATE;
+ gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
+ u0 : ip_arria10_e1sg_fifo_dc
+ GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
+ PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
index b0b982ff7e..d1219d60eb 100644
--- a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
@@ -29,6 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_fifo_lib;
LIBRARY ip_arria10_fifo_lib;
LIBRARY ip_arria10_e3sge3_fifo_lib;
+LIBRARY ip_arria10_e1sg_fifo_lib;
ENTITY tech_fifo_dc_mixed_widths IS
GENERIC (
@@ -75,4 +76,10 @@ BEGIN
PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
END GENERATE;
+ gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
+ u0 : ip_arria10_e1sg_fifo_dc_mixed_widths
+ GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
+ PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/fifo/tech_fifo_sc.vhd b/libraries/technology/fifo/tech_fifo_sc.vhd
index ee60048e85..88fae12daf 100644
--- a/libraries/technology/fifo/tech_fifo_sc.vhd
+++ b/libraries/technology/fifo/tech_fifo_sc.vhd
@@ -29,6 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_fifo_lib;
LIBRARY ip_arria10_fifo_lib;
LIBRARY ip_arria10_e3sge3_fifo_lib;
+LIBRARY ip_arria10_e1sg_fifo_lib;
ENTITY tech_fifo_sc IS
GENERIC (
@@ -72,5 +73,11 @@ BEGIN
GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
END GENERATE;
+
+ gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
+ u0 : ip_arria10_e1sg_fifo_sc
+ GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
+ PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
+ END GENERATE;
END ARCHITECTURE;
diff --git a/libraries/technology/flash/hdllib.cfg b/libraries/technology/flash/hdllib.cfg
index 4d9a2baef1..4424eaa642 100644
--- a/libraries/technology/flash/hdllib.cfg
+++ b/libraries/technology/flash/hdllib.cfg
@@ -6,6 +6,8 @@ hdl_lib_uses_synth = technology
ip_arria10_remote_update
ip_arria10_e3sge3_asmi_parallel
ip_arria10_e3sge3_remote_update
+ ip_arria10_e1sg_asmi_parallel
+ ip_arria10_e1sg_remote_update
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
@@ -14,6 +16,8 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_remote_update ip_arria10_remote_update_altera_remote_update_150
ip_arria10_e3sge3_asmi_parallel ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151
ip_arria10_e3sge3_remote_update ip_arria10_e3sge3_remote_update_altera_remote_update_151
+ ip_arria10_e1sg_asmi_parallel ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_151
+ ip_arria10_e1sg_remote_update ip_arria10_e1sg_remote_update_altera_remote_update_151
synth_files =
tech_flash_component_pkg.vhd
diff --git a/libraries/technology/flash/tech_flash_asmi_parallel.vhd b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
index 2de89479dd..e6bb150696 100644
--- a/libraries/technology/flash/tech_flash_asmi_parallel.vhd
+++ b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
@@ -31,6 +31,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_flash_lib;
LIBRARY ip_arria10_asmi_parallel_altera_asmi_parallel_150;
LIBRARY ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151;
+LIBRARY ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_151;
ENTITY tech_flash_asmi_parallel IS
GENERIC (
@@ -83,4 +84,9 @@ BEGIN
PORT MAP (addr, clkin, datain, rden, read, sector_erase, shift_bytes, wren, write, busy, data_valid, dataout, illegal_erase, illegal_write, reset, sce, en4b_addr);
END GENERATE;
+ gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
+ u0 : ip_arria10_e1sg_asmi_parallel
+ PORT MAP (addr, clkin, datain, rden, read, sector_erase, shift_bytes, wren, write, busy, data_valid, dataout, illegal_erase, illegal_write, reset, sce, en4b_addr);
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/flash/tech_flash_component_pkg.vhd b/libraries/technology/flash/tech_flash_component_pkg.vhd
index d2a779e93e..240ada1756 100644
--- a/libraries/technology/flash/tech_flash_component_pkg.vhd
+++ b/libraries/technology/flash/tech_flash_component_pkg.vhd
@@ -154,6 +154,47 @@ PACKAGE tech_flash_component_pkg IS
);
end component ip_arria10_e3sge3_remote_update;
+ -----------------------------------------------------------------------------
+ -- ip_arria10_e1sg
+ -----------------------------------------------------------------------------
+
+ component ip_arria10_e1sg_asmi_parallel is
+ port (
+ addr : in std_logic_vector(31 downto 0);
+ clkin : in std_logic;
+ datain : in std_logic_vector(7 downto 0);
+ rden : in std_logic;
+ read : in std_logic;
+ sector_erase : in std_logic;
+ shift_bytes : in std_logic;
+ wren : in std_logic;
+ write : in std_logic;
+ busy : out std_logic;
+ data_valid : out std_logic;
+ dataout : out std_logic_vector(7 downto 0);
+ illegal_erase : out std_logic;
+ illegal_write : out std_logic;
+ reset : in std_logic;
+ sce : in std_logic_vector(2 downto 0);
+ en4b_addr : in std_logic
+ );
+ end component ip_arria10_e1sg_asmi_parallel;
+
+ component ip_arria10_e1sg_remote_update is
+ port (
+ clock : in std_logic;
+ data_in : in std_logic_vector(31 downto 0);
+ param : in std_logic_vector(2 downto 0);
+ read_param : in std_logic;
+ reconfig : in std_logic;
+ reset : in std_logic;
+ reset_timer : in std_logic;
+ write_param : in std_logic;
+ busy : out std_logic;
+ data_out : out std_logic_vector(31 downto 0)
+ );
+ end component ip_arria10_e1sg_remote_update;
+
function tech_flash_addr_w( technology: in integer ) return integer;
function tech_flash_data_w( technology: in integer ) return integer;
@@ -169,7 +210,7 @@ package body tech_flash_component_pkg is
if technology = c_tech_arria10 then
return 32;
end if;
- if technology = c_tech_arria10_e3sge3 then
+ if technology = c_tech_arria10_e3sge3 or technology = c_tech_arria10_e1sg then
return 32;
end if;
end;
@@ -182,7 +223,7 @@ package body tech_flash_component_pkg is
if technology = c_tech_arria10 then
return 32;
end if;
- if technology = c_tech_arria10_e3sge3 then
+ if technology = c_tech_arria10_e3sge3 or technology = c_tech_arria10_e1sg then
return 32;
end if;
end;
diff --git a/libraries/technology/flash/tech_flash_remote_update.vhd b/libraries/technology/flash/tech_flash_remote_update.vhd
index 17c360efb8..3d387c1e54 100644
--- a/libraries/technology/flash/tech_flash_remote_update.vhd
+++ b/libraries/technology/flash/tech_flash_remote_update.vhd
@@ -31,6 +31,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_flash_lib;
LIBRARY ip_arria10_remote_update_altera_remote_update_150;
LIBRARY ip_arria10_e3sge3_remote_update_altera_remote_update_151;
+LIBRARY ip_arria10_e1sg_remote_update_altera_remote_update_151;
ENTITY tech_flash_remote_update IS
GENERIC (
@@ -72,4 +73,10 @@ BEGIN
u0 : ip_arria10_e3sge3_remote_update
PORT MAP (clock, data_in, param, read_param, reconfig, reset, reset_timer, write_param, busy, data_out);
END GENERATE;
+
+ gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
+ u0 : ip_arria10_e1sg_remote_update
+ PORT MAP (clock, data_in, param, read_param, reconfig, reset, reset_timer, write_param, busy, data_out);
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/fpga_temp_sens/hdllib.cfg b/libraries/technology/fpga_temp_sens/hdllib.cfg
index f7a6d5baf1..22f6125780 100644
--- a/libraries/technology/fpga_temp_sens/hdllib.cfg
+++ b/libraries/technology/fpga_temp_sens/hdllib.cfg
@@ -1,11 +1,12 @@
hdl_lib_name = tech_fpga_temp_sens
hdl_library_clause_name = tech_fpga_temp_sens_lib
-hdl_lib_uses_synth = technology common ip_arria10_temp_sense ip_arria10_e3sge3_temp_sense
+hdl_lib_uses_synth = technology common ip_arria10_temp_sense ip_arria10_e3sge3_temp_sense ip_arria10_e1sg_temp_sense
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_arria10_temp_sense ip_arria10_temp_sense_altera_temp_sense_150
ip_arria10_e3sge3_temp_sense ip_arria10_e3sge3_temp_sense_altera_temp_sense_151
+ ip_arria10_e1sg_temp_sense ip_arria10_e1sg_temp_sense_altera_temp_sense_151
synth_files =
tech_fpga_temp_sens_component_pkg.vhd
diff --git a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
index 1b69fc737e..ea06ed0820 100644
--- a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
+++ b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
@@ -29,6 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_temp_sense_altera_temp_sense_150;
LIBRARY ip_arria10_e3sge3_temp_sense_altera_temp_sense_151;
+LIBRARY ip_arria10_e1sg_temp_sense_altera_temp_sense_151;
ENTITY tech_fpga_temp_sens IS
@@ -67,4 +68,14 @@ BEGIN
);
END GENERATE;
+ gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
+ u0 : ip_arria10_e1sg_temp_sense
+ PORT MAP (
+ corectl => corectl, -- corectl.corectl
+ reset => reset, -- reset.reset
+ tempout => tempout, -- tempout.tempout
+ eoc => eoc -- eoc.eoc
+ );
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd
index 8c9c255c0f..9fa8feb814 100644
--- a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd
+++ b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd
@@ -44,5 +44,14 @@ PACKAGE tech_fpga_temp_sens_component_pkg IS
);
END COMPONENT;
+ COMPONENT ip_arria10_e1sg_temp_sense IS
+ PORT (
+ corectl : IN STD_LOGIC := '0'; -- corectl.corectl
+ eoc : OUT STD_LOGIC; -- eoc.eoc
+ reset : IN STD_LOGIC := '0'; -- reset.reset
+ tempout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) -- tempout.tempout
+ );
+ END COMPONENT;
+
END tech_fpga_temp_sens_component_pkg;
diff --git a/libraries/technology/fpga_voltage_sens/hdllib.cfg b/libraries/technology/fpga_voltage_sens/hdllib.cfg
index 15065eb71f..46c474c6d3 100644
--- a/libraries/technology/fpga_voltage_sens/hdllib.cfg
+++ b/libraries/technology/fpga_voltage_sens/hdllib.cfg
@@ -1,11 +1,12 @@
hdl_lib_name = tech_fpga_voltage_sens
hdl_library_clause_name = tech_fpga_voltage_sens_lib
-hdl_lib_uses_synth = technology common ip_arria10_voltage_sense ip_arria10_e3sge3_voltage_sense
+hdl_lib_uses_synth = technology common ip_arria10_voltage_sense ip_arria10_e3sge3_voltage_sense ip_arria10_e1sg_voltage_sense
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_arria10_voltage_sense ip_arria10_voltage_sense_altera_voltage_sense_150
ip_arria10_e3sge3_voltage_sense ip_arria10_e3sge3_voltage_sense_altera_voltage_sense_151
+ ip_arria10_e1sg_voltage_sense ip_arria10_e1sg_voltage_sense_altera_voltage_sense_151
synth_files =
tech_fpga_voltage_sens_component_pkg.vhd
diff --git a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
index f9111d1c90..8ddaaff0b2 100644
--- a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
+++ b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
@@ -28,6 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_voltage_sense_altera_voltage_sense_150;
LIBRARY ip_arria10_e3sge3_voltage_sense_altera_voltage_sense_151;
+LIBRARY ip_arria10_e1sg_voltage_sense_altera_voltage_sense_151;
ENTITY tech_fpga_voltage_sens IS
@@ -93,4 +94,23 @@ BEGIN
);
END GENERATE;
+ gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
+ u0 : ip_arria10_e1sg_voltage_sense
+ PORT MAP (
+ clock_clk => clock_clk,
+ reset_sink_reset => reset_sink_reset,
+ controller_csr_address => controller_csr_address,
+ controller_csr_read => controller_csr_read,
+ controller_csr_write => controller_csr_write,
+ controller_csr_writedata => controller_csr_writedata,
+ controller_csr_readdata => controller_csr_readdata,
+ sample_store_csr_address => sample_store_csr_address,
+ sample_store_csr_read => sample_store_csr_read,
+ sample_store_csr_write => sample_store_csr_write,
+ sample_store_csr_writedata => sample_store_csr_writedata,
+ sample_store_csr_readdata => sample_store_csr_readdata,
+ sample_store_irq_irq => sample_store_irq_irq
+ );
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd
index 9780d0870b..586f694dca 100644
--- a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd
+++ b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd
@@ -62,5 +62,23 @@ PACKAGE tech_fpga_voltage_sens_component_pkg IS
);
END COMPONENT;
+ COMPONENT ip_arria10_e1sg_voltage_sense IS
+ PORT (
+ clock_clk : in STD_LOGIC := '0';
+ reset_sink_reset : in STD_LOGIC;
+ controller_csr_address : in STD_LOGIC := '0';
+ controller_csr_read : in STD_LOGIC := '0';
+ controller_csr_write : in STD_LOGIC := '0';
+ controller_csr_writedata : in STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
+ controller_csr_readdata : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
+ sample_store_csr_address : in STD_LOGIC_VECTOR(3 downto 0) := "0000";
+ sample_store_csr_read : in STD_LOGIC := '0';
+ sample_store_csr_write : in STD_LOGIC := '0';
+ sample_store_csr_writedata : in STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
+ sample_store_csr_readdata : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
+ sample_store_irq_irq : out STD_LOGIC
+ );
+ END COMPONENT;
+
END tech_fpga_voltage_sens_component_pkg;
diff --git a/libraries/technology/fractional_pll/hdllib.cfg b/libraries/technology/fractional_pll/hdllib.cfg
index 3a19fc5d6d..aa107e1a63 100644
--- a/libraries/technology/fractional_pll/hdllib.cfg
+++ b/libraries/technology/fractional_pll/hdllib.cfg
@@ -1,8 +1,8 @@
hdl_lib_name = tech_fractional_pll
hdl_library_clause_name = tech_fractional_pll_lib
hdl_lib_uses_synth = technology common
-hdl_lib_uses_ip = ip_arria10_fractional_pll_clk200 ip_arria10_e3sge3_fractional_pll_clk200
- ip_arria10_fractional_pll_clk125 ip_arria10_e3sge3_fractional_pll_clk125
+hdl_lib_uses_ip = ip_arria10_fractional_pll_clk200 ip_arria10_e3sge3_fractional_pll_clk200 ip_arria10_e1sg_fractional_pll_clk200
+ ip_arria10_fractional_pll_clk125 ip_arria10_e3sge3_fractional_pll_clk125 ip_arria10_e1sg_fractional_pll_clk125
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
@@ -10,6 +10,8 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_fractional_pll_clk125 ip_arria10_fractional_pll_clk125_altera_xcvr_fpll_a10_150
ip_arria10_e3sge3_fractional_pll_clk200 ip_arria10_e3sge3_fractional_pll_clk200_altera_xcvr_fpll_a10_151
ip_arria10_e3sge3_fractional_pll_clk125 ip_arria10_e3sge3_fractional_pll_clk125_altera_xcvr_fpll_a10_151
+ ip_arria10_e1sg_fractional_pll_clk200 ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_151
+ ip_arria10_e1sg_fractional_pll_clk125 ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_151
synth_files =
tech_fractional_pll_component_pkg.vhd
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
index 00836d4503..db1911d583 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
@@ -28,6 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_fractional_pll_clk125_altera_xcvr_fpll_a10_150;
LIBRARY ip_arria10_e3sge3_fractional_pll_clk125_altera_xcvr_fpll_a10_151;
+LIBRARY ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_151;
ENTITY tech_fractional_pll_clk125 IS
GENERIC (
@@ -76,4 +77,18 @@ BEGIN
);
END GENERATE;
+ gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
+ u0 : ip_arria10_e1sg_fractional_pll_clk125
+ PORT MAP (
+ outclk0 => c0, -- outclk0.clk
+ outclk1 => c1, -- outclk1.clk
+ outclk2 => c2, -- outclk2.clk
+ outclk3 => c3, -- outclk3.clk
+ pll_cal_busy => OPEN, -- pll_cal_busy.pll_cal_busy
+ pll_locked => locked, -- pll_locked.pll_locked
+ pll_powerdown => areset, -- pll_powerdown.pll_powerdown
+ pll_refclk0 => inclk0 -- pll_refclk0.clk
+ );
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
index 9b138ac7d1..5114716224 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
@@ -28,6 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_fractional_pll_clk200_altera_xcvr_fpll_a10_150;
LIBRARY ip_arria10_e3sge3_fractional_pll_clk200_altera_xcvr_fpll_a10_151;
+LIBRARY ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_151;
ENTITY tech_fractional_pll_clk200 IS
GENERIC (
@@ -73,5 +74,18 @@ BEGIN
);
END GENERATE;
+ gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
+ u0 : ip_arria10_e1sg_fractional_pll_clk200
+ PORT MAP (
+ outclk0 => c0, -- outclk0.clk
+ outclk1 => c1, -- outclk1.clk
+ outclk2 => c2, -- outclk2.clk
+ pll_cal_busy => OPEN, -- pll_cal_busy.pll_cal_busy
+ pll_locked => locked, -- pll_locked.pll_locked
+ pll_powerdown => areset, -- pll_powerdown.pll_powerdown
+ pll_refclk0 => inclk0 -- pll_refclk0.clk
+ );
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd
index 8b0db6b937..d1b5292366 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd
@@ -88,5 +88,36 @@ PACKAGE tech_fractional_pll_component_pkg IS
);
END COMPONENT;
+ -----------------------------------------------------------------------------
+ -- ip_arria10_e1sg
+ -----------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_e1sg_fractional_pll_clk200 IS
+ PORT
+ (
+ outclk0 : out std_logic; -- outclk0.clk
+ outclk1 : out std_logic; -- outclk1.clk
+ outclk2 : out std_logic; -- outclk2.clk
+ pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
+ pll_locked : out std_logic; -- pll_locked.pll_locked
+ pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
+ pll_refclk0 : in std_logic := '0' -- pll_refclk0.clk
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e1sg_fractional_pll_clk125 IS
+ PORT
+ (
+ outclk0 : out std_logic; -- outclk0.clk
+ outclk1 : out std_logic; -- outclk1.clk
+ outclk2 : out std_logic; -- outclk2.clk
+ outclk3 : out std_logic; -- outclk2.clk
+ pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
+ pll_locked : out std_logic; -- pll_locked.pll_locked
+ pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
+ pll_refclk0 : in std_logic := '0' -- pll_refclk0.clk
+ );
+ END COMPONENT;
+
END tech_fractional_pll_component_pkg;
diff --git a/libraries/technology/iobuf/hdllib.cfg b/libraries/technology/iobuf/hdllib.cfg
index 382e5f2766..c6b41564de 100644
--- a/libraries/technology/iobuf/hdllib.cfg
+++ b/libraries/technology/iobuf/hdllib.cfg
@@ -1,12 +1,13 @@
hdl_lib_name = tech_iobuf
hdl_library_clause_name = tech_iobuf_lib
-hdl_lib_uses_synth = technology ip_stratixiv_ddio ip_arria10_ddio ip_arria10_e3sge3_ddio
+hdl_lib_uses_synth = technology ip_stratixiv_ddio ip_arria10_ddio ip_arria10_e3sge3_ddio ip_arria10_e1sg_ddio
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_stratixiv_ddio ip_stratixiv_ddio_lib
ip_arria10_ddio ip_arria10_ddio_lib
ip_arria10_e3sge3_ddio ip_arria10_e3sge3_ddio_lib
+ ip_arria10_e1sg_ddio ip_arria10_e1sg_ddio_lib
synth_files =
tech_iobuf_component_pkg.vhd
diff --git a/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd b/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd
index 2d66aebd7d..115d9789fd 100644
--- a/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd
+++ b/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd
@@ -125,4 +125,36 @@ PACKAGE tech_iobuf_component_pkg IS
);
END COMPONENT;
+ -----------------------------------------------------------------------------
+ -- ip_arria10_e1sg
+ -----------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_e1sg_ddio_in IS
+ GENERIC (
+ g_width : NATURAL := 1
+ );
+ PORT (
+ in_dat : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ in_clk : IN STD_LOGIC;
+ in_clk_en : IN STD_LOGIC := '1'; -- Not Connected
+ rst : IN STD_LOGIC := '0';
+ out_dat_hi : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ out_dat_lo : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e1sg_ddio_out IS
+ GENERIC(
+ g_width : NATURAL := 1
+ );
+ PORT (
+ rst : IN STD_LOGIC := '0';
+ in_clk : IN STD_LOGIC;
+ in_clk_en : IN STD_LOGIC := '1'; -- Not Connected
+ in_dat_hi : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ in_dat_lo : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ out_dat : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
END tech_iobuf_component_pkg;
diff --git a/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd b/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd
index 97531852b5..92e49a5c0b 100644
--- a/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd
+++ b/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd
@@ -29,6 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_ddio_lib;
LIBRARY ip_arria10_ddio_lib;
LIBRARY ip_arria10_e3sge3_ddio_lib;
+LIBRARY ip_arria10_e1sg_ddio_lib;
ENTITY tech_iobuf_ddio_in IS
GENERIC (
@@ -62,10 +63,16 @@ BEGIN
PORT MAP (in_dat, in_clk, in_clk_en, rst, out_dat_hi, out_dat_lo);
END GENERATE;
+ gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
+ u0 : ip_arria10_e1sg_ddio_in
+ GENERIC MAP (g_width)
+ PORT MAP (in_dat, in_clk, in_clk_en, rst, out_dat_hi, out_dat_lo);
+ END GENERATE;
+
gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
u0 : ip_arria10_e3sge3_ddio_in
GENERIC MAP (g_width)
PORT MAP (in_dat, in_clk, in_clk_en, rst, out_dat_hi, out_dat_lo);
END GENERATE;
-
+
END ARCHITECTURE;
diff --git a/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd b/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd
index b8f7773440..2c4fe9e581 100644
--- a/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd
+++ b/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd
@@ -29,6 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_ddio_lib;
LIBRARY ip_arria10_ddio_lib;
LIBRARY ip_arria10_e3sge3_ddio_lib;
+LIBRARY ip_arria10_e1sg_ddio_lib;
ENTITY tech_iobuf_ddio_out IS
GENERIC (
@@ -68,4 +69,10 @@ BEGIN
PORT MAP (rst, in_clk, in_clk_en, in_dat_hi, in_dat_lo, out_dat);
END GENERATE;
+ gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
+ u0 : ip_arria10_e1sg_ddio_out
+ GENERIC MAP (g_width)
+ PORT MAP (rst, in_clk, in_clk_en, in_dat_hi, in_dat_lo, out_dat);
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/mac_10g/hdllib.cfg b/libraries/technology/mac_10g/hdllib.cfg
index a2332f7b0a..c81aa3c753 100644
--- a/libraries/technology/mac_10g/hdllib.cfg
+++ b/libraries/technology/mac_10g/hdllib.cfg
@@ -1,19 +1,21 @@
hdl_lib_name = tech_mac_10g
hdl_library_clause_name = tech_mac_10g_lib
hdl_lib_uses_synth = technology common dp ip_stratixiv_mac_10g
-hdl_lib_uses_ip = ip_arria10_mac_10g ip_arria10_e3sge3_mac_10g
+hdl_lib_uses_ip = ip_arria10_mac_10g ip_arria10_e3sge3_mac_10g ip_arria10_e1sg_mac_10g
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_stratixiv_mac_10g ip_stratixiv_mac_10g_lib
ip_arria10_mac_10g ip_arria10_mac_10g_alt_em10g32_150
ip_arria10_e3sge3_mac_10g ip_arria10_e3sge3_mac_10g_alt_em10g32_151
+ ip_arria10_e1sg_mac_10g ip_arria10_e1sg_mac_10g_alt_em10g32_151
synth_files =
tech_mac_10g_component_pkg.vhd
tech_mac_10g_stratixiv.vhd
tech_mac_10g_arria10.vhd
tech_mac_10g_arria10_e3sge3.vhd
+ tech_mac_10g_arria10_e1sg.vhd
tech_mac_10g.vhd
test_bench_files =
diff --git a/libraries/technology/mac_10g/tech_mac_10g.vhd b/libraries/technology/mac_10g/tech_mac_10g.vhd
index 111449b150..5937011b3a 100644
--- a/libraries/technology/mac_10g/tech_mac_10g.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g.vhd
@@ -118,8 +118,8 @@ END tech_mac_10g;
ARCHITECTURE str OF tech_mac_10g IS
-- Adapt ST ready latency 1 to IP ready latency
- CONSTANT c_ip_tx_ready_latency : NATURAL := sel_a_b(g_technology=c_tech_stratixiv OR g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3, 0, 1);
- CONSTANT c_ip_rx_ready_latency : NATURAL := sel_a_b(g_technology=c_tech_stratixiv OR g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3, 0, 1);
+ CONSTANT c_ip_tx_ready_latency : NATURAL := sel_a_b(g_technology=c_tech_stratixiv OR g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg, 0, 1);
+ CONSTANT c_ip_rx_ready_latency : NATURAL := sel_a_b(g_technology=c_tech_stratixiv OR g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg, 0, 1);
SIGNAL tx_mac_snk_in_data : STD_LOGIC_VECTOR(c_tech_mac_10g_data_w-1 DOWNTO 0); -- 64 bit
SIGNAL tx_mac_snk_in : t_dp_sosi;
@@ -169,6 +169,14 @@ BEGIN
xgmii_link_status, xgmii_tx_data, xgmii_rx_data);
END GENERATE;
+ gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
+ u0 : ENTITY work.tech_mac_10g_arria10_e1sg
+ PORT MAP (mm_clk, mm_rst, csr_mosi, csr_miso,
+ tx_clk_312, tx_clk_156, tx_rst, tx_mac_snk_in, tx_mac_snk_out,
+ rx_clk_312, rx_clk_156, rx_rst, rx_mac_src_out, rx_mac_src_in,
+ xgmii_link_status, xgmii_tx_data, xgmii_rx_data);
+ END GENERATE;
+
-----------------------------------------------------------------------------
-- Debug signals to ease monitoring in wave window
-----------------------------------------------------------------------------
diff --git a/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd b/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd
new file mode 100644
index 0000000000..e01af57e01
--- /dev/null
+++ b/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd
@@ -0,0 +1,145 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
+LIBRARY ip_arria10_e1sg_mac_10g_alt_em10g32_151;
+
+LIBRARY IEEE, technology_lib, common_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_interface_layers_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE work.tech_mac_10g_component_pkg.ALL;
+
+ENTITY tech_mac_10g_arria10_e1sg IS
+ PORT (
+ -- MM
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+ csr_mosi : IN t_mem_mosi; -- CSR = control status register
+ csr_miso : OUT t_mem_miso;
+
+ -- ST
+ tx_clk_312 : IN STD_LOGIC;
+ tx_clk_156 : IN STD_LOGIC;
+ tx_rst : IN STD_LOGIC;
+ tx_snk_in : IN t_dp_sosi;
+ tx_snk_out : OUT t_dp_siso;
+
+ rx_clk_312 : IN STD_LOGIC;
+ rx_clk_156 : IN STD_LOGIC;
+ rx_rst : IN STD_LOGIC;
+ rx_src_out : OUT t_dp_sosi;
+ rx_src_in : IN t_dp_siso;
+
+ -- XGMII
+ xgmii_link_status : OUT STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0); -- 2 bit
+ xgmii_tx_data : OUT STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0); -- 72 bit
+ xgmii_rx_data : IN STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0) -- 72 bit
+ );
+END tech_mac_10g_arria10_e1sg;
+
+
+ARCHITECTURE str OF tech_mac_10g_arria10_e1sg IS
+
+ CONSTANT c_mac_10g_csr_addr_w : NATURAL := func_tech_mac_10g_csr_addr_w(c_tech_arria10); -- = 13
+
+ SIGNAL mm_rst_n : STD_LOGIC;
+ SIGNAL tx_rst_n : STD_LOGIC;
+ SIGNAL rx_rst_n : STD_LOGIC;
+
+ SIGNAL avalon_rx_src_out : t_dp_sosi := c_dp_sosi_rst;
+
+BEGIN
+
+ mm_rst_n <= NOT mm_rst;
+ tx_rst_n <= NOT tx_rst;
+ rx_rst_n <= NOT rx_rst;
+
+ -- Default frame level flow control
+ tx_snk_out.xon <= '1';
+
+ -- Force rx_src_out.sop = 0 when rx_src_out.valid = '0'
+ p_rx_src_out : PROCESS(avalon_rx_src_out)
+ BEGIN
+ rx_src_out <= avalon_rx_src_out;
+ rx_src_out.sop <= avalon_rx_src_out.sop AND avalon_rx_src_out.valid;
+ END PROCESS;
+
+ u_ip_arria10_e1sg_mac_10g : ip_arria10_e1sg_mac_10g
+ PORT MAP (
+ csr_clk => mm_clk,
+ csr_rst_n => mm_rst_n,
+
+ csr_address => csr_mosi.address(c_mac_10g_csr_addr_w-1 DOWNTO 0), -- 13 bit
+ csr_read => csr_mosi.rd,
+ csr_write => csr_mosi.wr,
+ csr_writedata => csr_mosi.wrdata(c_word_w-1 DOWNTO 0), -- 32 bit
+ csr_readdata => csr_miso.rddata(c_word_w-1 DOWNTO 0), -- 32 bit
+ csr_waitrequest => csr_miso.waitrequest,
+
+ tx_312_5_clk => tx_clk_312,
+ tx_156_25_clk => tx_clk_156,
+ tx_rst_n => tx_rst_n,
+
+ avalon_st_tx_ready => tx_snk_out.ready,
+ avalon_st_tx_startofpacket => tx_snk_in.sop,
+ avalon_st_tx_endofpacket => tx_snk_in.eop,
+ avalon_st_tx_valid => tx_snk_in.valid,
+ avalon_st_tx_data => tx_snk_in.data(c_xgmii_data_w-1 DOWNTO 0), -- 64 bit
+ avalon_st_tx_empty => tx_snk_in.empty(c_tech_mac_10g_empty_w-1 DOWNTO 0), -- 3 bit
+ avalon_st_tx_error => tx_snk_in.err(0), -- 1 bit std_logic = c_tech_mac_10g_tx_error_w
+ avalon_st_pause_data => (OTHERS=>'0'),
+
+ xgmii_tx => xgmii_tx_data, -- 72 bit
+
+ avalon_st_txstatus_valid => OPEN,
+ avalon_st_txstatus_data => OPEN,
+ avalon_st_txstatus_error => OPEN,
+
+ rx_312_5_clk => rx_clk_312,
+ rx_156_25_clk => rx_clk_156,
+ rx_rst_n => rx_rst_n,
+
+ xgmii_rx => xgmii_rx_data, -- 72 bit
+
+ avalon_st_rx_ready => rx_src_in.ready,
+ avalon_st_rx_startofpacket => avalon_rx_src_out.sop,
+ avalon_st_rx_endofpacket => avalon_rx_src_out.eop,
+ avalon_st_rx_valid => avalon_rx_src_out.valid,
+ avalon_st_rx_data => avalon_rx_src_out.data(c_xgmii_data_w-1 DOWNTO 0), -- 64 bit
+ avalon_st_rx_empty => avalon_rx_src_out.empty(c_tech_mac_10g_empty_w-1 DOWNTO 0), -- 3 bit
+ avalon_st_rx_error => avalon_rx_src_out.err(c_tech_mac_10g_rx_error_w-1 DOWNTO 0), -- 6 bit
+
+ avalon_st_rxstatus_valid => OPEN,
+ avalon_st_rxstatus_data => OPEN,
+ avalon_st_rxstatus_error => OPEN,
+
+ link_fault_status_xgmii_rx_data => xgmii_link_status, -- 0=ok, 1=local fault, 2=remote fault
+
+ unidirectional_en => OPEN,
+ unidirectional_remote_fault_dis => OPEN
+ );
+
+END str;
diff --git a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
index fdb1723ecd..089a409ec2 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
@@ -193,6 +193,55 @@ PACKAGE tech_mac_10g_component_pkg IS
);
END COMPONENT;
+ ------------------------------------------------------------------------------
+ -- ip_arria10_e1sg
+ ------------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_e1sg_mac_10g IS
+ PORT (
+ csr_read : in std_logic := '0'; -- csr.read
+ csr_write : in std_logic := '0'; -- .write
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ csr_readdata : out std_logic_vector(31 downto 0); -- .readdata
+ csr_waitrequest : out std_logic; -- .waitrequest
+ csr_address : in std_logic_vector(12 downto 0) := (others => '0'); -- .address
+ tx_312_5_clk : in std_logic := '0'; -- tx_312_5_clk.clk
+ tx_156_25_clk : in std_logic := '0'; -- tx_156_25_clk.clk
+ rx_312_5_clk : in std_logic := '0'; -- rx_312_5_clk.clk
+ rx_156_25_clk : in std_logic := '0'; -- rx_156_25_clk.clk
+ csr_clk : in std_logic := '0'; -- csr_clk.clk
+ csr_rst_n : in std_logic := '0'; -- csr_rst_n.reset_n
+ tx_rst_n : in std_logic := '0'; -- tx_rst_n.reset_n
+ rx_rst_n : in std_logic := '0'; -- rx_rst_n.reset_n
+ avalon_st_tx_startofpacket : in std_logic := '0'; -- avalon_st_tx.startofpacket
+ avalon_st_tx_endofpacket : in std_logic := '0'; -- .endofpacket
+ avalon_st_tx_valid : in std_logic := '0'; -- .valid
+ avalon_st_tx_data : in std_logic_vector(63 downto 0) := (others => '0'); -- .data
+ avalon_st_tx_empty : in std_logic_vector(2 downto 0) := (others => '0'); -- .empty
+ avalon_st_tx_error : in std_logic := '0'; -- .error
+ avalon_st_tx_ready : out std_logic; -- .ready
+ avalon_st_pause_data : in std_logic_vector(1 downto 0) := (others => '0'); -- avalon_st_pause.data
+ xgmii_tx : out std_logic_vector(71 downto 0); -- xgmii_tx.data
+ avalon_st_txstatus_valid : out std_logic; -- avalon_st_txstatus.valid
+ avalon_st_txstatus_data : out std_logic_vector(39 downto 0); -- .data
+ avalon_st_txstatus_error : out std_logic_vector(6 downto 0); -- .error
+ xgmii_rx : in std_logic_vector(71 downto 0) := (others => '0'); -- xgmii_rx.data
+ link_fault_status_xgmii_rx_data : out std_logic_vector(1 downto 0); -- link_fault_status_xgmii_rx.data
+ avalon_st_rx_data : out std_logic_vector(63 downto 0); -- avalon_st_rx.data
+ avalon_st_rx_startofpacket : out std_logic; -- .startofpacket
+ avalon_st_rx_valid : out std_logic; -- .valid
+ avalon_st_rx_empty : out std_logic_vector(2 downto 0); -- .empty
+ avalon_st_rx_error : out std_logic_vector(5 downto 0); -- .error
+ avalon_st_rx_ready : in std_logic := '0'; -- .ready
+ avalon_st_rx_endofpacket : out std_logic; -- .endofpacket
+ avalon_st_rxstatus_valid : out std_logic; -- avalon_st_rxstatus.valid
+ avalon_st_rxstatus_data : out std_logic_vector(39 downto 0); -- .data
+ avalon_st_rxstatus_error : out std_logic_vector(6 downto 0); -- .error
+ unidirectional_en : out std_logic; -- unidirectional.en
+ unidirectional_remote_fault_dis : out std_logic -- .remote_fault_dis
+ );
+ END COMPONENT;
+
END tech_mac_10g_component_pkg;
PACKAGE BODY tech_mac_10g_component_pkg IS
@@ -204,6 +253,7 @@ PACKAGE BODY tech_mac_10g_component_pkg IS
WHEN c_tech_stratixiv => v_csr_addr_w := 13;
WHEN c_tech_arria10 => v_csr_addr_w := 13; -- 13 with INSERT_CSR_ADAPTOR=1 in ip_arria10_mac_10g.qsys, 10 without
WHEN c_tech_arria10_e3sge3 => v_csr_addr_w := 13; -- 13 with INSERT_CSR_ADAPTOR=1 in ip_arria10_e3sge3_mac_10g.qsys, 10 without
+ WHEN c_tech_arria10_e1sg => v_csr_addr_w := 13; -- 13 with INSERT_CSR_ADAPTOR=1 in ip_arria10_e1sg_mac_10g.qsys, 10 without
WHEN OTHERS => v_csr_addr_w := 13; -- default to c_tech_stratixiv
END CASE;
RETURN v_csr_addr_w;
diff --git a/libraries/technology/memory/hdllib.cfg b/libraries/technology/memory/hdllib.cfg
index 1415618394..a2d022fb94 100644
--- a/libraries/technology/memory/hdllib.cfg
+++ b/libraries/technology/memory/hdllib.cfg
@@ -1,12 +1,13 @@
hdl_lib_name = tech_memory
hdl_library_clause_name = tech_memory_lib
-hdl_lib_uses_synth = technology ip_stratixiv_ram ip_arria10_ram ip_arria10_e3sge3_ram
+hdl_lib_uses_synth = technology ip_stratixiv_ram ip_arria10_ram ip_arria10_e3sge3_ram ip_arria10_e1sg_ram
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_stratixiv_ram ip_stratixiv_ram_lib
ip_arria10_ram ip_arria10_ram_lib
ip_arria10_e3sge3_ram ip_arria10_e3sge3_ram_lib
+ ip_arria10_e1sg_ram ip_arria10_e1sg_ram_lib
synth_files =
tech_memory_component_pkg.vhd
diff --git a/libraries/technology/memory/tech_memory_component_pkg.vhd b/libraries/technology/memory/tech_memory_component_pkg.vhd
index c256264184..c3baad4906 100644
--- a/libraries/technology/memory/tech_memory_component_pkg.vhd
+++ b/libraries/technology/memory/tech_memory_component_pkg.vhd
@@ -328,4 +328,98 @@ PACKAGE tech_memory_component_pkg IS
);
END COMPONENT;
+ -----------------------------------------------------------------------------
+ -- ip_arria10_e1sg
+ -----------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_e1sg_ram_crwk_crw IS
+ GENERIC (
+ g_adr_a_w : NATURAL := 5;
+ g_dat_a_w : NATURAL := 32;
+ g_adr_b_w : NATURAL := 4;
+ g_dat_b_w : NATURAL := 64;
+ g_nof_words_a : NATURAL := 2**5;
+ g_nof_words_b : NATURAL := 2**4;
+ g_rd_latency : NATURAL := 1; -- choose 1 or 2
+ g_init_file : STRING := "UNUSED"
+ );
+ PORT
+ (
+ address_a : IN STD_LOGIC_VECTOR (g_adr_a_w-1 DOWNTO 0);
+ address_b : IN STD_LOGIC_VECTOR (g_adr_b_w-1 DOWNTO 0);
+ clk_a : IN STD_LOGIC := '1';
+ clk_b : IN STD_LOGIC ;
+ data_a : IN STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
+ data_b : IN STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0);
+ wren_a : IN STD_LOGIC := '0';
+ wren_b : IN STD_LOGIC := '0';
+ q_a : OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
+ q_b : OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e1sg_ram_crw_crw IS
+ GENERIC (
+ g_inferred : BOOLEAN := FALSE;
+ g_adr_w : NATURAL := 5;
+ g_dat_w : NATURAL := 8;
+ g_nof_words : NATURAL := 2**5;
+ g_rd_latency : NATURAL := 1; -- choose 1 or 2
+ g_init_file : STRING := "UNUSED"
+ );
+ PORT
+ (
+ address_a : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+ address_b : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+ clk_a : IN STD_LOGIC := '1';
+ clk_b : IN STD_LOGIC ;
+ data_a : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ data_b : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ wren_a : IN STD_LOGIC := '0';
+ wren_b : IN STD_LOGIC := '0';
+ q_a : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ q_b : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e1sg_ram_cr_cw IS
+ GENERIC (
+ g_inferred : BOOLEAN := FALSE;
+ g_adr_w : NATURAL := 5;
+ g_dat_w : NATURAL := 8;
+ g_nof_words : NATURAL := 2**5;
+ g_rd_latency : NATURAL := 1; -- choose 1 or 2
+ g_init_file : STRING := "UNUSED"
+ );
+ PORT
+ (
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdaddress : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ wraddress : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+ wrclk : IN STD_LOGIC := '1';
+ wren : IN STD_LOGIC := '0';
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e1sg_ram_r_w IS
+ GENERIC (
+ g_inferred : BOOLEAN := FALSE;
+ g_adr_w : NATURAL := 5;
+ g_dat_w : NATURAL := 8;
+ g_nof_words : NATURAL := 2**5;
+ g_rd_latency : NATURAL := 1; -- choose 1 or 2
+ g_init_file : STRING := "UNUSED"
+ );
+ PORT (
+ clk : IN STD_LOGIC := '1';
+ data : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := (OTHERS=>'0');
+ rdaddress : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
+ wraddress : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
+ wren : IN STD_LOGIC := '0';
+ q : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
END tech_memory_component_pkg;
diff --git a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
index b29ac59a5f..412209602c 100644
--- a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
@@ -29,6 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_ram_lib;
LIBRARY ip_arria10_ram_lib;
LIBRARY ip_arria10_e3sge3_ram_lib;
+LIBRARY ip_arria10_e1sg_ram_lib;
ENTITY tech_memory_ram_cr_cw IS
GENERIC (
@@ -74,4 +75,10 @@ BEGIN
PORT MAP (data, rdaddress, rdclock, wraddress, wrclock, wren, q);
END GENERATE;
+ gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
+ u0 : ip_arria10_e1sg_ram_cr_cw
+ GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+ PORT MAP (data, rdaddress, rdclock, wraddress, wrclock, wren, q);
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
index 097ccb3289..501da0de25 100644
--- a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
@@ -29,6 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_ram_lib;
LIBRARY ip_arria10_ram_lib;
LIBRARY ip_arria10_e3sge3_ram_lib;
+LIBRARY ip_arria10_e1sg_ram_lib;
ENTITY tech_memory_ram_crw_crw IS
GENERIC (
@@ -81,4 +82,10 @@ BEGIN
PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
END GENERATE;
+ gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
+ u0 : ip_arria10_e1sg_ram_crw_crw
+ GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+ PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
index 33cff6d845..78b4e5c68c 100644
--- a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
@@ -29,6 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_ram_lib;
LIBRARY ip_arria10_ram_lib;
LIBRARY ip_arria10_e3sge3_ram_lib;
+LIBRARY ip_arria10_e1sg_ram_lib;
ENTITY tech_memory_ram_crwk_crw IS -- support different port data widths and corresponding address ranges
GENERIC (
@@ -83,4 +84,10 @@ BEGIN
PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
END GENERATE;
+ gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
+ u0 : ip_arria10_e1sg_ram_crwk_crw
+ GENERIC MAP (g_adr_a_w, g_dat_a_w, g_adr_b_w, g_dat_b_w, g_nof_words_a, g_nof_words_b, g_rd_latency, g_init_file)
+ PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/memory/tech_memory_ram_r_w.vhd b/libraries/technology/memory/tech_memory_ram_r_w.vhd
index 088235bcba..ca9222873d 100644
--- a/libraries/technology/memory/tech_memory_ram_r_w.vhd
+++ b/libraries/technology/memory/tech_memory_ram_r_w.vhd
@@ -29,6 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_ram_lib;
LIBRARY ip_arria10_ram_lib;
LIBRARY ip_arria10_e3sge3_ram_lib;
+LIBRARY ip_arria10_e1sg_ram_lib;
ENTITY tech_memory_ram_r_w IS
GENERIC (
@@ -71,4 +72,10 @@ BEGIN
PORT MAP (clock, data, rdaddress, wraddress, wren, q);
END GENERATE;
+ gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
+ u0 : ip_arria10_e1sg_ram_r_w
+ GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, 1, g_init_file)
+ PORT MAP (clock, data, rdaddress, wraddress, wren, q);
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/memory/tech_memory_rom_r.vhd b/libraries/technology/memory/tech_memory_rom_r.vhd
index 4a9d4ffc5d..9f961d977b 100644
--- a/libraries/technology/memory/tech_memory_rom_r.vhd
+++ b/libraries/technology/memory/tech_memory_rom_r.vhd
@@ -29,6 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_ram_lib;
LIBRARY ip_arria10_ram_lib;
LIBRARY ip_arria10_e3sge3_ram_lib;
+LIBRARY ip_arria10_e1sg_ram_lib;
ENTITY tech_memory_rom_r IS
GENERIC (
@@ -83,4 +84,18 @@ BEGIN
);
END GENERATE;
+ gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
+ -- use ip_arria10_e1sg_ram_r_w as ROM
+ u0 : ip_arria10_e1sg_ram_r_w
+ GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, 1, g_init_file)
+ PORT MAP (
+ clk => clock,
+ --data => ,
+ rdaddress => address,
+ --wraddress => ,
+ --wren => ,
+ q => q
+ );
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/mult/hdllib.cfg b/libraries/technology/mult/hdllib.cfg
index 486aaca04b..ed74842532 100644
--- a/libraries/technology/mult/hdllib.cfg
+++ b/libraries/technology/mult/hdllib.cfg
@@ -6,6 +6,7 @@ hdl_lib_uses_synth = common technology
ip_arria10_complex_mult
ip_arria10_complex_mult_rtl
ip_arria10_e3sge3_mult_add4
+ ip_arria10_e1sg_mult_add4
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
@@ -14,6 +15,7 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_complex_mult ip_arria10_complex_mult_altmult_complex_150
ip_arria10_complex_mult_rtl ip_arria10_complex_mult_rtl_lib
ip_arria10_e3sge3_mult_add4 ip_arria10_e3sge3_mult_add4_lib
+ ip_arria10_e1sg_mult_add4 ip_arria10_e1sg_mult_add4_lib
synth_files =
tech_mult_component_pkg.vhd
diff --git a/libraries/technology/mult/tech_mult_add4.vhd b/libraries/technology/mult/tech_mult_add4.vhd
index 08879f50bf..434684633b 100644
--- a/libraries/technology/mult/tech_mult_add4.vhd
+++ b/libraries/technology/mult/tech_mult_add4.vhd
@@ -29,6 +29,7 @@ USE work.tech_mult_component_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_mult_lib;
LIBRARY ip_arria10_e3sge3_mult_add4_lib;
+LIBRARY ip_arria10_e1sg_mult_add4_lib;
ENTITY tech_mult_add4 IS
GENERIC (
@@ -113,5 +114,31 @@ begin
);
END GENERATE;
+ gen_ip_arria10_e1sg_rtl : IF (g_technology=c_tech_arria10_e1sg AND g_variant="RTL") GENERATE
+ u0 : ip_arria10_e1sg_mult_add4_rtl
+ GENERIC MAP(
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_res_w => g_res_w,
+ g_force_dsp => g_force_dsp,
+ g_add_sub0 => g_add_sub0,
+ g_add_sub1 => g_add_sub1,
+ g_add_sub => g_add_sub,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ PORT MAP(
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_a => in_a,
+ in_b => in_b,
+ res => res
+ );
+ END GENERATE;
+
end str;
diff --git a/libraries/technology/mult/tech_mult_component_pkg.vhd b/libraries/technology/mult/tech_mult_component_pkg.vhd
index d793c7487b..2aa97f8b26 100644
--- a/libraries/technology/mult/tech_mult_component_pkg.vhd
+++ b/libraries/technology/mult/tech_mult_component_pkg.vhd
@@ -271,4 +271,33 @@ PACKAGE tech_mult_component_pkg IS
);
END COMPONENT;
+ -----------------------------------------------------------------------------
+ -- Arria 10 e1sg components
+ -----------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_e1sg_mult_add4_rtl IS
+ GENERIC (
+ g_in_a_w : POSITIVE;
+ g_in_b_w : POSITIVE;
+ g_res_w : POSITIVE; -- g_in_a_w + g_in_b_w + log2(4)
+ g_force_dsp : BOOLEAN := TRUE; -- when TRUE resize input width to >= 18
+ g_add_sub0 : STRING := "ADD"; -- or "SUB"
+ g_add_sub1 : STRING := "ADD"; -- or "SUB"
+ g_add_sub : STRING := "ADD"; -- or "SUB" only available with rtl architecture
+ g_nof_mult : INTEGER := 4; -- fixed
+ g_pipeline_input : NATURAL := 1; -- 0 or 1
+ g_pipeline_product : NATURAL := 0; -- 0 or 1
+ g_pipeline_adder : NATURAL := 1; -- 0 or 1, first sum
+ g_pipeline_output : NATURAL := 1 -- >= 0, second sum and optional rounding
+ );
+ PORT (
+ rst : IN STD_LOGIC := '0';
+ clk : IN STD_LOGIC;
+ clken : IN STD_LOGIC := '1';
+ in_a : IN STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
+ in_b : IN STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
+ res : OUT STD_LOGIC_VECTOR(g_res_w-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
END tech_mult_component_pkg;
diff --git a/libraries/technology/pll/hdllib.cfg b/libraries/technology/pll/hdllib.cfg
index 464015e19b..7b5ef9392e 100644
--- a/libraries/technology/pll/hdllib.cfg
+++ b/libraries/technology/pll/hdllib.cfg
@@ -1,10 +1,10 @@
hdl_lib_name = tech_pll
hdl_library_clause_name = tech_pll_lib
hdl_lib_uses_synth = technology common
-hdl_lib_uses_ip = ip_stratixiv_pll ip_arria10_pll_clk200 ip_arria10_e3sge3_pll_clk200
- ip_stratixiv_pll_clk25 ip_arria10_pll_clk25 ip_arria10_e3sge3_pll_clk25
- ip_arria10_pll_clk125 ip_arria10_e3sge3_pll_clk125
- ip_arria10_pll_xgmii_mac_clocks ip_arria10_e3sge3_pll_xgmii_mac_clocks
+hdl_lib_uses_ip = ip_stratixiv_pll ip_arria10_pll_clk200 ip_arria10_e3sge3_pll_clk200 ip_arria10_e1sg_pll_clk200
+ ip_stratixiv_pll_clk25 ip_arria10_pll_clk25 ip_arria10_e3sge3_pll_clk25 ip_arria10_e1sg_pll_clk25
+ ip_arria10_pll_clk125 ip_arria10_e3sge3_pll_clk125 ip_arria10_e1sg_pll_clk125
+ ip_arria10_pll_xgmii_mac_clocks ip_arria10_e3sge3_pll_xgmii_mac_clocks ip_arria10_e1sg_pll_xgmii_mac_clocks
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
@@ -18,6 +18,10 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e3sge3_pll_clk25 ip_arria10_e3sge3_pll_clk25_altera_iopll_151
ip_arria10_e3sge3_pll_clk125 ip_arria10_e3sge3_pll_clk125_altera_iopll_151
ip_arria10_e3sge3_pll_xgmii_mac_clocks ip_arria10_e3sge3_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151
+ ip_arria10_e1sg_pll_clk200 ip_arria10_e1sg_pll_clk200_altera_iopll_151
+ ip_arria10_e1sg_pll_clk25 ip_arria10_e1sg_pll_clk25_altera_iopll_151
+ ip_arria10_e1sg_pll_clk125 ip_arria10_e1sg_pll_clk125_altera_iopll_151
+ ip_arria10_e1sg_pll_xgmii_mac_clocks ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151
synth_files =
tech_pll_component_pkg.vhd
diff --git a/libraries/technology/pll/tech_pll_clk125.vhd b/libraries/technology/pll/tech_pll_clk125.vhd
index 0c13ffc207..dc5cd91e9f 100644
--- a/libraries/technology/pll/tech_pll_clk125.vhd
+++ b/libraries/technology/pll/tech_pll_clk125.vhd
@@ -28,6 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_pll_clk125_altera_iopll_150;
LIBRARY ip_arria10_e3sge3_pll_clk125_altera_iopll_151;
+LIBRARY ip_arria10_e1sg_pll_clk125_altera_iopll_151;
ENTITY tech_pll_clk125 IS
GENERIC (
@@ -73,4 +74,18 @@ BEGIN
locked => locked
);
END GENERATE;
+
+ gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
+ u0 : ip_arria10_e1sg_pll_clk125
+ PORT MAP (
+ rst => areset,
+ refclk => inclk0,
+ outclk_0 => c0,
+ outclk_1 => c1,
+ outclk_2 => c2,
+ outclk_3 => c3,
+ locked => locked
+ );
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/pll/tech_pll_clk200.vhd b/libraries/technology/pll/tech_pll_clk200.vhd
index 539bf15f15..2e9f9ed5e7 100644
--- a/libraries/technology/pll/tech_pll_clk200.vhd
+++ b/libraries/technology/pll/tech_pll_clk200.vhd
@@ -29,6 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_pll_lib;
LIBRARY ip_arria10_pll_clk200_altera_iopll_150;
LIBRARY ip_arria10_e3sge3_pll_clk200_altera_iopll_151;
+LIBRARY ip_arria10_e1sg_pll_clk200_altera_iopll_151;
ENTITY tech_pll_clk200 IS
GENERIC (
@@ -81,4 +82,16 @@ BEGIN
);
END GENERATE;
+ gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
+ u0 : ip_arria10_e1sg_pll_clk200
+ PORT MAP (
+ rst => areset,
+ refclk => inclk0,
+ outclk_0 => c0,
+ outclk_1 => c1,
+ outclk_2 => c2,
+ locked => locked
+ );
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/pll/tech_pll_clk25.vhd b/libraries/technology/pll/tech_pll_clk25.vhd
index 13301ec202..e065439d75 100644
--- a/libraries/technology/pll/tech_pll_clk25.vhd
+++ b/libraries/technology/pll/tech_pll_clk25.vhd
@@ -29,6 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_pll_clk25_altera_iopll_150;
LIBRARY ip_stratixiv_pll_clk25_lib;
LIBRARY ip_arria10_e3sge3_pll_clk25_altera_iopll_151;
+LIBRARY ip_arria10_e1sg_pll_clk25_altera_iopll_151;
ENTITY tech_pll_clk25 IS
GENERIC (
@@ -75,6 +76,19 @@ BEGIN
);
END GENERATE;
+ gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
+ u0 : ip_arria10_e1sg_pll_clk25
+ PORT MAP (
+ rst => areset,
+ refclk => inclk0,
+ outclk_0 => c0,
+ outclk_1 => c1,
+ outclk_2 => c2,
+ outclk_3 => c3,
+ locked => locked
+ );
+ END GENERATE;
+
gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
u0 : ip_stratixiv_pll_clk25
PORT MAP (
diff --git a/libraries/technology/pll/tech_pll_component_pkg.vhd b/libraries/technology/pll/tech_pll_component_pkg.vhd
index fab118242b..090f131329 100644
--- a/libraries/technology/pll/tech_pll_component_pkg.vhd
+++ b/libraries/technology/pll/tech_pll_component_pkg.vhd
@@ -229,6 +229,59 @@ PACKAGE tech_pll_component_pkg IS
);
END COMPONENT;
+ -----------------------------------------------------------------------------
+ -- ip_arria10_e1sg
+ -----------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_e1sg_pll_xgmii_mac_clocks IS
+ PORT (
+ pll_refclk0 : in std_logic := '0'; -- pll_refclk0.clk
+ pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
+ pll_locked : out std_logic; -- pll_locked.pll_locked
+ outclk0 : out std_logic; -- outclk0.clk
+ pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
+ outclk1 : out std_logic -- outclk1.clk
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e1sg_pll_clk200 IS
+ PORT
+ (
+ rst : IN STD_LOGIC := '0';
+ refclk : IN STD_LOGIC := '0';
+ outclk_0 : OUT STD_LOGIC ;
+ outclk_1 : OUT STD_LOGIC ;
+ outclk_2 : OUT STD_LOGIC ;
+ locked : OUT STD_LOGIC
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e1sg_pll_clk25 IS
+ PORT
+ (
+ rst : IN STD_LOGIC := '0';
+ refclk : IN STD_LOGIC := '0';
+ outclk_0 : OUT STD_LOGIC ;
+ outclk_1 : OUT STD_LOGIC ;
+ outclk_2 : OUT STD_LOGIC ;
+ outclk_3 : OUT STD_LOGIC ;
+ locked : OUT STD_LOGIC
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e1sg_pll_clk125 IS
+ PORT
+ (
+ rst : IN STD_LOGIC := '0';
+ refclk : IN STD_LOGIC := '0';
+ outclk_0 : OUT STD_LOGIC ;
+ outclk_1 : OUT STD_LOGIC ;
+ outclk_2 : OUT STD_LOGIC ;
+ outclk_3 : OUT STD_LOGIC ;
+ locked : OUT STD_LOGIC
+ );
+ END COMPONENT;
+
END tech_pll_component_pkg;
diff --git a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
index 7bc38df5ee..731530e585 100644
--- a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
+++ b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
@@ -43,6 +43,7 @@ USE common_lib.common_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_150;
LIBRARY ip_arria10_e3sge3_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151;
+LIBRARY ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151;
ENTITY tech_pll_xgmii_mac_clocks IS
GENERIC (
@@ -92,6 +93,18 @@ BEGIN
);
END GENERATE;
+ gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
+ u0 : ip_arria10_e1sg_pll_xgmii_mac_clocks
+ PORT MAP (
+ pll_refclk0 => refclk_644,
+ pll_powerdown => rst_in,
+ pll_locked => pll_locked,
+ outclk0 => i_clk_156,
+ pll_cal_busy => OPEN,
+ outclk1 => i_clk_312
+ );
+ END GENERATE;
+
pll_locked_n <= NOT pll_locked;
-- The delta-cycle difference in simulation between i_clk and output clk is no issue because i_clk is only used to create rst which is not clk cycle critical
diff --git a/libraries/technology/technology_pkg.vhd b/libraries/technology/technology_pkg.vhd
index 6225527c85..52b2a54043 100644
--- a/libraries/technology/technology_pkg.vhd
+++ b/libraries/technology/technology_pkg.vhd
@@ -47,7 +47,8 @@ PACKAGE technology_pkg IS
CONSTANT c_tech_virtex7 : INTEGER := 4; -- e.g. used on Roach3 for Casper
CONSTANT c_tech_arria10 : INTEGER := 5; -- e.g. used on UniBoard2 first proto (1 board version "00" may 2015)
CONSTANT c_tech_arria10_e3sge3 : INTEGER := 6; -- e.g. used on UniBoard2 second run (7 boards version "01" dec 2015)
- CONSTANT c_tech_nof_technologies : INTEGER := 7;
+ CONSTANT c_tech_arria10_e1sg : INTEGER := 7; -- e.g. used on UniBoard2 third run (5 'ARTS' boards version "01" feb 2017)
+ CONSTANT c_tech_nof_technologies : INTEGER := 8;
-- Functions
FUNCTION tech_sel_a_b(sel : BOOLEAN; a, b : STRING) RETURN STRING;
@@ -127,4 +128,4 @@ PACKAGE BODY technology_pkg IS
RETURN r;
END;
-END technology_pkg;
\ No newline at end of file
+END technology_pkg;
diff --git a/libraries/technology/tse/hdllib.cfg b/libraries/technology/tse/hdllib.cfg
index 2e38ea022f..e9dc7a5dab 100644
--- a/libraries/technology/tse/hdllib.cfg
+++ b/libraries/technology/tse/hdllib.cfg
@@ -4,6 +4,7 @@ hdl_lib_uses_synth = technology common dp
hdl_lib_uses_ip = ip_stratixiv_tse_sgmii_lvds ip_stratixiv_tse_sgmii_gx
ip_arria10_tse_sgmii_lvds ip_arria10_tse_sgmii_gx
ip_arria10_e3sge3_tse_sgmii_lvds ip_arria10_e3sge3_tse_sgmii_gx
+ ip_arria10_e1sg_tse_sgmii_lvds ip_arria10_e1sg_tse_sgmii_gx
hdl_lib_uses_sim = tech_transceiver
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
@@ -13,6 +14,8 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_tse_sgmii_gx ip_arria10_tse_sgmii_gx_altera_eth_tse_150
ip_arria10_e3sge3_tse_sgmii_lvds ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_151
ip_arria10_e3sge3_tse_sgmii_gx ip_arria10_e3sge3_tse_sgmii_gx_altera_eth_tse_151
+ ip_arria10_e1sg_tse_sgmii_lvds ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_151
+ ip_arria10_e1sg_tse_sgmii_gx ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_151
synth_files =
tech_tse_component_pkg.vhd
@@ -20,6 +23,7 @@ synth_files =
tech_tse_stratixiv.vhd
tech_tse_arria10.vhd
tech_tse_arria10_e3sge3.vhd
+ tech_tse_arria10_e1sg.vhd
sim_tse.vhd
tech_tse.vhd
tb_tech_tse_pkg.vhd
diff --git a/libraries/technology/tse/tech_tse.vhd b/libraries/technology/tse/tech_tse.vhd
index 064d5c5014..0fdc5bb4c4 100644
--- a/libraries/technology/tse/tech_tse.vhd
+++ b/libraries/technology/tse/tech_tse.vhd
@@ -123,6 +123,19 @@ BEGIN
tse_led);
END GENERATE;
+ gen_ip_arria10_e1sg : IF c_use_technology=TRUE AND g_technology=c_tech_arria10_e1sg GENERATE
+ u0 : ENTITY work.tech_tse_arria10_e1sg
+ GENERIC MAP (g_ETH_PHY)
+ PORT MAP (mm_rst, mm_clk, eth_clk, tx_snk_clk, rx_src_clk,
+ mm_sla_in, mm_sla_out,
+ tx_snk_in, tx_snk_out,
+ tx_mac_in, tx_mac_out,
+ rx_src_in, rx_src_out,
+ rx_mac_out,
+ eth_txp, eth_rxp,
+ tse_led);
+ END GENERATE;
+
gen_sim_tse : IF c_use_sim_model=TRUE GENERATE
u_sim_tse : ENTITY work.sim_tse
GENERIC MAP (g_sim_tx, g_sim_rx)
diff --git a/libraries/technology/tse/tech_tse_arria10_e1sg.vhd b/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
new file mode 100644
index 0000000000..7ff63e2531
--- /dev/null
+++ b/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
@@ -0,0 +1,256 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE work.tech_tse_component_pkg.ALL;
+USE work.tech_tse_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
+LIBRARY ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_151;
+LIBRARY ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_151;
+
+ENTITY tech_tse_arria10_e1sg IS
+ GENERIC (
+ g_ETH_PHY : STRING := "LVDS" -- "LVDS" (default): uses LVDS IOs for ctrl_unb2_board, "XCVR": uses tranceiver PHY
+ );
+ PORT (
+ -- Clocks and reset
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ eth_clk : IN STD_LOGIC;
+ tx_snk_clk : IN STD_LOGIC;
+ rx_src_clk : IN STD_LOGIC;
+
+ -- Memory Mapped Slave
+ mm_sla_in : IN t_mem_mosi;
+ mm_sla_out : OUT t_mem_miso;
+
+ -- MAC transmit interface
+ -- . ST sink
+ tx_snk_in : IN t_dp_sosi;
+ tx_snk_out : OUT t_dp_siso;
+ -- . MAC specific
+ tx_mac_in : IN t_tech_tse_tx_mac;
+ tx_mac_out : OUT t_tech_tse_tx_mac;
+
+ -- MAC receive interface
+ -- . ST Source
+ rx_src_in : IN t_dp_siso;
+ rx_src_out : OUT t_dp_sosi;
+ -- . MAC specific
+ rx_mac_out : OUT t_tech_tse_rx_mac;
+
+ -- PHY interface
+ eth_txp : OUT STD_LOGIC;
+ eth_rxp : IN STD_LOGIC;
+
+ tse_led : OUT t_tech_tse_led
+ );
+END tech_tse_arria10_e1sg;
+
+ARCHITECTURE str OF tech_tse_arria10_e1sg IS
+
+ SIGNAL ff_tx_mod : STD_LOGIC_VECTOR(c_tech_tse_empty_w-1 DOWNTO 0);
+
+ SIGNAL ff_rx_out : t_dp_sosi := c_dp_sosi_rst;
+
+BEGIN
+
+ -- Default frame level flow control
+ tx_snk_out.xon <= '1';
+
+ -- Force empty = 0 when eop = '0' to avoid TSE MAC bug of missing two bytes when empty = 2 (observed with v9.1)
+ ff_tx_mod <= tx_snk_in.empty(c_tech_tse_empty_w-1 DOWNTO 0) WHEN tx_snk_in.eop='1' ELSE (OTHERS=>'0');
+
+ -- Force unused bits and fields in rx_src_out to c_dp_sosi_rst to avoid confusing 'X' in wave window
+ rx_src_out <= ff_rx_out;
+
+ u_LVDS_tse: IF g_ETH_PHY = "LVDS" GENERATE
+
+ u_tse : ip_arria10_e1sg_tse_sgmii_lvds
+ -- The tse_sgmii_lvds needs to be regenerated if its parameters are changed.
+ -- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling
+ -- . ENABLE_SUP_ADDR = 0 : An extra MAC addresses can e.g. be used as service MAC for tests
+ -- . ENA_HASH = 0 : A multi cast hash table can be used to address all nodes at once
+ -- . STAT_CNT_ENA = 0 : PHY statistics counts are useful for monitoring, but not realy needed
+ -- . EG_FIFO = 256 : Tx FIFO depth in nof 32 bit words (256 --> 1 M9K)
+ -- . ING_FIFO = 256 : Rx FIFO depth in nof 32 bit words (256 --> 1 M9K)
+ -- . ENABLE_SGMII = 0 : PHY access 1000BASE-X
+ PORT MAP (
+ -- MAC transmit interface
+ -- . Avalon ST
+ ff_tx_clk => tx_snk_clk,
+ ff_tx_rdy => tx_snk_out.ready,
+ ff_tx_data => tx_snk_in.data(c_tech_tse_data_w-1 DOWNTO 0),
+ ff_tx_wren => tx_snk_in.valid,
+ ff_tx_sop => tx_snk_in.sop,
+ ff_tx_eop => tx_snk_in.eop,
+ ff_tx_mod => ff_tx_mod,
+ ff_tx_err => tx_snk_in.err(0),
+ -- . MAC specific
+ ff_tx_crc_fwd => tx_mac_in.crc_fwd, -- when '0' MAC inserts CRC32 after eop
+ ff_tx_septy => tx_mac_out.septy, -- when '0' then tx FIFO goes above section-empty threshold
+ ff_tx_a_full => tx_mac_out.a_full, -- when '1' then tx FIFO goes above almost-full threshold
+ ff_tx_a_empty => tx_mac_out.a_empty, -- when '1' then tx FIFO goes below almost-empty threshold
+ tx_ff_uflow => tx_mac_out.uflow, -- when '1' then tx FIFO underflow
+ -- MAC receive interface
+ -- . Avalon ST
+ ff_rx_clk => rx_src_clk,
+ ff_rx_rdy => rx_src_in.ready,
+ ff_rx_data => ff_rx_out.data(c_tech_tse_data_w-1 DOWNTO 0),
+ ff_rx_dval => ff_rx_out.valid,
+ ff_rx_sop => ff_rx_out.sop,
+ ff_rx_eop => ff_rx_out.eop,
+ ff_rx_mod => ff_rx_out.empty(c_tech_tse_empty_w-1 DOWNTO 0),
+ rx_err => ff_rx_out.err(c_tech_tse_error_w-1 DOWNTO 0), -- [5] collision error (can only occur in half duplex mode)
+ -- [4] PHY error on GMII
+ -- [3] receive frame truncated due to FIFO overflow
+ -- [2] CRC-32 error
+ -- [1] invalid length
+ -- [0] = OR of [1:5]
+ -- . MAC specific
+ rx_err_stat => rx_mac_out.ethertype, -- [17,16] VLAN info, [15:0] Ethernet lentgh/type field
+ rx_frm_type => rx_mac_out.frm_type, -- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
+ ff_rx_dsav => rx_mac_out.dsav, -- rx frame available, but not necessarily a complete frame
+ ff_rx_a_full => rx_mac_out.a_full, -- when '1' then rx FIFO goes above almost-full threshold
+ ff_rx_a_empty => rx_mac_out.a_empty, -- when '1' then rx FIFO goes below almost-empty threshold
+ -- Reset
+ reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
+ -- MM control interface
+ clk => mm_clk,
+ reg_addr => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
+ reg_data_out => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
+ reg_rd => mm_sla_in.rd,
+ reg_data_in => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
+ reg_wr => mm_sla_in.wr,
+ reg_busy => mm_sla_out.waitrequest,
+ -- Status LEDs
+ led_an => tse_led.an, -- '1' = autonegation completed
+ led_link => tse_led.link, -- '1' = successful link synchronisation
+ led_disp_err => tse_led.disp_err, -- TBI character error
+ led_char_err => tse_led.char_err, -- TBI disparity error
+ -- crs and col are only available with the SGMII bridge
+ led_crs => tse_led.crs, -- carrier sense '1' when there is tx/rx activity on the line
+ led_col => tse_led.col, -- tx collision detected (always '0' for full duplex)
+ -- Serial 1.25 Gbps
+ rx_recovclkout => OPEN,
+ ref_clk => eth_clk,
+ txp => eth_txp,
+ rxp => eth_rxp
+ );
+
+ END GENERATE;
+
+ u_XCVR_tse: IF g_ETH_PHY = "XCVR" GENERATE
+
+ u_tse : ip_arria10_e1sg_tse_sgmii_gx
+ -- The tse_sgmii_xcvr needs to be regenerated if its parameters are changed.
+ -- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling
+ -- . ENABLE_SUP_ADDR = 0 : An extra MAC addresses can e.g. be used as service MAC for tests
+ -- . ENA_HASH = 0 : A multi cast hash table can be used to address all nodes at once
+ -- . STAT_CNT_ENA = 0 : PHY statistics counts are useful for monitoring, but not realy needed
+ -- . EG_FIFO = 2048 : Tx FIFO depth in nof 32 bit words (2048 --> 4 M9K)
+ -- . ING_FIFO = 2048 : Rx FIFO depth in nof 32 bit words (2048 --> 4 M9K)
+ -- . ENABLE_SGMII = 0 : PHY access 1000BASE-X
+ PORT MAP (
+ -- MAC transmit interface
+ -- . Avalon ST
+ ff_tx_clk => tx_snk_clk,
+ ff_tx_rdy => tx_snk_out.ready,
+ ff_tx_data => tx_snk_in.data(c_tech_tse_data_w-1 DOWNTO 0),
+ ff_tx_wren => tx_snk_in.valid,
+ ff_tx_sop => tx_snk_in.sop,
+ ff_tx_eop => tx_snk_in.eop,
+ ff_tx_mod => ff_tx_mod,
+ ff_tx_err => tx_snk_in.err(0),
+ -- . MAC specific
+ ff_tx_crc_fwd => tx_mac_in.crc_fwd, -- when '0' MAC inserts CRC32 after eop
+ ff_tx_septy => tx_mac_out.septy, -- when '0' then tx FIFO goes above section-empty threshold
+ ff_tx_a_full => tx_mac_out.a_full, -- when '1' then tx FIFO goes above almost-full threshold
+ ff_tx_a_empty => tx_mac_out.a_empty, -- when '1' then tx FIFO goes below almost-empty threshold
+ tx_ff_uflow => tx_mac_out.uflow, -- when '1' then tx FIFO underflow
+ -- MAC receive interface
+ -- . Avalon ST
+ ff_rx_clk => rx_src_clk,
+ ff_rx_rdy => rx_src_in.ready,
+ ff_rx_data => ff_rx_out.data(c_tech_tse_data_w-1 DOWNTO 0),
+ ff_rx_dval => ff_rx_out.valid,
+ ff_rx_sop => ff_rx_out.sop,
+ ff_rx_eop => ff_rx_out.eop,
+ ff_rx_mod => ff_rx_out.empty(c_tech_tse_empty_w-1 DOWNTO 0),
+ rx_err => ff_rx_out.err(c_tech_tse_error_w-1 DOWNTO 0), -- [5] collision error (can only occur in half duplex mode)
+ -- [4] PHY error on GMII
+ -- [3] receive frame truncated due to FIFO overflow
+ -- [2] CRC-32 error
+ -- [1] invalid length
+ -- [0] = OR of [1:5]
+ -- . MAC specific
+ rx_err_stat => rx_mac_out.ethertype, -- [17,16] VLAN info, [15:0] Ethernet lentgh/type field
+ rx_frm_type => rx_mac_out.frm_type, -- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
+ ff_rx_dsav => rx_mac_out.dsav, -- rx frame available, but not necessarily a complete frame
+ ff_rx_a_full => rx_mac_out.a_full, -- when '1' then rx FIFO goes above almost-full threshold
+ ff_rx_a_empty => rx_mac_out.a_empty, -- when '1' then rx FIFO goes below almost-empty threshold
+ -- Reset
+ reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
+ -- MM control interface
+ clk => mm_clk,
+ reg_addr => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
+ reg_data_out => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
+ reg_rd => mm_sla_in.rd,
+ reg_data_in => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
+ reg_wr => mm_sla_in.wr,
+ reg_busy => mm_sla_out.waitrequest,
+ -- Status LEDs
+ led_an => tse_led.an, -- '1' = autonegation completed
+ led_link => tse_led.link, -- '1' = successful link synchronisation
+ led_disp_err => tse_led.disp_err, -- TBI character error
+ led_char_err => tse_led.char_err, -- TBI disparity error
+ -- crs and col are only available with the SGMII bridge
+ led_crs => tse_led.crs, -- carrier sense '1' when there is tx/rx activity on the line
+ led_col => tse_led.col, -- tx collision detected (always '0' for full duplex)
+ -- Serial 1.25 Gbps
+ rx_recovclkout => OPEN,
+ ref_clk => eth_clk,
+ txp => eth_txp,
+ rxp => eth_rxp,
+
+ -- GX connections ????
+ tx_serial_clk => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_serial_clk.clk
+ rx_cdr_refclk => '0', -- : in std_logic := '0'; -- rx_cdr_refclk.clk
+ tx_analogreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_digitalreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ rx_analogreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_digitalreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ tx_cal_busy => OPEN, -- : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy
+ rx_cal_busy => OPEN, -- : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_set_locktodata => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktodata.rx_set_locktodata
+ rx_set_locktoref => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktoref.rx_set_locktoref
+ rx_is_lockedtoref => OPEN, -- : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtodata => OPEN -- : out std_logic_vector(0 downto 0) -- rx_is_lockedtodata.rx_is_lockedtodata
+ );
+
+ END GENERATE;
+
+END str;
diff --git a/libraries/technology/tse/tech_tse_component_pkg.vhd b/libraries/technology/tse/tech_tse_component_pkg.vhd
index f01da8f8fc..9a92d12862 100644
--- a/libraries/technology/tse/tech_tse_component_pkg.vhd
+++ b/libraries/technology/tse/tech_tse_component_pkg.vhd
@@ -262,7 +262,7 @@ PACKAGE tech_tse_component_pkg IS
------------------------------------------------------------------------------
- -- ip_arria10
+ -- ip_arria10_e3sge3
------------------------------------------------------------------------------
-- Copied from $RADIOHDL/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/generated/sim/ip_arria10_e3sge3_tse_sgmii_lvds.vhd
@@ -379,5 +379,122 @@ PACKAGE tech_tse_component_pkg IS
);
END COMPONENT;
+ ------------------------------------------------------------------------------
+ -- ip_arria10_e1sg
+ ------------------------------------------------------------------------------
+
+ -- Copied from $RADIOHDL/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim/ip_arria10_e1sg_tse_sgmii_lvds.vhd
+ COMPONENT ip_arria10_e1sg_tse_sgmii_lvds IS
+ PORT (
+ reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
+ reg_rd : in std_logic := '0'; -- .read
+ reg_data_in : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reg_wr : in std_logic := '0'; -- .write
+ reg_busy : out std_logic; -- .waitrequest
+ reg_addr : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
+ clk : in std_logic := '0'; -- control_port_clock_connection.clk
+ ff_tx_crc_fwd : in std_logic := '0'; -- mac_misc_connection.ff_tx_crc_fwd
+ ff_tx_septy : out std_logic; -- .ff_tx_septy
+ tx_ff_uflow : out std_logic; -- .tx_ff_uflow
+ ff_tx_a_full : out std_logic; -- .ff_tx_a_full
+ ff_tx_a_empty : out std_logic; -- .ff_tx_a_empty
+ rx_err_stat : out std_logic_vector(17 downto 0); -- .rx_err_stat
+ rx_frm_type : out std_logic_vector(3 downto 0); -- .rx_frm_type
+ ff_rx_dsav : out std_logic; -- .ff_rx_dsav
+ ff_rx_a_full : out std_logic; -- .ff_rx_a_full
+ ff_rx_a_empty : out std_logic; -- .ff_rx_a_empty
+ ref_clk : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk
+ ff_rx_data : out std_logic_vector(31 downto 0); -- receive.data
+ ff_rx_eop : out std_logic; -- .endofpacket
+ rx_err : out std_logic_vector(5 downto 0); -- .error
+ ff_rx_mod : out std_logic_vector(1 downto 0); -- .empty
+ ff_rx_rdy : in std_logic := '0'; -- .ready
+ ff_rx_sop : out std_logic; -- .startofpacket
+ ff_rx_dval : out std_logic; -- .valid
+ ff_rx_clk : in std_logic := '0'; -- receive_clock_connection.clk
+ reset : in std_logic := '0'; -- reset_connection.reset
+ rx_recovclkout : out std_logic; -- serdes_control_connection.export
+ rxp : in std_logic := '0'; -- serial_connection.rxp_0
+ txp : out std_logic; -- .txp_0
+ led_crs : out std_logic; -- status_led_connection.crs
+ led_link : out std_logic; -- .link
+ led_col : out std_logic; -- .col
+ led_an : out std_logic; -- .an
+ led_char_err : out std_logic; -- .char_err
+ led_disp_err : out std_logic; -- .disp_err
+ ff_tx_data : in std_logic_vector(31 downto 0) := (others => '0'); -- transmit.data
+ ff_tx_eop : in std_logic := '0'; -- .endofpacket
+ ff_tx_err : in std_logic := '0'; -- .error
+ ff_tx_mod : in std_logic_vector(1 downto 0) := (others => '0'); -- .empty
+ ff_tx_rdy : out std_logic; -- .ready
+ ff_tx_sop : in std_logic := '0'; -- .startofpacket
+ ff_tx_wren : in std_logic := '0'; -- .valid
+ ff_tx_clk : in std_logic := '0' -- transmit_clock_connection.clk
+ );
+ END COMPONENT;
+
+
+ -- Copied from $RADIOHDL/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim/ip_arria10_e1sg_tse_sgmii_gx.vhd
+ COMPONENT ip_arria10_e1sg_tse_sgmii_gx IS
+ PORT (
+ reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
+ reg_rd : in std_logic := '0'; -- .read
+ reg_data_in : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reg_wr : in std_logic := '0'; -- .write
+ reg_busy : out std_logic; -- .waitrequest
+ reg_addr : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
+ clk : in std_logic := '0'; -- control_port_clock_connection.clk
+ ff_tx_crc_fwd : in std_logic := '0'; -- mac_misc_connection.ff_tx_crc_fwd
+ ff_tx_septy : out std_logic; -- .ff_tx_septy
+ tx_ff_uflow : out std_logic; -- .tx_ff_uflow
+ ff_tx_a_full : out std_logic; -- .ff_tx_a_full
+ ff_tx_a_empty : out std_logic; -- .ff_tx_a_empty
+ rx_err_stat : out std_logic_vector(17 downto 0); -- .rx_err_stat
+ rx_frm_type : out std_logic_vector(3 downto 0); -- .rx_frm_type
+ ff_rx_dsav : out std_logic; -- .ff_rx_dsav
+ ff_rx_a_full : out std_logic; -- .ff_rx_a_full
+ ff_rx_a_empty : out std_logic; -- .ff_rx_a_empty
+ ref_clk : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk
+ ff_rx_data : out std_logic_vector(31 downto 0); -- receive.data
+ ff_rx_eop : out std_logic; -- .endofpacket
+ rx_err : out std_logic_vector(5 downto 0); -- .error
+ ff_rx_mod : out std_logic_vector(1 downto 0); -- .empty
+ ff_rx_rdy : in std_logic := '0'; -- .ready
+ ff_rx_sop : out std_logic; -- .startofpacket
+ ff_rx_dval : out std_logic; -- .valid
+ ff_rx_clk : in std_logic := '0'; -- receive_clock_connection.clk
+ reset : in std_logic := '0'; -- reset_connection.reset
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cdr_refclk : in std_logic := '0'; -- rx_cdr_refclk.clk
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtoref : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_set_locktodata : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktodata.rx_set_locktodata
+ rx_set_locktoref : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktoref.rx_set_locktoref
+ rx_recovclkout : out std_logic; -- serdes_control_connection.export
+ rxp : in std_logic := '0'; -- serial_connection.rxp
+ txp : out std_logic; -- .txp
+ led_crs : out std_logic; -- status_led_connection.crs
+ led_link : out std_logic; -- .link
+ led_panel_link : out std_logic; -- .panel_link
+ led_col : out std_logic; -- .col
+ led_an : out std_logic; -- .an
+ led_char_err : out std_logic; -- .char_err
+ led_disp_err : out std_logic; -- .disp_err
+ ff_tx_data : in std_logic_vector(31 downto 0) := (others => '0'); -- transmit.data
+ ff_tx_eop : in std_logic := '0'; -- .endofpacket
+ ff_tx_err : in std_logic := '0'; -- .error
+ ff_tx_mod : in std_logic_vector(1 downto 0) := (others => '0'); -- .empty
+ ff_tx_rdy : out std_logic; -- .ready
+ ff_tx_sop : in std_logic := '0'; -- .startofpacket
+ ff_tx_wren : in std_logic := '0'; -- .valid
+ ff_tx_clk : in std_logic := '0'; -- transmit_clock_connection.clk
+ tx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_serial_clk : in std_logic_vector(0 downto 0) := (others => '0') -- tx_serial_clk.clk
+ );
+ END COMPONENT;
END tech_tse_component_pkg;
--
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